Attachment #15482 for bug #28692

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#define AC97_POWER_PINREADY  0x0001
#define AC97_POWER_POUTPOWER 0x0200
#define AC97_POWER_POUTREADY 0x0002
#define AC97_POWER_D3	0xFF00

/* play/record buffer */
#define ICH_FIFOINDEX 32

	struct ich_desc *index;
	bus_dmamap_t imap;
	u_int32_t lvi;
	int run_save;
};

/* device private data */

/* -------------------------------------------------------------------- */
/* Hardware */
static u_int32_t
ich_rd_1(struct sc_info *sc, int regno)
{
	return bus_space_read_1(sc->nambart, sc->nambarh, regno);
	case 1:
		return bus_space_read_1(sc->nambart, sc->nambarh, regno);
	case 2:
		return bus_space_read_2(sc->nambart, sc->nambarh, regno);
	case 4:
		return bus_space_read_4(sc->nambart, sc->nambarh, regno);
	default:
		return 0xffffffff;
	}
}

static u_int32_t
ich_rd_2(struct sc_info *sc, int regno)
{
	return bus_space_read_2(sc->nambart, sc->nambarh, regno);
}

static u_int32_t
ich_rd_4(struct sc_info *sc, int regno)
{
	return bus_space_read_4(sc->nambart, sc->nambarh, regno);
}

#define ich_rd(sc, regno, size)	ich_rd_ ## size (sc, regno)

static void
ich_wr_1(struct sc_info *sc, int regno, u_int32_t data)
{
	bus_space_write_1(sc->nambart, sc->nambarh, regno, data);
	case 1:
		bus_space_write_1(sc->nambart, sc->nambarh, regno, data);
		break;
	case 2:
		bus_space_write_2(sc->nambart, sc->nambarh, regno, data);
		break;
	case 4:
		bus_space_write_4(sc->nambart, sc->nambarh, regno, data);
		break;
	}
}

static void
ich_wr_2(struct sc_info *sc, int regno, u_int32_t data)
{
	bus_space_write_2(sc->nambart, sc->nambarh, regno, data);
}

static void
ich_wr_4(struct sc_info *sc, int regno, u_int32_t data)
{
	bus_space_write_4(sc->nambart, sc->nambarh, regno, data);
}

#define ich_wr(sc,regno,data,size)	ich_wr_ ## size (sc,regno, data)

/* ac97 codec */
static int
ich_waitcd(void *devinfo)

	ch->parent = sc;
	ch->dir = PCMDIR_PLAY;
	ch->run = 0;
	ch->run_save = 0;
	ch->lvi = 0;
	if (ichchan_initbuf(ch)) {
		device_printf(sc->dev, "cannot allocate channel buffer\n");

#if(0)
		device_printf(ch->parent->dev, "ichpchan_trigger():PCMTRIG_START\n");
#endif
		if (ch->run > 0) {
			return 0;
		}
		ch->run = 1;
		ichpchan_power(obj, sc, 1);
		bus_space_write_4(sc->nabmbart, sc->nabmbarh, ICH_REG_PO_BDBAR,

#if(0)
		device_printf(ch->parent->dev, "ichpchan_trigger():PCMTRIG_STOP\n");
#endif
		if (ch->run <= 0) {
			return 0;
		}
		cr = bus_space_read_1(sc->nabmbart, sc->nabmbarh,
		    ICH_REG_PO_CR);
		bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PO_CR,

#if(0)
		device_printf(ch->parent->dev, "ichpchan_trigger():PCMTRIG_ABORT\n");
#endif
		if (ch->run < 0) {
			return 0;
		}
		bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PO_CR,
		    0);
		bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PO_CR,

				break;
		}
		ichpchan_power(obj, sc, 0);
		ch->run = -1;
		ch->lvi = 0;
		break;
	default:

	ch->parent = sc;
	ch->dir = PCMDIR_REC;
	ch->run = 0;
	ch->run_save = 0;
	ch->lvi = 0;
	if (ichchan_initbuf(ch)) {
		device_printf(sc->dev, "cannot allocate channel buffer\n");


	switch (go) {
	case PCMTRIG_START:
		if (ch->run > 0) {
			return 0;
		}
		ch->run = 1;
		ichrchan_power(obj, sc, 1);
		bus_space_write_4(sc->nabmbart, sc->nabmbarh, ICH_REG_PI_BDBAR,

		    ICH_X_CR_FEIE);
		break;
	case PCMTRIG_STOP:
		if (ch->run <= 0) {
			return 0;
		}
		cr = bus_space_read_1(sc->nabmbart, sc->nabmbarh,
		    ICH_REG_PI_CR);
		bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PI_CR,

		ch->run = 0;
		break;
	case PCMTRIG_ABORT:
		if (ch->run < 0) {
			return 0;
		}
		bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PI_CR,
		    0);
		bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PI_CR,

				break;
		}
		ichrchan_power(obj, sc, 0);
		ch->run = -1;
		ch->lvi = 0;
		break;
	default:

	u_int32_t stat;
	u_int32_t save;

	bus_space_write_4(sc->nabmbart, sc->nabmbarh,  ICH_REG_GLOB_CNT, 0);
	DELAY(10);
	bus_space_write_4(sc->nabmbart, sc->nabmbarh,
	    ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD);
	DELAY(600000);

}

static int
ich_pci_suspend(device_t dev)
{
	struct sc_info *sc;
	u_int32_t cr;

	sc = pcm_getdevinfo(dev);

	sc->po->run_save = sc->po->run;
	sc->pi->run_save = sc->pi->run;
	if (sc->po->run > 0) {
		ichpchan_trigger(NULL,sc->po,  PCMTRIG_STOP);
	}
	if (sc->pi->run > 0) {
		ichrchan_trigger(NULL, sc->pi, PCMTRIG_STOP);
	}
        
	/* CODEC power off */
	cr = ich_rdcd(NULL, sc, AC97_REG_POWER);
	cr |=  AC97_POWER_D3;
	ich_wrcd(NULL, sc, AC97_REG_POWER, cr);
	/* ACLINK shut off */
	ich_wr(sc,ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_SHUT, 4);

	return 0;
}

static int
ich_pci_resume(device_t dev)
{
	struct sc_info *sc;

		device_printf(dev, "unable to reinitialize the mixer\n");
		return ENXIO;
	}

	if (sc->po->run_save > 0) {
		ichpchan_trigger(NULL, sc->po, PCMTRIG_START);
	}       
	if (sc->pi->run_save > 0) {
		ichrchan_trigger(NULL, sc->pi, PCMTRIG_START);
	}

	return 0;
}


	DEVMETHOD(device_probe,		ich_pci_probe),
	DEVMETHOD(device_attach,	ich_pci_attach),
	DEVMETHOD(device_detach,	ich_pci_detach),
	DEVMETHOD(device_suspend, 	ich_pci_suspend),
	DEVMETHOD(device_resume,	ich_pci_resume),
	{ 0, 0 }
};

Return to bug 28692

Lines 108-113 Link Here

(-)ich.c (-25 / +94 lines)
108	#define AC97_POWER_PINREADY 0x0001	108	#define AC97_POWER_PINREADY 0x0001
109	#define AC97_POWER_POUTPOWER 0x0200	109	#define AC97_POWER_POUTPOWER 0x0200
110	#define AC97_POWER_POUTREADY 0x0002	110	#define AC97_POWER_POUTREADY 0x0002
		111	#define AC97_POWER_D3 0xFF00
111		112
112	/* play/record buffer */	113	/* play/record buffer */
113	#define ICH_FIFOINDEX 32	114	#define ICH_FIFOINDEX 32
Lines 131-136 Link Here
131	struct ich_desc *index;	132	struct ich_desc *index;
132	bus_dmamap_t imap;	133	bus_dmamap_t imap;
133	u_int32_t lvi;	134	u_int32_t lvi;
		135	int run_save;
134	};	136	};
135		137
136	/* device private data */	138	/* device private data */
Lines 212-247 Link Here
212	/* -------------------------------------------------------------------- */	214	/* -------------------------------------------------------------------- */
213	/* Hardware */	215	/* Hardware */
214	static u_int32_t	216	static u_int32_t
215	ich_rd(struct sc_info *sc, int regno, int size)	217	ich_rd_1(struct sc_info *sc, int regno)
216	{	218	{
217	switch (size) {	219	return bus_space_read_1(sc->nambart, sc->nambarh, regno);
218	case 1:
219	return bus_space_read_1(sc->nambart, sc->nambarh, regno);
220	case 2:
221	return bus_space_read_2(sc->nambart, sc->nambarh, regno);
222	case 4:
223	return bus_space_read_4(sc->nambart, sc->nambarh, regno);
224	default:
225	return 0xffffffff;
226	}
227	}	220	}
228		221
		222	static u_int32_t
		223	ich_rd_2(struct sc_info *sc, int regno)
		224	{
		225	return bus_space_read_2(sc->nambart, sc->nambarh, regno);
		226	}
		227
		228	static u_int32_t
		229	ich_rd_4(struct sc_info *sc, int regno)
		230	{
		231	return bus_space_read_4(sc->nambart, sc->nambarh, regno);
		232	}
		233
		234	#define ich_rd(sc, regno, size) ich_rd_ ## size (sc, regno)
		235
229	static void	236	static void
230	ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size)	237	ich_wr_1(struct sc_info *sc, int regno, u_int32_t data)
231	{	238	{
232	switch (size) {	239	bus_space_write_1(sc->nambart, sc->nambarh, regno, data);
233	case 1:
234	bus_space_write_1(sc->nambart, sc->nambarh, regno, data);
235	break;
236	case 2:
237	bus_space_write_2(sc->nambart, sc->nambarh, regno, data);
238	break;
239	case 4:
240	bus_space_write_4(sc->nambart, sc->nambarh, regno, data);
241	break;
242	}
243	}	240	}
244		241
		242	static void
		243	ich_wr_2(struct sc_info *sc, int regno, u_int32_t data)
		244	{
		245	bus_space_write_2(sc->nambart, sc->nambarh, regno, data);
		246	}
		247
		248	static void
		249	ich_wr_4(struct sc_info *sc, int regno, u_int32_t data)
		250	{
		251	bus_space_write_4(sc->nambart, sc->nambarh, regno, data);
		252	}
		253
		254	#define ich_wr(sc,regno,data,size) ich_wr_ ## size (sc,regno, data)
		255
245	/* ac97 codec */	256	/* ac97 codec */
246	static int	257	static int
247	ich_waitcd(void *devinfo)	258	ich_waitcd(void *devinfo)
Lines 423-428 Link Here
423	ch->parent = sc;	434	ch->parent = sc;
424	ch->dir = PCMDIR_PLAY;	435	ch->dir = PCMDIR_PLAY;
425	ch->run = 0;	436	ch->run = 0;
		437	ch->run_save = 0;
426	ch->lvi = 0;	438	ch->lvi = 0;
427	if (ichchan_initbuf(ch)) {	439	if (ichchan_initbuf(ch)) {
428	device_printf(sc->dev, "cannot allocate channel buffer\n");	440	device_printf(sc->dev, "cannot allocate channel buffer\n");
Lines 555-560 Link Here
555	#if(0)	567	#if(0)
556	device_printf(ch->parent->dev, "ichpchan_trigger():PCMTRIG_START\n");	568	device_printf(ch->parent->dev, "ichpchan_trigger():PCMTRIG_START\n");
557	#endif	569	#endif
		570	if (ch->run > 0) {
		571	return 0;
		572	}
558	ch->run = 1;	573	ch->run = 1;
559	ichpchan_power(obj, sc, 1);	574	ichpchan_power(obj, sc, 1);
560	bus_space_write_4(sc->nabmbart, sc->nabmbarh, ICH_REG_PO_BDBAR,	575	bus_space_write_4(sc->nabmbart, sc->nabmbarh, ICH_REG_PO_BDBAR,
Lines 569-574 Link Here
569	#if(0)	584	#if(0)
570	device_printf(ch->parent->dev, "ichpchan_trigger():PCMTRIG_STOP\n");	585	device_printf(ch->parent->dev, "ichpchan_trigger():PCMTRIG_STOP\n");
571	#endif	586	#endif
		587	if (ch->run <= 0) {
		588	return 0;
		589	}
572	cr = bus_space_read_1(sc->nabmbart, sc->nabmbarh,	590	cr = bus_space_read_1(sc->nabmbart, sc->nabmbarh,
573	ICH_REG_PO_CR);	591	ICH_REG_PO_CR);
574	bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PO_CR,	592	bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PO_CR,
Lines 580-585 Link Here
580	#if(0)	598	#if(0)
581	device_printf(ch->parent->dev, "ichpchan_trigger():PCMTRIG_ABORT\n");	599	device_printf(ch->parent->dev, "ichpchan_trigger():PCMTRIG_ABORT\n");
582	#endif	600	#endif
		601	if (ch->run < 0) {
		602	return 0;
		603	}
583	bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PO_CR,	604	bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PO_CR,
584	0);	605	0);
585	bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PO_CR,	606	bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PO_CR,
Lines 591-597 Link Here
591	break;	612	break;
592	}	613	}
593	ichpchan_power(obj, sc, 0);	614	ichpchan_power(obj, sc, 0);
594	ch->run = 0;	615	ch->run = -1;
595	ch->lvi = 0;	616	ch->lvi = 0;
596	break;	617	break;
597	default:	618	default:
Lines 722-727 Link Here
722	ch->parent = sc;	743	ch->parent = sc;
723	ch->dir = PCMDIR_REC;	744	ch->dir = PCMDIR_REC;
724	ch->run = 0;	745	ch->run = 0;
		746	ch->run_save = 0;
725	ch->lvi = 0;	747	ch->lvi = 0;
726	if (ichchan_initbuf(ch)) {	748	if (ichchan_initbuf(ch)) {
727	device_printf(sc->dev, "cannot allocate channel buffer\n");	749	device_printf(sc->dev, "cannot allocate channel buffer\n");
Lines 796-801 Link Here
796		818
797	switch (go) {	819	switch (go) {
798	case PCMTRIG_START:	820	case PCMTRIG_START:
		821	if (ch->run > 0) {
		822	return 0;
		823	}
799	ch->run = 1;	824	ch->run = 1;
800	ichrchan_power(obj, sc, 1);	825	ichrchan_power(obj, sc, 1);
801	bus_space_write_4(sc->nabmbart, sc->nabmbarh, ICH_REG_PI_BDBAR,	826	bus_space_write_4(sc->nabmbart, sc->nabmbarh, ICH_REG_PI_BDBAR,
Lines 808-813 Link Here
808	ICH_X_CR_FEIE);	833	ICH_X_CR_FEIE);
809	break;	834	break;
810	case PCMTRIG_STOP:	835	case PCMTRIG_STOP:
		836	if (ch->run <= 0) {
		837	return 0;
		838	}
811	cr = bus_space_read_1(sc->nabmbart, sc->nabmbarh,	839	cr = bus_space_read_1(sc->nabmbart, sc->nabmbarh,
812	ICH_REG_PI_CR);	840	ICH_REG_PI_CR);
813	bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PI_CR,	841	bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PI_CR,
Lines 816-821 Link Here
816	ch->run = 0;	844	ch->run = 0;
817	break;	845	break;
818	case PCMTRIG_ABORT:	846	case PCMTRIG_ABORT:
		847	if (ch->run < 0) {
		848	return 0;
		849	}
819	bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PI_CR,	850	bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PI_CR,
820	0);	851	0);
821	bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PI_CR,	852	bus_space_write_1(sc->nabmbart, sc->nabmbarh, ICH_REG_PI_CR,
Lines 827-833 Link Here
827	break;	858	break;
828	}	859	}
829	ichrchan_power(obj, sc, 0);	860	ichrchan_power(obj, sc, 0);
830	ch->run = 0;	861	ch->run = -1;
831	ch->lvi = 0;	862	ch->lvi = 0;
832	break;	863	break;
833	default:	864	default:
Lines 984-989 Link Here
984	u_int32_t stat;	1015	u_int32_t stat;
985	u_int32_t save;	1016	u_int32_t save;
986		1017
		1018	bus_space_write_4(sc->nabmbart, sc->nabmbarh, ICH_REG_GLOB_CNT, 0);
		1019	DELAY(10);
987	bus_space_write_4(sc->nabmbart, sc->nabmbarh,	1020	bus_space_write_4(sc->nabmbart, sc->nabmbarh,
988	ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD);	1021	ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD);
989	DELAY(600000);	1022	DELAY(600000);
Lines 1164-1169 Link Here
1164	}	1197	}
1165		1198
1166	static int	1199	static int
		1200	ich_pci_suspend(device_t dev)
		1201	{
		1202	struct sc_info *sc;
		1203	u_int32_t cr;
		1204
		1205	sc = pcm_getdevinfo(dev);
		1206
		1207	sc->po->run_save = sc->po->run;
		1208	sc->pi->run_save = sc->pi->run;
		1209	if (sc->po->run > 0) {
		1210	ichpchan_trigger(NULL,sc->po, PCMTRIG_STOP);
		1211	}
		1212	if (sc->pi->run > 0) {
		1213	ichrchan_trigger(NULL, sc->pi, PCMTRIG_STOP);
		1214	}
		1215
		1216	/* CODEC power off */
		1217	cr = ich_rdcd(NULL, sc, AC97_REG_POWER);
		1218	cr \|= AC97_POWER_D3;
		1219	ich_wrcd(NULL, sc, AC97_REG_POWER, cr);
		1220	/* ACLINK shut off */
		1221	ich_wr(sc,ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD \| ICH_GLOB_CTL_SHUT, 4);
		1222
		1223	return 0;
		1224	}
		1225
		1226	static int
1167	ich_pci_resume(device_t dev)	1227	ich_pci_resume(device_t dev)
1168	{	1228	{
1169	struct sc_info *sc;	1229	struct sc_info *sc;
Lines 1180-1185 Link Here
1180	device_printf(dev, "unable to reinitialize the mixer\n");	1240	device_printf(dev, "unable to reinitialize the mixer\n");
1181	return ENXIO;	1241	return ENXIO;
1182	}	1242	}
		1243
		1244	if (sc->po->run_save > 0) {
		1245	ichpchan_trigger(NULL, sc->po, PCMTRIG_START);
		1246	}
		1247	if (sc->pi->run_save > 0) {
		1248	ichrchan_trigger(NULL, sc->pi, PCMTRIG_START);
		1249	}
		1250
1183	return 0;	1251	return 0;
1184	}	1252	}
1185		1253
Lines 1188-1193 Link Here
1188	DEVMETHOD(device_probe, ich_pci_probe),	1256	DEVMETHOD(device_probe, ich_pci_probe),
1189	DEVMETHOD(device_attach, ich_pci_attach),	1257	DEVMETHOD(device_attach, ich_pci_attach),
1190	DEVMETHOD(device_detach, ich_pci_detach),	1258	DEVMETHOD(device_detach, ich_pci_detach),
		1259	DEVMETHOD(device_suspend, ich_pci_suspend),
1191	DEVMETHOD(device_resume, ich_pci_resume),	1260	DEVMETHOD(device_resume, ich_pci_resume),
1192	{ 0, 0 }	1261	{ 0, 0 }
1193	};	1262	};