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Lines 175-180
ahci_attach(device_t dev)
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| 175 |
resource_int_value(device_get_name(dev), |
175 |
resource_int_value(device_get_name(dev), |
| 176 |
device_get_unit(dev), "ccc", &ctlr->ccc); |
176 |
device_get_unit(dev), "ccc", &ctlr->ccc); |
| 177 |
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177 |
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178 |
device_printf(dev, "quirks1=0x%b\n", ctlr->quirks, AHCI_Q_BIT_STRING); |
| 178 |
/* Setup our own memory management for channels. */ |
179 |
/* Setup our own memory management for channels. */ |
| 179 |
ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); |
180 |
ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); |
| 180 |
ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); |
181 |
ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); |
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Lines 190-195
ahci_attach(device_t dev)
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| 190 |
rman_fini(&ctlr->sc_iomem); |
191 |
rman_fini(&ctlr->sc_iomem); |
| 191 |
return (error); |
192 |
return (error); |
| 192 |
} |
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} |
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194 |
device_printf(dev, "quirks2=0x%b\n", ctlr->quirks, AHCI_Q_BIT_STRING); |
| 193 |
/* Get the HW capabilities */ |
195 |
/* Get the HW capabilities */ |
| 194 |
version = ATA_INL(ctlr->r_mem, AHCI_VS); |
196 |
version = ATA_INL(ctlr->r_mem, AHCI_VS); |
| 195 |
ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); |
197 |
ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); |
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Lines 212-217
ahci_attach(device_t dev)
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| 212 |
device_printf(dev, "Forcing PI to %d ports (mask = %x)\n", |
214 |
device_printf(dev, "Forcing PI to %d ports (mask = %x)\n", |
| 213 |
nports, nmask); |
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nports, nmask); |
| 214 |
} |
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} |
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217 |
device_printf(dev, "quirks3=0x%b\n", ctlr->quirks, AHCI_Q_BIT_STRING); |
| 215 |
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218 |
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| 216 |
ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); |
219 |
ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); |
| 217 |
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220 |
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Lines 234-239
ahci_attach(device_t dev)
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| 234 |
ctlr->caps |= 3; |
237 |
ctlr->caps |= 3; |
| 235 |
ctlr->ichannels &= 0x0f; |
238 |
ctlr->ichannels &= 0x0f; |
| 236 |
} |
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} |
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240 |
device_printf(dev, "quirks4=0x%b\n", ctlr->quirks, AHCI_Q_BIT_STRING); |
| 237 |
ctlr->channels = MAX(flsl(ctlr->ichannels), |
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ctlr->channels = MAX(flsl(ctlr->ichannels), |
| 238 |
(ctlr->caps & AHCI_CAP_NPMASK) + 1); |
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(ctlr->caps & AHCI_CAP_NPMASK) + 1); |
| 239 |
if (ctlr->quirks & AHCI_Q_NOPMP) |
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if (ctlr->quirks & AHCI_Q_NOPMP) |
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Lines 255-260
ahci_attach(device_t dev)
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| 255 |
rman_fini(&ctlr->sc_iomem); |
259 |
rman_fini(&ctlr->sc_iomem); |
| 256 |
return (ENXIO); |
260 |
return (ENXIO); |
| 257 |
} |
261 |
} |
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262 |
device_printf(dev, "quirks5=0x%b\n", ctlr->quirks, AHCI_Q_BIT_STRING); |
| 258 |
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| 259 |
ahci_ctlr_setup(dev); |
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ahci_ctlr_setup(dev); |
| 260 |
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265 |
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Lines 266-271
ahci_attach(device_t dev)
Link Here
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| 266 |
rman_fini(&ctlr->sc_iomem); |
271 |
rman_fini(&ctlr->sc_iomem); |
| 267 |
return (error); |
272 |
return (error); |
| 268 |
} |
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} |
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274 |
device_printf(dev, "quirks6=0x%b\n", ctlr->quirks, AHCI_Q_BIT_STRING); |
| 269 |
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| 270 |
i = 0; |
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i = 0; |
| 271 |
for (u = ctlr->ichannels; u != 0; u >>= 1) |
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for (u = ctlr->ichannels; u != 0; u >>= 1) |