Attachment #158572 for bug #199495

Lines 16-21 from older versions of FreeBSD, try WITHOUT_CLANG Link Here

(-)UPDATING (+6 lines)
16	stable/10, and then rebuild without this option. The bootstrap process from	16	stable/10, and then rebuild without this option. The bootstrap process from
17	older version of current is a bit fragile.	17	older version of current is a bit fragile.
18		18
		19	20150709:
		20	From legacy ata(4) driver was removed support for SATA controllers
		21	supported by more functional drivers ahci(4), siis(4) and mvs(4).
		22	Kernel modules ataahci and ataadaptec were removed completely,
		23	replaced by ahci and mvs modules respectively.
		24
19	20150624:	25	20150624:
20	An additional fix for the issue described in the 20150614 sendmail	26	An additional fix for the issue described in the 20150614 sendmail
21	entry below has been been committed in revision 284786.	27	entry below has been been committed in revision 284786.




Supporting AHCI controllers may transmit that information to the backplane
controllers via SGPIO interface. Backplane controllers interpret received
statuses in some way (IBPI standard) to report them using present indicators.
.Pp
AHCI hardware is also supported by ataahci driver from
.Xr ata 4
subsystem.
If both drivers are loaded at the same time, this one will be
given precedence as the more functional of the two.
.Sh HARDWARE
The
.Nm




.\"
.\" $FreeBSD$
.\"
.Dd March 23, 2015
.Dt ATA 4
.Os
.Sh NAME


ataacard_load="YES"
ataacerlabs_load="YES"
ataadaptec_load="YES"
ataahci_load="YES"
ataamd_load="YES"
ataati_load="YES"
atacenatek_load="YES"

The first line is for the common hardware independent code, and is a
prerequisite for the other modules.
The next three lines are generic bus-specific drivers.
The rest are vendor-specific PCI drivers.
The others are vendor-specific PCI drivers.
.Pp
The following tunables are settable from the
.Xr loader 8 :
.Bl -ohang
.It Va hw.ahci.force
set to nonzero value for forcing drivers to attach to some known AHCI-capable
chips even if they are configured for legacy IDE emulation (the default is 1,
force the attach).
.It Va hw.ata.ata_dma_check_80pin
set to 0 to disable the 80pin cable check (the default is 1, check the cable).
.It Va hint.atapci.X.msi

This is the default value.
.It 1
The device is allowed to initiate a PM state change; the host is passive.
.It 2
The host initiates a PARTIAL PM state transition every time a port becomes idle.
.It 3
host initiates SLUMBER PM state transition every time port becomes idle.
.El
.Pp
Modes 2 and 3 are only supported for AHCI.
.It Va hint.ata. Ns Ar X Ns Va .dev Ns Ar X Ns Va .sata_rev
limits the initial SATA revision (speed) for the specified device
on the specified channel.

.It JMicron:
JMB360, JMB361, JMB363, JMB365, JMB366, JMB368.
.It Marvell
88SE6101, 88SE6102, 88SE6111, 88SE6121, 88SE6141, 88SE6145.
88SE6102, 88SE6111, 88SE6121, 88SE6141, 88SE6145, 88SX7042.
.It National:
SC1100.
.It NetCell:

.It ServerWorks:
HT1000, ROSB4, CSB5, CSB6, K2, Frodo4, Frodo8.
.It Silicon Image:
SiI0680, SiI3112, SiI3114, SiI3512.
.It SiS:
SIS180, SIS181, SIS182, SIS5513, SIS530, SIS540, SIS550, SIS620, SIS630,
SIS630S, SIS633, SIS635, SIS730, SIS733, SIS735, SIS745, SIS961, SIS962,

VT8237A, VT8237S, VT8251, CX700, VX800, VX855, VX900.
.El
.Pp
Some of above chips can be configured for AHCI mode.
In such case they are supported by
.Xr ahci 4
driver instead.
.Xr siis 4
drivers.
If both drivers are loaded at the same time, those will have precedence.
.Pp
Unknown ATA chipsets are supported in PIO modes, and if the standard
busmaster DMA registers are present and contain valid setup, DMA is




.\"
.\" $FreeBSD$
.\"
.Dd March 23, 2015
.Dt MVS 4
.Os
.Sh NAME

hardware command queues (up to 31 command per port),
Native Command Queuing, SATA interface Power Management, device hot-plug
and Message Signaled Interrupts.
.Pp
The same hardware is also supported by the atamarvell and ataadaptec
drivers from the
.Xr ata 4
subsystem.
If both drivers are loaded at the same time, this one will be
given precedence as the more functional of the two.
.Sh HARDWARE
The
.Nm




.\"
.\" $FreeBSD$
.\"
.Dd March 23, 2015
.Dt SIIS 4
.Os
.Sh NAME

driver can be controlled via the
.Xr led 4
API for localization or status reporting purposes.
.Pp
Same hardware is also supported by the atasiliconimage driver from
.Xr ata 4
subsystem.
If both drivers are loaded at the same time, this one will be
given precedence as the more functional of the two.
.Sh HARDWARE
The
.Nm

Lines 27-33 arm/mv/mv_common.c standard Link Here

(-)sys/arm/mv/files.mv (-1 lines)
27	arm/mv/mv_localbus.c standard	27	arm/mv/mv_localbus.c standard
28	arm/mv/mv_machdep.c standard	28	arm/mv/mv_machdep.c standard
29	arm/mv/mv_pci.c optional pci	29	arm/mv/mv_pci.c optional pci
30	arm/mv/mv_sata.c optional ata \| atamvsata
31	arm/mv/mv_ts.c standard	30	arm/mv/mv_ts.c standard
32	arm/mv/timer.c standard	31	arm/mv/timer.c standard
33	arm/mv/twsi.c optional iicbus	32	arm/mv/twsi.c optional iicbus




/*-
 * Copyright (C) 2008-2009 Semihalf
 * All rights reserved.
 *
 * Initial version developed by Ilya Bakulin. Full functionality and bringup
 * by Piotr Ziecik.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");

#include <sys/param.h>
#include <sys/bus.h>
#include <sys/lock.h>
#include <sys/resource.h>
#include <sys/systm.h>
#include <sys/rman.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <sys/endian.h>
#include <sys/sema.h>
#include <sys/taskqueue.h>
#include <vm/uma.h>
#include <machine/bus.h>
#include <machine/resource.h>

#include <sys/ata.h>
#include <dev/ata/ata-all.h>
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>

#include "ata_if.h"

#include "mvreg.h"
#include "mvvar.h"

/* Useful macros */
#define EDMA_TIMEOUT		100000 /* 100 ms */
#define SATA_INL(sc, reg)	ATA_INL((sc)->sc_mem_res, reg)
#define SATA_OUTL(sc, reg, val)	ATA_OUTL((sc)->sc_mem_res, reg, val)

/* HW-related data structures */
struct sata_prdentry {
	uint32_t	prd_addrlo;
	uint32_t	prd_count;
	uint32_t	prd_addrhi;
	uint32_t	prd_reserved;
};

struct sata_crqb {
	uint32_t	crqb_prdlo;
	uint32_t	crqb_prdhi;
	uint32_t	crqb_flags;
	uint16_t	crqb_count;
	uint16_t	crqb_reserved1[2];
	uint8_t		crqb_ata_command;
	uint8_t		crqb_ata_feature;
	uint8_t		crqb_ata_lba_low;
	uint8_t		crqb_ata_lba_mid;
	uint8_t		crqb_ata_lba_high;
	uint8_t		crqb_ata_device;
	uint8_t		crqb_ata_lba_low_p;
	uint8_t		crqb_ata_lba_mid_p;
	uint8_t		crqb_ata_lba_high_p;
	uint8_t		crqb_ata_feature_p;
	uint8_t		crqb_ata_count;
	uint8_t		crqb_ata_count_p;
	uint16_t	crqb_reserved2;
};

struct sata_crpb {
	uint8_t		crpb_tag;
	uint8_t		crpb_reserved;
	uint8_t		crpb_edma_status;
	uint8_t		crpb_dev_status;
	uint32_t	crpb_timestamp;
};

/* Identification section. */
struct sata_softc {
	device_t		sc_dev;
	unsigned int		sc_version;
	unsigned int		sc_edma_qlen;
	uint32_t		sc_edma_reqis_mask;
	uint32_t		sc_edma_resos_mask;
	struct resource		*sc_mem_res;
	bus_space_tag_t		sc_mem_res_bustag;
	bus_space_handle_t	sc_mem_res_bushdl;
	struct resource		*sc_irq_res;
	void			*sc_irq_cookiep;
	struct {
		void	(*function)(void *);
		void	*argument;
	} sc_interrupt[SATA_CHAN_NUM];
};

/* Controller functions */
static int	sata_probe(device_t dev);
static int	sata_attach(device_t dev);
static int	sata_detach(device_t dev);
static void	sata_intr(void*);
static struct resource * sata_alloc_resource(device_t dev, device_t child,
    int type, int *rid, u_long start, u_long end, u_long count, u_int flags);
static int	sata_release_resource(device_t dev, device_t child, int type,
    int rid, struct resource *r);
static int	sata_setup_intr(device_t dev, device_t child,
    struct resource *irq, int flags, driver_filter_t *filt,
    driver_intr_t *function, void *argument, void **cookiep);
static int	sata_teardown_intr(device_t dev, device_t child,
    struct resource *irq, void *cookie);

/* Channel functions */
static int	sata_channel_probe(device_t dev);
static int	sata_channel_attach(device_t dev);
static int	sata_channel_detach(device_t dev);
static int	sata_channel_begin_transaction(struct ata_request *request);
static int	sata_channel_end_transaction(struct ata_request *request);
static int	sata_channel_status(device_t dev);
static int	sata_channel_setmode(device_t dev, int target, int mode);
static int	sata_channel_getrev(device_t dev, int target);
static void	sata_channel_reset(device_t dev);
static void	sata_channel_dmasetprd(void *xsc, bus_dma_segment_t *segs,
    int nsegs, int error);

/* EDMA functions */
static int	sata_edma_ctrl(device_t dev, int on);
static int	sata_edma_is_running(device_t);

static device_method_t sata_methods[] = {
	/* Device method */
	DEVMETHOD(device_probe,		sata_probe),
	DEVMETHOD(device_attach,	sata_attach),
	DEVMETHOD(device_detach,	sata_detach),
	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
	DEVMETHOD(device_suspend,	bus_generic_suspend),
	DEVMETHOD(device_resume,	bus_generic_resume),

	/* ATA bus methods. */
	DEVMETHOD(bus_alloc_resource,		sata_alloc_resource),
	DEVMETHOD(bus_release_resource,		sata_release_resource),
	DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
	DEVMETHOD(bus_deactivate_resource,	bus_generic_deactivate_resource),
	DEVMETHOD(bus_setup_intr,		sata_setup_intr),
	DEVMETHOD(bus_teardown_intr,		sata_teardown_intr),
	{ 0, 0 },
};

static driver_t sata_driver = {
	"sata",
	sata_methods,
	sizeof(struct sata_softc),
};

devclass_t sata_devclass;

DRIVER_MODULE(sata, simplebus, sata_driver, sata_devclass, 0, 0);
MODULE_VERSION(sata, 1);
MODULE_DEPEND(sata, ata, 1, 1, 1);

static int
sata_probe(device_t dev)
{
	struct sata_softc *sc;
	uint32_t d, r;

	if (!ofw_bus_status_okay(dev))
		return (ENXIO);

	if (!ofw_bus_is_compatible(dev, "mrvl,sata"))
		return (ENXIO);

	soc_id(&d, &r);
	sc = device_get_softc(dev);

	switch(d) {
	case MV_DEV_88F5182:
		sc->sc_version = 1;
		sc->sc_edma_qlen = 128;
		break;
	case MV_DEV_88F6281:
	case MV_DEV_88F6282:
	case MV_DEV_MV78100:
	case MV_DEV_MV78100_Z0:
	case MV_DEV_MV78460:
		sc->sc_version = 2;
		sc->sc_edma_qlen = 32;
		break;
	default:
		device_printf(dev, "unsupported SoC (ID: 0x%08X)!\n", d);
		return (ENXIO);
	}

	sc->sc_edma_reqis_mask = (sc->sc_edma_qlen - 1) << SATA_EDMA_REQIS_OFS;
	sc->sc_edma_resos_mask = (sc->sc_edma_qlen - 1) << SATA_EDMA_RESOS_OFS;

	device_set_desc(dev, "Marvell Integrated SATA Controller");
	return (0);
}

static int
sata_attach(device_t dev)
{
	struct sata_softc *sc;
	int mem_id, irq_id, error, i;
	device_t ata_chan;
	uint32_t reg;

	sc = device_get_softc(dev);
	sc->sc_dev = dev;
	mem_id = 0;
	irq_id = 0;

	/* Allocate resources */
	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
	    &mem_id, RF_ACTIVE);
	if (sc->sc_mem_res == NULL) {
		device_printf(dev, "could not allocate memory.\n");
		return (ENOMEM);
	}

	sc->sc_mem_res_bustag = rman_get_bustag(sc->sc_mem_res);
	sc->sc_mem_res_bushdl = rman_get_bushandle(sc->sc_mem_res);
	KASSERT(sc->sc_mem_res_bustag && sc->sc_mem_res_bushdl,
	    ("cannot get bus handle or tag."));

	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq_id,
	    RF_ACTIVE);
	if (sc->sc_irq_res == NULL) {
		device_printf(dev, "could not allocate IRQ.\n");
		error = ENOMEM;
		goto err;
	}

	error = bus_setup_intr(dev, sc->sc_irq_res,
	    INTR_TYPE_BIO | INTR_MPSAFE | INTR_ENTROPY,
	    NULL, sata_intr, sc, &sc->sc_irq_cookiep);
	if (error != 0) {
		device_printf(dev, "could not setup interrupt.\n");
		goto err;
	}

	/* Attach channels */
	for (i = 0; i < SATA_CHAN_NUM; i++) {
		ata_chan = device_add_child(dev, "ata",
		    devclass_find_free_unit(ata_devclass, 0));

		if (!ata_chan) {
			device_printf(dev, "cannot add channel %d.\n", i);
			error = ENOMEM;
			goto err;
		}
	}

	/* Disable interrupt coalescing */
	reg = SATA_INL(sc, SATA_CR);
	for (i = 0; i < SATA_CHAN_NUM; i++)
		reg |= SATA_CR_COALDIS(i);

	/* Disable DMA byte swapping */
	if (sc->sc_version == 2)
		reg |= SATA_CR_NODMABS | SATA_CR_NOEDMABS |
		    SATA_CR_NOPRDPBS;

	SATA_OUTL(sc, SATA_CR, reg);

	/* Clear and mask all interrupts */
	SATA_OUTL(sc, SATA_ICR, 0);
	SATA_OUTL(sc, SATA_MIMR, 0);

	return(bus_generic_attach(dev));

err:
	sata_detach(dev);
	return (error);
}

static int
sata_detach(device_t dev)
{
	struct sata_softc *sc;

	sc = device_get_softc(dev);

	if (device_is_attached(dev))
		bus_generic_detach(dev);

	if (sc->sc_mem_res != NULL) {
		bus_release_resource(dev, SYS_RES_MEMORY,
		    rman_get_rid(sc->sc_mem_res), sc->sc_mem_res);
		sc->sc_mem_res = NULL;
	}

	if (sc->sc_irq_res != NULL) {
		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_cookiep);
		bus_release_resource(dev, SYS_RES_IRQ,
		    rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
		sc->sc_irq_res = NULL;
	}

	return (0);
}

static struct resource *
sata_alloc_resource(device_t dev, device_t child, int type, int *rid,
    u_long start, u_long end, u_long count, u_int flags)
{
	struct sata_softc *sc;

	sc = device_get_softc(dev);

	KASSERT(type == SYS_RES_IRQ && *rid == ATA_IRQ_RID,
	    ("illegal resource request (type %u, rid %u).",
	    type, *rid));

	return (sc->sc_irq_res);
}

static int
sata_release_resource(device_t dev, device_t child, int type, int rid,
    struct resource *r)
{

	KASSERT(type == SYS_RES_IRQ && rid == ATA_IRQ_RID,
	    ("strange type %u and/or rid %u while releasing resource.", type,
	    rid));

	return (0);
}

static int
sata_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
    driver_filter_t *filt, driver_intr_t *function, void *argument,
    void **cookiep)
{
	struct sata_softc *sc;
	struct ata_channel *ch;

	sc = device_get_softc(dev);
	ch = device_get_softc(child);

	if (filt != NULL) {
		device_printf(dev, "filter interrupts are not supported.\n");
		return (EINVAL);
	}

	sc->sc_interrupt[ch->unit].function = function;
	sc->sc_interrupt[ch->unit].argument = argument;
	*cookiep = sc;

	return (0);
}

static int
sata_teardown_intr(device_t dev, device_t child, struct resource *irq,
    void *cookie)
{
	struct sata_softc *sc;
	struct ata_channel *ch;

	sc = device_get_softc(dev);
	ch = device_get_softc(child);

	sc->sc_interrupt[ch->unit].function = NULL;
	sc->sc_interrupt[ch->unit].argument = NULL;

	return (0);
}

static void
sata_intr(void *xsc)
{
	struct sata_softc *sc;
	int unit;

	sc = xsc;

	/*
	 * Behave like ata_generic_intr() for PCI controllers.
	 * Simply invoke ISRs on all channels.
	 */
	for (unit = 0; unit < SATA_CHAN_NUM; unit++)
		if (sc->sc_interrupt[unit].function != NULL)
			sc->sc_interrupt[unit].function(
			    sc->sc_interrupt[unit].argument);
}

static int
sata_channel_probe(device_t dev)
{

	device_set_desc(dev, "Marvell Integrated SATA Channel");
	return (ata_probe(dev));
}

static int
sata_channel_attach(device_t dev)
{
	struct sata_softc *sc;
	struct ata_channel *ch;
	uint64_t work;
	int error, i;

	sc = device_get_softc(device_get_parent(dev));
	ch = device_get_softc(dev);

	if (ch->attached)
		return (0);

	ch->dev = dev;
	ch->unit = device_get_unit(dev);
	ch->flags |= ATA_USE_16BIT | ATA_NO_SLAVE | ATA_SATA;

	/* Set legacy ATA resources. */
	for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
		ch->r_io[i].res = sc->sc_mem_res;
		ch->r_io[i].offset = SATA_SHADOWR_BASE(ch->unit) + (i << 2);
	}

	ch->r_io[ATA_CONTROL].res = sc->sc_mem_res;
	ch->r_io[ATA_CONTROL].offset = SATA_SHADOWR_CONTROL(ch->unit);

	ch->r_io[ATA_IDX_ADDR].res = sc->sc_mem_res;
	ata_default_registers(dev);

	/* Set SATA resources. */
	ch->r_io[ATA_SSTATUS].res = sc->sc_mem_res;
	ch->r_io[ATA_SSTATUS].offset = SATA_SATA_SSTATUS(ch->unit);
	ch->r_io[ATA_SERROR].res = sc->sc_mem_res;
	ch->r_io[ATA_SERROR].offset = SATA_SATA_SERROR(ch->unit);
	ch->r_io[ATA_SCONTROL].res = sc->sc_mem_res;
	ch->r_io[ATA_SCONTROL].offset = SATA_SATA_SCONTROL(ch->unit);
	ata_generic_hw(dev);

	ch->hw.begin_transaction = sata_channel_begin_transaction;
	ch->hw.end_transaction = sata_channel_end_transaction;
	ch->hw.status = sata_channel_status;

	/* Set DMA resources */
	ata_dmainit(dev);
	ch->dma.setprd = sata_channel_dmasetprd;

	/* Clear work area */
	KASSERT(sc->sc_edma_qlen * (sizeof(struct sata_crqb) +
	    sizeof(struct sata_crpb)) <= ch->dma.max_iosize,
	    ("insufficient DMA memory for request/response queues.\n"));
	bzero(ch->dma.work, sc->sc_edma_qlen * (sizeof(struct sata_crqb) +
	    sizeof(struct sata_crpb)));
	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

	/* Turn off EDMA engine */
	error = sata_edma_ctrl(dev, 0);
	if (error) {
		ata_dmafini(dev);
		return (error);
	}

	/*
	 * Initialize EDMA engine:
	 *	- Native Command Queuing off,
	 *	- Non-Queued operation,
	 *	- Host Queue Cache enabled.
	 */
	SATA_OUTL(sc, SATA_EDMA_CFG(ch->unit), SATA_EDMA_CFG_HQCACHE |
	    (sc->sc_version == 1) ? SATA_EDMA_CFG_QL128 : 0);

	/* Set request queue pointers */
	work = ch->dma.work_bus;
	SATA_OUTL(sc, SATA_EDMA_REQBAHR(ch->unit), work >> 32);
	SATA_OUTL(sc, SATA_EDMA_REQIPR(ch->unit), work & 0xFFFFFFFF);
	SATA_OUTL(sc, SATA_EDMA_REQOPR(ch->unit), work & 0xFFFFFFFF);

	/* Set response queue pointers */
	work += sc->sc_edma_qlen * sizeof(struct sata_crqb);
	SATA_OUTL(sc, SATA_EDMA_RESBAHR(ch->unit), work >> 32);
	SATA_OUTL(sc, SATA_EDMA_RESIPR(ch->unit), work & 0xFFFFFFFF);
	SATA_OUTL(sc, SATA_EDMA_RESOPR(ch->unit), work & 0xFFFFFFFF);

	/* Clear any outstanding interrupts */
	ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
	SATA_OUTL(sc, SATA_SATA_FISICR(ch->unit), 0);
	SATA_OUTL(sc, SATA_EDMA_IECR(ch->unit), 0);
	SATA_OUTL(sc, SATA_ICR,
	    ~(SATA_ICR_DEV(ch->unit) | SATA_ICR_DMADONE(ch->unit)));

	/* Umask channel interrupts */
	SATA_OUTL(sc, SATA_EDMA_IEMR(ch->unit), 0xFFFFFFFF);
	SATA_OUTL(sc, SATA_MIMR, SATA_INL(sc, SATA_MIMR) |
	    SATA_MICR_DONE(ch->unit) | SATA_MICR_DMADONE(ch->unit) |
	    SATA_MICR_ERR(ch->unit));

	ch->attached = 1;

	return (ata_attach(dev));
}

static int
sata_channel_detach(device_t dev)
{
	struct sata_softc *sc;
	struct ata_channel *ch;
	int error;

	sc = device_get_softc(device_get_parent(dev));
	ch = device_get_softc(dev);

	if (!ch->attached)
		return (0);

	/* Turn off EDMA engine */
	sata_edma_ctrl(dev, 0);

	/* Mask chanel interrupts */
	SATA_OUTL(sc, SATA_EDMA_IEMR(ch->unit), 0);
	SATA_OUTL(sc, SATA_MIMR, SATA_INL(sc, SATA_MIMR) & ~(
	    SATA_MICR_DONE(ch->unit) | SATA_MICR_DMADONE(ch->unit) |
	    SATA_MICR_ERR(ch->unit)));

	error = ata_detach(dev);
	ata_dmafini(dev);

	ch->attached = 0;

	return (error);
}

static int
sata_channel_begin_transaction(struct ata_request *request)
{
	struct sata_softc *sc;
	struct ata_channel *ch;
	struct sata_crqb *crqb;
	uint32_t req_in;
	int error, slot;

	sc = device_get_softc(device_get_parent(request->parent));
	ch = device_get_softc(request->parent);

	mtx_assert(&ch->state_mtx, MA_OWNED);

	/* Only DMA R/W goes through the EDMA machine. */
	if (request->u.ata.command != ATA_READ_DMA &&
	    request->u.ata.command != ATA_WRITE_DMA &&
	    request->u.ata.command != ATA_READ_DMA48 &&
	    request->u.ata.command != ATA_WRITE_DMA48) {

		/* Disable EDMA before accessing legacy registers */
		if (sata_edma_is_running(request->parent)) {
			error = sata_edma_ctrl(request->parent, 0);
			if (error) {
				request->result = error;
				return (ATA_OP_FINISHED);
			}
		}

		return (ata_begin_transaction(request));
	}

	/* Prepare data for DMA */
	if ((error = ch->dma.load(request, NULL, NULL))) {
		device_printf(request->parent, "setting up DMA failed!\n");
		request->result = error;
		return ATA_OP_FINISHED;
	}

	/* Get next free queue slot */
	req_in = SATA_INL(sc, SATA_EDMA_REQIPR(ch->unit));
	slot = (req_in & sc->sc_edma_reqis_mask) >> SATA_EDMA_REQIS_OFS;
	crqb = (struct sata_crqb *)(ch->dma.work +
	    (slot << SATA_EDMA_REQIS_OFS));

	/* Fill in request */
	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);

	crqb->crqb_prdlo = htole32((uint64_t)request->dma->sg_bus & 0xFFFFFFFF);
	crqb->crqb_prdhi = htole32((uint64_t)request->dma->sg_bus >> 32);
	crqb->crqb_flags = htole32((request->flags & ATA_R_READ ? 0x01 : 0x00) |
	    (request->tag << 1));

	crqb->crqb_ata_command = request->u.ata.command;
	crqb->crqb_ata_feature = request->u.ata.feature;
	crqb->crqb_ata_lba_low = request->u.ata.lba;
	crqb->crqb_ata_lba_mid = request->u.ata.lba >> 8;
	crqb->crqb_ata_lba_high = request->u.ata.lba >> 16;
	crqb->crqb_ata_device = ((request->u.ata.lba >> 24) & 0x0F) | (1 << 6);
	crqb->crqb_ata_lba_low_p = request->u.ata.lba >> 24;
	crqb->crqb_ata_lba_mid_p = request->u.ata.lba >> 32;
	crqb->crqb_ata_lba_high_p = request->u.ata.lba >> 40;
	crqb->crqb_ata_feature_p = request->u.ata.feature >> 8;
	crqb->crqb_ata_count = request->u.ata.count;
	crqb->crqb_ata_count_p = request->u.ata.count >> 8;

	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

	/* Enable EDMA if disabled */
	if (!sata_edma_is_running(request->parent)) {
		error = sata_edma_ctrl(request->parent, 1);
		if (error) {
			ch->dma.unload(request);
			request->result = error;
			return (ATA_OP_FINISHED);
		}
	}

	/* Tell EDMA about new request */
	req_in = (req_in & ~sc->sc_edma_reqis_mask) | (((slot + 1) <<
	    SATA_EDMA_REQIS_OFS) & sc->sc_edma_reqis_mask);

	SATA_OUTL(sc, SATA_EDMA_REQIPR(ch->unit), req_in);

	return (ATA_OP_CONTINUES);
}

static int
sata_channel_end_transaction(struct ata_request *request)
{
	struct sata_softc *sc;
	struct ata_channel *ch;
	struct sata_crpb *crpb;
	uint32_t res_in, res_out, icr;
	int slot;

	sc = device_get_softc(device_get_parent(request->parent));
	ch = device_get_softc(request->parent);

	mtx_assert(&ch->state_mtx, MA_OWNED);

	icr = SATA_INL(sc, SATA_ICR);
	if (icr & SATA_ICR_DMADONE(ch->unit)) {
		/* Get current response slot */
		res_out = SATA_INL(sc, SATA_EDMA_RESOPR(ch->unit));
		slot = (res_out & sc->sc_edma_resos_mask) >>
		    SATA_EDMA_RESOS_OFS;
		crpb = (struct sata_crpb *)(ch->dma.work +
		    (sc->sc_edma_qlen * sizeof(struct sata_crqb)) +
		    (slot << SATA_EDMA_RESOS_OFS));

		/* Record this request status */
		bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);

		request->status = crpb->crpb_dev_status;
		request->error = 0;

		bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

		/* Update response queue pointer */
		res_out = (res_out & ~sc->sc_edma_resos_mask) | (((slot + 1) <<
		    SATA_EDMA_RESOS_OFS) & sc->sc_edma_resos_mask);

		SATA_OUTL(sc, SATA_EDMA_RESOPR(ch->unit), res_out);

		/* Ack DMA interrupt if there is nothing more to do */
		res_in = SATA_INL(sc, SATA_EDMA_RESIPR(ch->unit));
		res_in &= sc->sc_edma_resos_mask;
		res_out &= sc->sc_edma_resos_mask;

		if (res_in == res_out)
			SATA_OUTL(sc, SATA_ICR,
			    ~SATA_ICR_DMADONE(ch->unit));

		/* Update progress */
		if (!(request->status & ATA_S_ERROR) &&
		    !(request->flags & ATA_R_TIMEOUT))
			request->donecount = request->bytecount;

		/* Unload DMA data */
		ch->dma.unload(request);

		return(ATA_OP_FINISHED);
	}

	/* Legacy ATA interrupt */
	return (ata_end_transaction(request));
}

static int
sata_channel_status(device_t dev)
{
	struct sata_softc *sc;
	struct ata_channel *ch;
	uint32_t icr, iecr;

	sc = device_get_softc(device_get_parent(dev));
	ch = device_get_softc(dev);

	icr = SATA_INL(sc, SATA_ICR);
	iecr = SATA_INL(sc, SATA_EDMA_IECR(ch->unit));

	if ((icr & SATA_ICR_DEV(ch->unit)) || iecr) {
		/* Disable EDMA before accessing SATA registers */
		sata_edma_ctrl(dev, 0);
		ata_sata_phy_check_events(dev, -1);

		/* Ack device and error interrupt */
		SATA_OUTL(sc, SATA_ICR, ~SATA_ICR_DEV(ch->unit));
		SATA_OUTL(sc, SATA_EDMA_IECR(ch->unit), 0);
	}

	icr &= SATA_ICR_DEV(ch->unit) | SATA_ICR_DMADONE(ch->unit);
	return (icr);
}

static void
sata_channel_reset(device_t dev)
{
	struct sata_softc *sc;
	struct ata_channel *ch;

	sc = device_get_softc(device_get_parent(dev));
	ch = device_get_softc(dev);

	/* Disable EDMA before using legacy registers */
	sata_edma_ctrl(dev, 0);

	/* Mask all EDMA interrups */
	SATA_OUTL(sc, SATA_EDMA_IEMR(ch->unit), 0);

	/* Reset EDMA */
	SATA_OUTL(sc, SATA_EDMA_CMD(ch->unit), SATA_EDMA_CMD_RESET);
	DELAY(25);
	SATA_OUTL(sc, SATA_EDMA_CMD(ch->unit), 0);

	/* Reset PHY and device */
	if (ata_sata_phy_reset(dev, -1, 1))
		ata_generic_reset(dev);
	else
		ch->devices = 0;

	/* Clear EDMA errors */
	SATA_OUTL(sc, SATA_SATA_FISICR(ch->unit), 0);
	SATA_OUTL(sc, SATA_EDMA_IECR(ch->unit), 0);

	/* Unmask all EDMA interrups */
	SATA_OUTL(sc, SATA_EDMA_IEMR(ch->unit), 0xFFFFFFFF);
}

static int
sata_channel_setmode(device_t parent, int target, int mode)
{

	/* Disable EDMA before using legacy registers */
	sata_edma_ctrl(parent, 0);
	return (ata_sata_setmode(parent, target, mode));
}

static int
sata_channel_getrev(device_t parent, int target)
{

	/* Disable EDMA before using legacy registers */
	sata_edma_ctrl(parent, 0);
	return (ata_sata_getrev(parent, target));
}

static void
sata_channel_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
    int error)
{
	struct ata_dmasetprd_args *args;
	struct sata_prdentry *prd;
	int i;

	args = xsc;
	prd = args->dmatab;

	if ((args->error = error))
		return;

	for (i = 0; i < nsegs; i++) {
		prd[i].prd_addrlo = htole32(segs[i].ds_addr);
		prd[i].prd_addrhi = htole32((uint64_t)segs[i].ds_addr >> 32);
		prd[i].prd_count = htole32(segs[i].ds_len);
	}

	prd[i - 1].prd_count |= htole32(ATA_DMA_EOT);
	KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries.\n"));
	args->nsegs = nsegs;
}

static int
sata_edma_ctrl(device_t dev, int on)
{
	struct sata_softc *sc;
	struct ata_channel *ch;
	int bit, timeout;
	uint32_t reg;

	sc = device_get_softc(device_get_parent(dev));
	ch = device_get_softc(dev);
	bit = on ? SATA_EDMA_CMD_ENABLE : SATA_EDMA_CMD_DISABLE;
	timeout = EDMA_TIMEOUT;

	SATA_OUTL(sc, SATA_EDMA_CMD(ch->unit), bit);

	while (1) {
		DELAY(1);

		reg = SATA_INL(sc, SATA_EDMA_CMD(ch->unit));

		/* Enable bit will be 1 after disable command completion */
		if (on && (reg & SATA_EDMA_CMD_ENABLE))
			break;

		/* Disable bit will be 0 after disable command completion */
		if (!on && !(reg & SATA_EDMA_CMD_DISABLE))
			break;

		if (timeout-- <= 0) {
			device_printf(dev, "EDMA command timeout!\n");
			return (ETIMEDOUT);
		}
	}

	return (0);
}

static int
sata_edma_is_running(device_t dev)
{
	struct sata_softc *sc;
	struct ata_channel *ch;

	sc = device_get_softc(device_get_parent(dev));
	ch = device_get_softc(dev);

	return (SATA_INL(sc, SATA_EDMA_CMD(ch->unit)) & SATA_EDMA_CMD_ENABLE);
}

static device_method_t sata_channel_methods[] = {
	/* Device interface. */
	DEVMETHOD(device_probe,		sata_channel_probe),
	DEVMETHOD(device_attach,	sata_channel_attach),
	DEVMETHOD(device_detach,	sata_channel_detach),
	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
	DEVMETHOD(device_suspend,	ata_suspend),
	DEVMETHOD(device_resume,	ata_resume),

	/* ATA channel interface */
	DEVMETHOD(ata_reset,		sata_channel_reset),
	DEVMETHOD(ata_setmode,		sata_channel_setmode),
	DEVMETHOD(ata_getrev,		sata_channel_getrev),
	{ 0, 0 }
};

driver_t sata_channel_driver = {
	"ata",
	sata_channel_methods,
	sizeof(struct ata_channel),
};

DRIVER_MODULE(ata, sata, sata_channel_driver, ata_devclass, 0, 0);

Lines 149-158 module_path="/boot/modules" # Set the module searc Link Here

(-)sys/boot/forth/loader.conf (-2 lines)
149	### ATA modules ##############################################	149	### ATA modules ##############################################
150	##############################################################	150	##############################################################
151		151
152	ataahci_load="NO" # AHCI SATA
153	ataacard_load="NO" # ACARD	152	ataacard_load="NO" # ACARD
154	ataacerlabs_load="NO" # Acer Labs Inc. (ALI)	153	ataacerlabs_load="NO" # Acer Labs Inc. (ALI)
155	ataadaptec_load="NO" # Adaptec
156	ataamd_load="NO" # American Micro Devices (AMD)	154	ataamd_load="NO" # American Micro Devices (AMD)
157	ataati_load="NO" # ATI	155	ataati_load="NO" # ATI
158	atacenatek_load="NO" # Cenatek	156	atacenatek_load="NO" # Cenatek

Lines 1719-1728 device ata Link Here

(-)sys/conf/NOTES (-2 lines)
1719	#device atapci # PCI bus support; only generic chipset support	1719	#device atapci # PCI bus support; only generic chipset support
1720		1720
1721	# PCI ATA chipsets	1721	# PCI ATA chipsets
1722	#device ataahci # AHCI SATA
1723	#device ataacard # ACARD	1722	#device ataacard # ACARD
1724	#device ataacerlabs # Acer Labs Inc. (ALI)	1723	#device ataacerlabs # Acer Labs Inc. (ALI)
1725	#device ataadaptec # Adaptec
1726	#device ataamd # American Micro Devices (AMD)	1724	#device ataamd # American Micro Devices (AMD)
1727	#device ataati # ATI	1725	#device ataati # ATI
1728	#device atacenatek # Cenatek	1726	#device atacenatek # Cenatek




dev/ata/ata-cbus.c		optional ata pc98 | atapc98
dev/ata/ata-isa.c		optional ata isa | ataisa
dev/ata/ata-pci.c		optional ata pci | atapci
dev/ata/chipsets/ata-ahci.c	optional ata pci | ataahci | ataacerlabs | \
					 ataati | ataintel | atajmicron | \
					 atavia | atanvidia
dev/ata/chipsets/ata-acard.c	optional ata pci | ataacard
dev/ata/chipsets/ata-acerlabs.c	optional ata pci | ataacerlabs
dev/ata/chipsets/ata-adaptec.c	optional ata pci | ataadaptec
dev/ata/chipsets/ata-amd.c	optional ata pci | ataamd
dev/ata/chipsets/ata-ati.c	optional ata pci | ataati
dev/ata/chipsets/ata-cenatek.c	optional ata pci | atacenatek

dev/ata/chipsets/ata-intel.c	optional ata pci | ataintel
dev/ata/chipsets/ata-ite.c	optional ata pci | ataite
dev/ata/chipsets/ata-jmicron.c	optional ata pci | atajmicron
dev/ata/chipsets/ata-marvell.c	optional ata pci | atamarvell
dev/ata/chipsets/ata-micron.c	optional ata pci | atamicron
dev/ata/chipsets/ata-national.c	optional ata pci | atanational
dev/ata/chipsets/ata-netcell.c	optional ata pci | atanetcell





#define ATA_SACTIVE                     16

/* SATA AHCI v1.0 register defines */
#define ATA_AHCI_CAP                    0x00
#define		ATA_AHCI_CAP_NPMASK	0x0000001f
#define		ATA_AHCI_CAP_SXS	0x00000020
#define		ATA_AHCI_CAP_EMS	0x00000040
#define		ATA_AHCI_CAP_CCCS	0x00000080
#define		ATA_AHCI_CAP_NCS	0x00001F00
#define		ATA_AHCI_CAP_NCS_SHIFT	8
#define		ATA_AHCI_CAP_PSC	0x00002000
#define		ATA_AHCI_CAP_SSC	0x00004000
#define		ATA_AHCI_CAP_PMD	0x00008000
#define		ATA_AHCI_CAP_FBSS	0x00010000
#define		ATA_AHCI_CAP_SPM	0x00020000
#define		ATA_AHCI_CAP_SAM	0x00080000
#define		ATA_AHCI_CAP_ISS	0x00F00000
#define		ATA_AHCI_CAP_ISS_SHIFT	20
#define		ATA_AHCI_CAP_SCLO	0x01000000
#define		ATA_AHCI_CAP_SAL	0x02000000
#define		ATA_AHCI_CAP_SALP	0x04000000
#define		ATA_AHCI_CAP_SSS	0x08000000
#define		ATA_AHCI_CAP_SMPS	0x10000000
#define		ATA_AHCI_CAP_SSNTF	0x20000000
#define		ATA_AHCI_CAP_SNCQ	0x40000000
#define		ATA_AHCI_CAP_64BIT	0x80000000

#define ATA_AHCI_GHC                    0x04
#define         ATA_AHCI_GHC_AE         0x80000000
#define         ATA_AHCI_GHC_IE         0x00000002
#define         ATA_AHCI_GHC_HR         0x00000001

#define ATA_AHCI_IS                     0x08
#define ATA_AHCI_PI                     0x0c
#define ATA_AHCI_VS                     0x10

#define ATA_AHCI_OFFSET                 0x80

#define ATA_AHCI_P_CLB                  0x100
#define ATA_AHCI_P_CLBU                 0x104
#define ATA_AHCI_P_FB                   0x108
#define ATA_AHCI_P_FBU                  0x10c
#define ATA_AHCI_P_IS                   0x110
#define ATA_AHCI_P_IE                   0x114
#define         ATA_AHCI_P_IX_DHR       0x00000001
#define         ATA_AHCI_P_IX_PS        0x00000002
#define         ATA_AHCI_P_IX_DS        0x00000004
#define         ATA_AHCI_P_IX_SDB       0x00000008
#define         ATA_AHCI_P_IX_UF        0x00000010
#define         ATA_AHCI_P_IX_DP        0x00000020
#define         ATA_AHCI_P_IX_PC        0x00000040
#define         ATA_AHCI_P_IX_DI        0x00000080

#define         ATA_AHCI_P_IX_PRC       0x00400000
#define         ATA_AHCI_P_IX_IPM       0x00800000
#define         ATA_AHCI_P_IX_OF        0x01000000
#define         ATA_AHCI_P_IX_INF       0x04000000
#define         ATA_AHCI_P_IX_IF        0x08000000
#define         ATA_AHCI_P_IX_HBD       0x10000000
#define         ATA_AHCI_P_IX_HBF       0x20000000
#define         ATA_AHCI_P_IX_TFE       0x40000000
#define         ATA_AHCI_P_IX_CPD       0x80000000

#define ATA_AHCI_P_CMD                  0x118
#define         ATA_AHCI_P_CMD_ST       0x00000001
#define         ATA_AHCI_P_CMD_SUD      0x00000002
#define         ATA_AHCI_P_CMD_POD      0x00000004
#define         ATA_AHCI_P_CMD_CLO      0x00000008
#define         ATA_AHCI_P_CMD_FRE      0x00000010
#define         ATA_AHCI_P_CMD_CCS_MASK 0x00001f00
#define         ATA_AHCI_P_CMD_ISS      0x00002000
#define         ATA_AHCI_P_CMD_FR       0x00004000
#define         ATA_AHCI_P_CMD_CR       0x00008000
#define         ATA_AHCI_P_CMD_CPS      0x00010000
#define         ATA_AHCI_P_CMD_PMA      0x00020000
#define         ATA_AHCI_P_CMD_HPCP     0x00040000
#define         ATA_AHCI_P_CMD_ISP      0x00080000
#define         ATA_AHCI_P_CMD_CPD      0x00100000
#define         ATA_AHCI_P_CMD_ATAPI    0x01000000
#define         ATA_AHCI_P_CMD_DLAE     0x02000000
#define         ATA_AHCI_P_CMD_ALPE     0x04000000
#define         ATA_AHCI_P_CMD_ASP      0x08000000
#define         ATA_AHCI_P_CMD_ICC_MASK 0xf0000000
#define         ATA_AHCI_P_CMD_NOOP     0x00000000
#define         ATA_AHCI_P_CMD_ACTIVE   0x10000000
#define         ATA_AHCI_P_CMD_PARTIAL  0x20000000
#define         ATA_AHCI_P_CMD_SLUMBER  0x60000000

#define ATA_AHCI_P_TFD                  0x120
#define ATA_AHCI_P_SIG                  0x124
#define ATA_AHCI_P_SSTS                 0x128
#define ATA_AHCI_P_SCTL                 0x12c
#define ATA_AHCI_P_SERR                 0x130
#define ATA_AHCI_P_SACT                 0x134
#define ATA_AHCI_P_CI                   0x138
#define ATA_AHCI_P_SNTF                 0x13C
#define ATA_AHCI_P_FBS                  0x140

#define ATA_AHCI_CL_SIZE                32
#define ATA_AHCI_CL_OFFSET              0
#define ATA_AHCI_FB_OFFSET              (ATA_AHCI_CL_SIZE * 32)
#define ATA_AHCI_CT_OFFSET              (ATA_AHCI_FB_OFFSET + 4096)
#define ATA_AHCI_CT_SIZE                (2176 + 128)

struct ata_ahci_dma_prd {
    u_int64_t                   dba;
    u_int32_t                   reserved;
    u_int32_t                   dbc;            /* 0 based */
#define ATA_AHCI_PRD_MASK       0x003fffff      /* max 4MB */
#define ATA_AHCI_PRD_IPC        (1<<31)
} __packed;

struct ata_ahci_cmd_tab {
    u_int8_t                    cfis[64];
    u_int8_t                    acmd[32];
    u_int8_t                    reserved[32];
#define ATA_AHCI_DMA_ENTRIES            129
    struct ata_ahci_dma_prd     prd_tab[ATA_AHCI_DMA_ENTRIES];
} __packed;

struct ata_ahci_cmd_list {
    u_int16_t                   cmd_flags;
#define ATA_AHCI_CMD_ATAPI		0x0020
#define ATA_AHCI_CMD_WRITE		0x0040
#define ATA_AHCI_CMD_PREFETCH		0x0080
#define ATA_AHCI_CMD_RESET		0x0100
#define ATA_AHCI_CMD_BIST		0x0200
#define ATA_AHCI_CMD_CLR_BUSY		0x0400

    u_int16_t                   prd_length;     /* PRD entries */
    u_int32_t                   bytecount;
    u_int64_t                   cmd_table_phys; /* 128byte aligned */
} __packed;


/* DMA register defines */
#define ATA_DMA_ENTRIES                 256
#define ATA_DMA_EOT                     0x80000000




#define ATA_I6300ESB_R1         0x25b08086
#define ATA_I63XXESB2           0x269e8086
#define ATA_I63XXESB2_S1        0x26808086
#define ATA_I63XXESB2_S2        0x26818086
#define ATA_I63XXESB2_R1        0x26828086
#define ATA_I63XXESB2_R2        0x26838086
#define ATA_I82801FB            0x266f8086
#define ATA_I82801FB_S1         0x26518086
#define ATA_I82801FB_R1         0x26528086

#define ATA_I82801FBM           0x26538086
#define ATA_I82801GB            0x27df8086
#define ATA_I82801GB_S1         0x27c08086
#define ATA_I82801GB_AH         0x27c18086
#define ATA_I82801GB_R1         0x27c38086
#define ATA_I82801GBM_S1        0x27c48086
#define ATA_I82801GBM_AH        0x27c58086
#define ATA_I82801GBM_R1        0x27c68086
#define ATA_I82801HB_S1         0x28208086
#define ATA_I82801HB_AH6        0x28218086
#define ATA_I82801HB_R1         0x28228086
#define ATA_I82801HB_AH4        0x28248086
#define ATA_I82801HB_S2         0x28258086
#define ATA_I82801HBM           0x28508086
#define ATA_I82801HBM_S1        0x28288086
#define ATA_I82801HBM_S2        0x28298086
#define ATA_I82801HBM_S3        0x282a8086
#define ATA_I82801IB_S1         0x29208086
#define ATA_I82801IB_S3         0x29218086
#define ATA_I82801IB_AH6        0x29228086
#define ATA_I82801IB_AH4        0x29238086
#define ATA_I82801IB_R1         0x29258086
#define ATA_I82801IB_S2         0x29268086
#define ATA_I82801IBM_S1        0x29288086
#define ATA_I82801IBM_AH        0x29298086
#define ATA_I82801IBM_R1        0x292a8086
#define ATA_I82801IBM_S2        0x292d8086
#define ATA_I82801JIB_S1        0x3a208086
#define ATA_I82801JIB_AH        0x3a228086
#define ATA_I82801JIB_R1        0x3a258086
#define ATA_I82801JIB_S2        0x3a268086
#define ATA_I82801JD_S1         0x3a008086
#define ATA_I82801JD_AH         0x3a028086
#define ATA_I82801JD_R1         0x3a058086
#define ATA_I82801JD_S2         0x3a068086
#define ATA_I82801JI_S1         0x3a208086
#define ATA_I82801JI_AH         0x3a228086
#define ATA_I82801JI_R1         0x3a258086
#define ATA_I82801JI_S2         0x3a268086

#define ATA_5Series_S1          0x3b208086
#define ATA_5Series_S2          0x3b218086
#define ATA_5Series_AH1         0x3b228086
#define ATA_5Series_AH2         0x3b238086
#define ATA_5Series_R1          0x3b258086
#define ATA_5Series_S3          0x3b268086
#define ATA_5Series_S4          0x3b288086
#define ATA_5Series_AH3         0x3b298086
#define ATA_5Series_R2          0x3b2c8086
#define ATA_5Series_S5          0x3b2d8086
#define ATA_5Series_S6          0x3b2e8086
#define ATA_5Series_AH4         0x3b2f8086

#define ATA_CPT_S1              0x1c008086
#define ATA_CPT_S2              0x1c018086
#define ATA_CPT_AH1             0x1c028086
#define ATA_CPT_AH2             0x1c038086
#define ATA_CPT_R1              0x1c048086
#define ATA_CPT_R2              0x1c058086
#define ATA_CPT_S3              0x1c088086
#define ATA_CPT_S4              0x1c098086

#define ATA_PBG_S1		0x1d008086
#define ATA_PBG_AH1		0x1d028086
#define ATA_PBG_R1		0x1d048086
#define ATA_PBG_R2		0x1d068086
#define ATA_PBG_R3		0x28268086
#define ATA_PBG_S2		0x1d088086

#define ATA_PPT_S1		0x1e008086
#define ATA_PPT_S2		0x1e018086
#define ATA_PPT_AH1		0x1e028086
#define ATA_PPT_AH2		0x1e038086
#define ATA_PPT_R1		0x1e048086
#define ATA_PPT_R2		0x1e058086
#define ATA_PPT_R3		0x1e068086
#define ATA_PPT_R4		0x1e078086
#define ATA_PPT_S3		0x1e088086
#define ATA_PPT_S4		0x1e098086
#define ATA_PPT_R5		0x1e0e8086
#define ATA_PPT_R6		0x1e0f8086

#define ATA_AVOTON_S1		0x1f208086
#define ATA_AVOTON_S2		0x1f218086


#define ATA_LPT_S1		0x8c008086
#define ATA_LPT_S2		0x8c018086
#define ATA_LPT_AH1		0x8c028086
#define ATA_LPT_AH2		0x8c038086
#define ATA_LPT_R1		0x8c048086
#define ATA_LPT_R2		0x8c058086
#define ATA_LPT_R3		0x8c068086
#define ATA_LPT_R4		0x8c078086
#define ATA_LPT_S3		0x8c088086
#define ATA_LPT_S4		0x8c098086
#define ATA_LPT_R5		0x8c0e8086
#define ATA_LPT_R6		0x8c0f8086

#define ATA_WCPT_S1		0x8c808086
#define ATA_WCPT_S2		0x8c818086
#define ATA_WCPT_AH1		0x8c828086
#define ATA_WCPT_AH2		0x8c838086
#define ATA_WCPT_R1		0x8c848086
#define ATA_WCPT_R2		0x8c858086
#define ATA_WCPT_R3		0x8c868086
#define ATA_WCPT_R4		0x8c878086
#define ATA_WCPT_S3		0x8c888086
#define ATA_WCPT_S4		0x8c898086
#define ATA_WCPT_R5		0x8c8e8086
#define ATA_WCPT_R6		0x8c8f8086

#define ATA_WELLS_S1		0x8d008086
#define ATA_WELLS_S2		0x8d088086


#define ATA_I31244              0x32008086
#define ATA_ISCH                0x811a8086
#define ATA_DH89XXCC            0x23238086

#define ATA_COLETOCRK_AH1       0x23a38086
#define ATA_COLETOCRK_S1        0x23a18086
#define ATA_COLETOCRK_S2        0x23a68086


#define ATA_JMB368_2            0x0368197b

#define ATA_MARVELL_ID          0x11ab
#define ATA_M88SX5040           0x504011ab
#define ATA_M88SX5041           0x504111ab
#define ATA_M88SX5080           0x508011ab
#define ATA_M88SX5081           0x508111ab
#define ATA_M88SX6041           0x604111ab
#define ATA_M88SX6042           0x604211ab
#define ATA_M88SX6081           0x608111ab
#define ATA_M88SX7042           0x704211ab
#define ATA_M88SE6101           0x610111ab
#define ATA_M88SE6102           0x610211ab
#define ATA_M88SE6111           0x611111ab

#define ATA_SII3512             0x35121095
#define ATA_SII3112             0x31121095
#define ATA_SII3112_1           0x02401095
#define ATA_SII3124		0x31241095
#define ATA_SII3132		0x31321095
#define ATA_SII3132_1		0x02421095
#define ATA_SII3132_2		0x02441095
#define ATA_SII0680             0x06801095
#define ATA_CMD646              0x06461095
#define ATA_CMD648              0x06481095

int ata_mode2idx(int mode);

/* global prototypes from chipsets/ata-*.c */
int ata_ahci_chipinit(device_t);
int ata_marvell_edma_chipinit(device_t);
int ata_sii_chipinit(device_t);

/* externs */

Lines 117-127 ata_ali_chipinit(device_t dev) Link Here

(-)sys/dev/ata/chipsets/ata-acerlabs.c (-6 lines)
117	ctlr->setmode = ata_sata_setmode;	117	ctlr->setmode = ata_sata_setmode;
118	ctlr->getrev = ata_sata_getrev;	118	ctlr->getrev = ata_sata_getrev;
119		119
120	/* AHCI mode is correctly supported only on the ALi 5288. */
121	if ((ctlr->chip->chipid == ATA_ALI_5288) &&
122	(ata_ahci_chipinit(dev) != ENXIO))
123	return 0;
124
125	/* Allocate resources for later use by channel attach routines. */	120	/* Allocate resources for later use by channel attach routines. */
126	res = malloc(sizeof(struct ali_sata_resources), M_ATAPCI, M_WAITOK);	121	res = malloc(sizeof(struct ali_sata_resources), M_ATAPCI, M_WAITOK);
127	for (i = 0; i < 4; i++) {	122	for (i = 0; i < 4; i++) {
Lines 347-350 ata_ali_setmode(device_t dev, int target, int mode Link Here
347	}	342	}
348		343
349	ATA_DECLARE_DRIVER(ata_ali);	344	ATA_DECLARE_DRIVER(ata_ali);
350	MODULE_DEPEND(ata_ali, ata_ahci, 1, 1, 1);




/*-
 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer,
 *    without modification, immediately at the beginning of the file.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");

#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/ata.h>
#include <sys/bus.h>
#include <sys/endian.h>
#include <sys/malloc.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/sema.h>
#include <sys/taskqueue.h>
#include <vm/uma.h>
#include <machine/stdarg.h>
#include <machine/resource.h>
#include <machine/bus.h>
#include <sys/rman.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/ata/ata-all.h>
#include <dev/ata/ata-pci.h>
#include <ata_if.h>

/* misc defines */
#define MV_60XX		60		//must match ata_marvell.c's definition
#define MV_7042		72		//must match ata_marvell.c's definition

/*
 * Adaptec chipset support functions
 */
static int
ata_adaptec_probe(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(dev);
    static const struct ata_chip_id ids[] =
    {{ ATA_ADAPTEC_1420, 0, 4, MV_60XX, ATA_SA300, "1420SA" },
     { ATA_ADAPTEC_1430, 0, 4, MV_7042, ATA_SA300, "1430SA" },
     { 0, 0, 0, 0, 0, 0}};

    if (pci_get_vendor(dev) != ATA_ADAPTEC_ID)
	return ENXIO;

    if (!(ctlr->chip = ata_match_chip(dev, ids)))
	return ENXIO;

    ata_set_desc(dev);
    ctlr->chipinit = ata_marvell_edma_chipinit;

    return (BUS_PROBE_LOW_PRIORITY);
}

ATA_DECLARE_DRIVER(ata_adaptec);
MODULE_DEPEND(ata_adaptec, ata_marvell, 1, 1, 1);




/*-
 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer,
 *    without modification, immediately at the beginning of the file.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");

#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/ata.h>
#include <sys/bus.h>
#include <sys/endian.h>
#include <sys/malloc.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/sema.h>
#include <sys/taskqueue.h>
#include <vm/uma.h>
#include <machine/stdarg.h>
#include <machine/resource.h>
#include <machine/bus.h>
#include <sys/rman.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/ata/ata-all.h>
#include <dev/ata/ata-pci.h>
#include <ata_if.h>

/* local prototypes */
static int ata_ahci_ch_attach(device_t dev);
static int ata_ahci_ch_detach(device_t dev);
static int ata_ahci_ch_suspend(device_t dev);
static int ata_ahci_ch_resume(device_t dev);
static int ata_ahci_ctlr_reset(device_t dev);
static void ata_ahci_reset(device_t dev);
static int ata_ahci_suspend(device_t dev);
static int ata_ahci_status(device_t dev);
static int ata_ahci_begin_transaction(struct ata_request *request);
static int ata_ahci_end_transaction(struct ata_request *request);
static int ata_ahci_pm_read(device_t dev, int port, int reg, u_int32_t *result);
static int ata_ahci_pm_write(device_t dev, int port, int reg, u_int32_t result);
static int ata_ahci_hardreset(device_t dev, int port, uint32_t *signature);
static u_int32_t ata_ahci_softreset(device_t dev, int port);
static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *equest);
static void ata_ahci_dmainit(device_t dev);
static void ata_ahci_start(device_t dev);
static void ata_ahci_stop(device_t dev);
static void ata_ahci_clo(device_t dev);
static void ata_ahci_start_fr(device_t dev);
static void ata_ahci_stop_fr(device_t dev);

/*
 * AHCI v1.x compliant SATA chipset support functions
 */
static int
ata_ahci_probe(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(dev);
    char buffer[64];

    /* is this a possible AHCI candidate ? */
    if (pci_get_class(dev) != PCIC_STORAGE ||
	pci_get_subclass(dev) != PCIS_STORAGE_SATA)
	    return (ENXIO);

    /* is this PCI device flagged as an AHCI compliant chip ? */
    if (pci_get_progif(dev) != PCIP_STORAGE_SATA_AHCI_1_0)
	return (ENXIO);

    if (bootverbose)
	sprintf(buffer, "%s (ID=%08x) AHCI controller", 
		ata_pcivendor2str(dev), pci_get_devid(dev));
    else
	sprintf(buffer, "%s AHCI controller", ata_pcivendor2str(dev));
    device_set_desc_copy(dev, buffer);
    ctlr->chipinit = ata_ahci_chipinit;
    return (BUS_PROBE_GENERIC);
}

static int
ata_ahci_ata_probe(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(dev);

    if ((intptr_t)device_get_ivars(dev) >= 0)
	    return (ENXIO);
    device_set_desc_copy(dev, "AHCI SATA controller");
    ctlr->chipinit = ata_ahci_chipinit;
    return (BUS_PROBE_GENERIC);
}

static int
ata_ahci_ata_attach(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(dev);
    device_t child;
    int unit;

    /* do chipset specific setups only needed once */
    ctlr->legacy = 0;
    ctlr->ichannels = -1;
    ctlr->ch_attach = ata_pci_ch_attach;
    ctlr->ch_detach = ata_pci_ch_detach;
    ctlr->dev = dev;
    if (ctlr->chipinit(dev))
	return ENXIO;
    /* attach all channels on this controller */
    for (unit = 0; unit < ctlr->channels; unit++) {
	if ((ctlr->ichannels & (1 << unit)) == 0)
	    continue;
	child = device_add_child(dev, "ata",
	    ((unit == 0 || unit == 1) && ctlr->legacy) ?
	    unit : devclass_find_free_unit(ata_devclass, 2));
	if (child == NULL)
	    device_printf(dev, "failed to add ata child device\n");
	else
	    device_set_ivars(child, (void *)(intptr_t)unit);
    }
    bus_generic_attach(dev);
    return 0;
}

int
ata_ahci_chipinit(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(dev);
    int error, speed;
    u_int32_t caps, version;

    /* if we have a memory BAR(5) we are likely on an AHCI part */
    ctlr->r_type2 = SYS_RES_MEMORY;
    ctlr->r_rid2 = PCIR_BAR(5);
    if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
					       &ctlr->r_rid2, RF_ACTIVE)))
	return ENXIO;

    /* setup interrupt delivery if not done allready by a vendor driver */
    if (!ctlr->r_irq) {
	if (ata_setup_interrupt(dev, ata_generic_intr)) {
	    bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
	    return ENXIO;
	}
    }
    else
	device_printf(dev, "AHCI called from vendor specific driver\n");

    /* reset controller */
    if ((error = ata_ahci_ctlr_reset(dev)) != 0) {
	bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
	return (error);
    };

    /* get the number of HW channels */
    ctlr->ichannels = ATA_INL(ctlr->r_res2, ATA_AHCI_PI);
    ctlr->channels = MAX(flsl(ctlr->ichannels),
	    (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_NPMASK) + 1);
    if (pci_get_devid(dev) == ATA_M88SE6111)
	    ctlr->channels = 1;
    else if (pci_get_devid(dev) == ATA_M88SE6121)
	    ctlr->channels = 2;
    else if (pci_get_devid(dev) == ATA_M88SE6141 ||
	pci_get_devid(dev) == ATA_M88SE6145)
	    ctlr->channels = 4;

    ctlr->reset = ata_ahci_reset;
    ctlr->ch_attach = ata_ahci_ch_attach;
    ctlr->ch_detach = ata_ahci_ch_detach;
    ctlr->ch_suspend = ata_ahci_ch_suspend;
    ctlr->ch_resume = ata_ahci_ch_resume;
    ctlr->setmode = ata_sata_setmode;
    ctlr->getrev = ata_sata_getrev;
    ctlr->suspend = ata_ahci_suspend;
    ctlr->resume = ata_ahci_ctlr_reset;

	/* announce we support the HW */
	version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
	caps = ATA_INL(ctlr->r_res2, ATA_AHCI_CAP);
	speed = (caps & ATA_AHCI_CAP_ISS) >> ATA_AHCI_CAP_ISS_SHIFT;
	device_printf(dev,
		    "AHCI v%x.%02x controller with %d %sGbps ports, PM %s\n",
		    ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
		    ((version >> 4) & 0xf0) + (version & 0x0f),
		    (caps & ATA_AHCI_CAP_NPMASK) + 1,
		    ((speed == 1) ? "1.5":((speed == 2) ? "3":
		    ((speed == 3) ? "6":"?"))),
		    (caps & ATA_AHCI_CAP_SPM) ?
		    "supported" : "not supported");
	if (bootverbose) {
		device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
		    (caps & ATA_AHCI_CAP_64BIT) ? " 64bit":"",
		    (caps & ATA_AHCI_CAP_SNCQ) ? " NCQ":"",
		    (caps & ATA_AHCI_CAP_SSNTF) ? " SNTF":"",
		    (caps & ATA_AHCI_CAP_SMPS) ? " MPS":"",
		    (caps & ATA_AHCI_CAP_SSS) ? " SS":"",
		    (caps & ATA_AHCI_CAP_SALP) ? " ALP":"",
		    (caps & ATA_AHCI_CAP_SAL) ? " AL":"",
		    (caps & ATA_AHCI_CAP_SCLO) ? " CLO":"",
		    ((speed == 1) ? "1.5":((speed == 2) ? "3":
		    ((speed == 3) ? "6":"?"))));
		printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
		    (caps & ATA_AHCI_CAP_SAM) ? " AM":"",
		    (caps & ATA_AHCI_CAP_SPM) ? " PM":"",
		    (caps & ATA_AHCI_CAP_FBSS) ? " FBS":"",
		    (caps & ATA_AHCI_CAP_PMD) ? " PMD":"",
		    (caps & ATA_AHCI_CAP_SSC) ? " SSC":"",
		    (caps & ATA_AHCI_CAP_PSC) ? " PSC":"",
		    ((caps & ATA_AHCI_CAP_NCS) >> ATA_AHCI_CAP_NCS_SHIFT) + 1,
		    (caps & ATA_AHCI_CAP_CCCS) ? " CCC":"",
		    (caps & ATA_AHCI_CAP_EMS) ? " EM":"",
		    (caps & ATA_AHCI_CAP_SXS) ? " eSATA":"",
		    (caps & ATA_AHCI_CAP_NPMASK) + 1);
	}
	return 0;
}

static int
ata_ahci_ctlr_reset(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(dev);
    int timeout;

    /* enable AHCI mode */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);

    /* reset AHCI controller */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE|ATA_AHCI_GHC_HR);
    for (timeout = 1000; timeout > 0; timeout--) {
	    DELAY(1000);
	    if ((ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) == 0)
		    break;
    }
    if (timeout == 0) {
	device_printf(dev, "AHCI controller reset failure\n");
	return ENXIO;
    }

    /* reenable AHCI mode */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);

    /* clear interrupts */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));

    /* enable AHCI interrupts */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
	     ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);

    return 0;
}

static int
ata_ahci_suspend(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(dev);

    /* disable interupts so the state change(s) doesn't trigger */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
             ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & (~ATA_AHCI_GHC_IE));
    return 0;
}

static int
ata_ahci_ch_attach(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    int offset = ch->unit << 7;

    ata_ahci_dmainit(dev);

    /* set the SATA resources */
    ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
    ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
    ch->r_io[ATA_SERROR].res = ctlr->r_res2;
    ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
    ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
    ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
    ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
    ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;

    ch->hw.status = ata_ahci_status;
    ch->hw.begin_transaction = ata_ahci_begin_transaction;
    ch->hw.end_transaction = ata_ahci_end_transaction;
    ch->hw.command = NULL;      /* not used here */
    ch->hw.softreset = ata_ahci_softreset;
    ch->hw.pm_read = ata_ahci_pm_read;
    ch->hw.pm_write = ata_ahci_pm_write;
    ch->flags |= ATA_NO_SLAVE;
    ch->flags |= ATA_SATA;

    ata_ahci_ch_resume(dev);
    return 0;
}

static int
ata_ahci_ch_detach(device_t dev)
{
    struct ata_channel *ch = device_get_softc(dev);
 
    if (ch->dma.work_tag && ch->dma.work_map)
	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
    ata_ahci_ch_suspend(dev);
    ata_dmafini(dev);
    return (0);
}

static int
ata_ahci_ch_suspend(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    int offset = ch->unit << 7;

    /* Disable port interrupts. */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
    /* Reset command register. */
    ata_ahci_stop(dev);
    ata_ahci_stop_fr(dev);
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 0);

    /* Allow everything including partial and slumber modes. */
    ATA_IDX_OUTL(ch, ATA_SCONTROL, 0);
    /* Request slumber mode transition and give some time to get there. */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, ATA_AHCI_P_CMD_SLUMBER);
    DELAY(100);
    /* Disable PHY. */
    ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_DISABLE);

    return (0);
}

static int
ata_ahci_ch_resume(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    uint64_t work;
    int offset = ch->unit << 7;

    /* Disable port interrupts */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);

    /* setup work areas */
    work = ch->dma.work_bus + ATA_AHCI_CL_OFFSET;
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);

    work = ch->dma.work_bus + ATA_AHCI_FB_OFFSET;
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff); 
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);

    /* activate the channel and power/spin up device */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
	     (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD |
	     ((ch->pm_level > 1) ? ATA_AHCI_P_CMD_ALPE : 0) |
	     ((ch->pm_level > 2) ? ATA_AHCI_P_CMD_ASP : 0 )));
    ata_ahci_start_fr(dev);
    ata_ahci_start(dev);

    return (0);
}

static int
ata_ahci_status(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
    int offset = ch->unit << 7;

#define ATA_AHCI_STATBITS \
	(ATA_AHCI_P_IX_IF|ATA_AHCI_P_IX_HBD|ATA_AHCI_P_IX_HBF|ATA_AHCI_P_IX_TFE)

    if (action & (1 << ch->unit)) {
	u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
	u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);

	/* clear interrupt(s) */
	ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
	ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, 1 << ch->unit);

	/* do we have any PHY events ? */
	if (istatus & (ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC))
	    ata_sata_phy_check_events(dev, -1);

	/* do we have a potentially hanging engine to take care of? */
	/* XXX SOS what todo on NCQ */
	if ((istatus & ATA_AHCI_STATBITS) && (cstatus & 1)) {

	    u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
	    int timeout = 0;

	    /* kill off all activity on this channel */
	    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
		     cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));

	    /* XXX SOS this is not entirely wrong */
	    do {
		DELAY(1000);
		if (timeout++ > 1000) {
		    device_printf(dev, "stopping AHCI engine failed\n");
		    break;
		}
    	    } while (ATA_INL(ctlr->r_res2,
			     ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);

	    /* start operations on this channel */
	    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
		     cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));

	    return 1;
	}
	else
	    /* XXX SOS what todo on NCQ */
	    return (!(cstatus & 1));
    }
    return 0;
}

/* must be called with ATA channel locked and state_mtx held */
static int
ata_ahci_begin_transaction(struct ata_request *request)
{
    struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
    struct ata_channel *ch = device_get_softc(request->parent);
    struct ata_ahci_cmd_tab *ctp;
    struct ata_ahci_cmd_list *clp;
    int offset = ch->unit << 7;
    int port = request->unit & 0x0f;
    int entries = 0;
    int fis_size;
	
    /* get a piece of the workspace for this request */
    ctp = (struct ata_ahci_cmd_tab *)
	  (ch->dma.work + ATA_AHCI_CT_OFFSET);

    /* setup the FIS for this request */
    if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
	device_printf(request->parent, "setting up SATA FIS failed\n");
	request->result = EIO;
	return ATA_OP_FINISHED;
    }

    /* if request moves data setup and load SG list */
    if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
	if (ch->dma.load(request, ctp->prd_tab, &entries)) {
	    device_printf(request->parent, "setting up DMA failed\n");
	    request->result = EIO;
	    return ATA_OP_FINISHED;
	}
    }

    /* setup the command list entry */
    clp = (struct ata_ahci_cmd_list *)
	  (ch->dma.work + ATA_AHCI_CL_OFFSET);

    clp->prd_length = entries;
    clp->cmd_flags = (request->flags & ATA_R_WRITE ? ATA_AHCI_CMD_WRITE : 0) |
		     (request->flags & ATA_R_ATAPI ?
		      (ATA_AHCI_CMD_ATAPI | ATA_AHCI_CMD_PREFETCH) : 0) |
		     (fis_size / sizeof(u_int32_t)) |
    		     (port << 12);
    clp->bytecount = 0;
    clp->cmd_table_phys = htole64(ch->dma.work_bus + ATA_AHCI_CT_OFFSET);

    /* set command type bit */
    if (request->flags & ATA_R_ATAPI)
	ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
		 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
		 ATA_AHCI_P_CMD_ATAPI);
    else
	ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
		 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
		 ~ATA_AHCI_P_CMD_ATAPI);

    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
	BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

    /* issue command to controller */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, 1);
    
    if (!(request->flags & ATA_R_ATAPI)) {
	/* device reset doesn't interrupt */
	if (request->u.ata.command == ATA_DEVICE_RESET) {
	    u_int32_t tf_data;
	    int timeout = 1000000;

	    do {
		DELAY(10);
		tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
	    } while ((tf_data & ATA_S_BUSY) && timeout--);
	    if (bootverbose)
		device_printf(ch->dev, "device_reset timeout=%dus\n",
			      (1000000-timeout)*10);
	    request->status = tf_data;
	    if (request->status & ATA_S_ERROR)
		request->error = tf_data >> 8;
	    return ATA_OP_FINISHED;
	}
    }

    /* start the timeout */
    callout_reset(&request->callout, request->timeout * hz,
		  (timeout_t*)ata_timeout, request);
    return ATA_OP_CONTINUES;
}

/* must be called with ATA channel locked and state_mtx held */
static int
ata_ahci_end_transaction(struct ata_request *request)
{
    struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
    struct ata_channel *ch = device_get_softc(request->parent);
    struct ata_ahci_cmd_list *clp;
    u_int32_t tf_data;
    int offset = ch->unit << 7;

    /* kill the timeout */
    callout_stop(&request->callout);

    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
	BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);

    /* get status */
    tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
    request->status = tf_data;

    /* if error status get details */
    if (request->status & ATA_S_ERROR)  
	request->error = tf_data >> 8;

    /* Read back registers to the request struct. */
    if ((request->flags & ATA_R_ATAPI) == 0 &&
	((request->status & ATA_S_ERROR) ||
	 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT)))) {
	u_int8_t *fis = ch->dma.work + ATA_AHCI_FB_OFFSET + 0x40;

	request->u.ata.count = fis[12] | ((u_int16_t)fis[13] << 8);
	request->u.ata.lba = fis[4] | ((u_int64_t)fis[5] << 8) |
			     ((u_int64_t)fis[6] << 16);
	if (request->flags & ATA_R_48BIT)
	    request->u.ata.lba |= ((u_int64_t)fis[8] << 24) |
				  ((u_int64_t)fis[9] << 32) |
				  ((u_int64_t)fis[10] << 40);
	else
	    request->u.ata.lba |= ((u_int64_t)(fis[7] & 0x0f) << 24);
    }

    /* record how much data we actually moved */
    clp = (struct ata_ahci_cmd_list *)
	  (ch->dma.work + ATA_AHCI_CL_OFFSET);
    request->donecount = le32toh(clp->bytecount);

    /* release SG list etc */
    ch->dma.unload(request);

    return ATA_OP_FINISHED;
}

static int
ata_ahci_issue_cmd(device_t dev, u_int16_t flags, int timeout)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    struct ata_ahci_cmd_list *clp =
	(struct ata_ahci_cmd_list *)(ch->dma.work + ATA_AHCI_CL_OFFSET);
    struct ata_ahci_cmd_tab *ctp =
	(struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
    u_int32_t status = 0;
    int offset = ch->unit << 7;
    int port = (ctp->cfis[1] & 0x0f);
    int count;

    clp->prd_length = 0;
    clp->cmd_flags = (20 / sizeof(u_int32_t)) | flags | (port << 12);
    clp->bytecount = 0;
    clp->cmd_table_phys = htole64(ch->dma.work_bus + ATA_AHCI_CT_OFFSET);

    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
	BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

    /* issue command to controller */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, 1);

    /* poll for command finished */
    for (count = 0; count < timeout; count++) {
        DELAY(1000);
        if (!((status = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset)) & 1))
            break;
    }

    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
	BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);

    /* clear interrupts */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
	    ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));

    if (timeout && (count >= timeout)) {
	if (bootverbose) {
	    device_printf(dev, "ahci_issue_cmd timeout: %d of %dms, status=%08x\n",
		      count, timeout, status);
	}
	return EIO;
    }

    return 0;
}

static int
ata_ahci_pm_read(device_t dev, int port, int reg, u_int32_t *result)
{
    struct ata_channel *ch = device_get_softc(dev);
    struct ata_ahci_cmd_tab *ctp =
	(struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
    u_int8_t *fis = ch->dma.work + ATA_AHCI_FB_OFFSET + 0x40;

    if (port < 0) {
	*result = ATA_IDX_INL(ch, reg);
	return (0);
    }
    if (port < ATA_PM) {
	switch (reg) {
	case ATA_SSTATUS:
	    reg = 0;
	    break;
	case ATA_SERROR:
	    reg = 1;
	    break;
	case ATA_SCONTROL:
	    reg = 2;
	    break;
	default:
	    return (EINVAL);
	}
    }
    bzero(ctp->cfis, 64);
    ctp->cfis[0] = 0x27;	/* host to device */
    ctp->cfis[1] = 0x8f;	/* command FIS to PM port */
    ctp->cfis[2] = ATA_READ_PM;
    ctp->cfis[3] = reg;
    ctp->cfis[7] = port | ATA_D_LBA;
    ctp->cfis[15] = ATA_A_4BIT;

    if (ata_ahci_issue_cmd(dev, 0, 10)) {
	device_printf(dev, "error reading PM port\n");
	return EIO;
    }

    *result = fis[12] | (fis[4] << 8) | (fis[5] << 16) | (fis[6] << 24);
    return 0;
}

static int
ata_ahci_pm_write(device_t dev, int port, int reg, u_int32_t value)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    struct ata_ahci_cmd_tab *ctp =
	(struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
    int offset = ch->unit << 7;

    if (port < 0) {
	ATA_IDX_OUTL(ch, reg, value);
	return (0);
    }
    if (port < ATA_PM) {
	switch (reg) {
	case ATA_SSTATUS:
	    reg = 0;
	    break;
	case ATA_SERROR:
	    reg = 1;
	    break;
	case ATA_SCONTROL:
	    reg = 2;
	    break;
	default:
	    return (EINVAL);
	}
    }
    bzero(ctp->cfis, 64);
    ctp->cfis[0] = 0x27;	/* host to device */
    ctp->cfis[1] = 0x8f;	/* command FIS to PM port */
    ctp->cfis[2] = ATA_WRITE_PM;
    ctp->cfis[3] = reg;
    ctp->cfis[7] = port | ATA_D_LBA;
    ctp->cfis[12] = value & 0xff;
    ctp->cfis[4] = (value >> 8) & 0xff;
    ctp->cfis[5] = (value >> 16) & 0xff;
    ctp->cfis[6] = (value >> 24) & 0xff;
    ctp->cfis[15] = ATA_A_4BIT;

    if (ata_ahci_issue_cmd(dev, 0, 100)) {
	device_printf(dev, "error writing PM port\n");
	return ATA_E_ABORT;
    }

    return (ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset) >> 8) & 0xff;
}

static void
ata_ahci_stop(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    u_int32_t cmd;
    int offset = ch->unit << 7;
    int timeout;

    /* kill off all activity on this channel */
    cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
	     cmd & ~ATA_AHCI_P_CMD_ST);

    /* XXX SOS this is not entirely wrong */
    timeout = 0;
    do {
	DELAY(1000);
	if (timeout++ > 1000) {
	    device_printf(dev, "stopping AHCI engine failed\n");
	    break;
	}
    }
    while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
}

static void
ata_ahci_clo(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    u_int32_t cmd;
    int offset = ch->unit << 7;
    int timeout;

    /* issue Command List Override if supported */ 
    if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_SCLO) {
	cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
	cmd |= ATA_AHCI_P_CMD_CLO;
	ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
	timeout = 0;
	do {
	    DELAY(1000);
	    if (timeout++ > 1000) {
		device_printf(dev, "executing CLO failed\n");
		break;
	    }
        }
	while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
    }
}

static void
ata_ahci_start(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    u_int32_t cmd;
    int offset = ch->unit << 7;

    /* clear SATA error register */
    ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));

    /* clear any interrupts pending on this channel */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
	     ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));

    /* start operations on this channel */
    cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
	     cmd | ATA_AHCI_P_CMD_ST |
	     (ch->devices & ATA_PORTMULTIPLIER ? ATA_AHCI_P_CMD_PMA : 0));
}

static void
ata_ahci_stop_fr(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    u_int32_t cmd;
    int offset = ch->unit << 7;
    int timeout;

    /* kill off all activity on this channel */
    cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd & ~ATA_AHCI_P_CMD_FRE);

    timeout = 0;
    do {
	DELAY(1000);
	if (timeout++ > 1000) {
	    device_printf(dev, "stopping AHCI FR engine failed\n");
	    break;
	}
    }
    while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_FR);
}

static void
ata_ahci_start_fr(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    u_int32_t cmd;
    int offset = ch->unit << 7;

    /* start FIS reception on this channel */
    cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd | ATA_AHCI_P_CMD_FRE);
}

static int
ata_ahci_wait_ready(device_t dev, int t)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    int offset = ch->unit << 7;
    int timeout = 0;
    uint32_t val;

    while ((val = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset)) &
	(ATA_S_BUSY | ATA_S_DRQ)) {
	    DELAY(1000);
	    if (timeout++ > t) {
		device_printf(dev, "port is not ready (timeout %dms) tfd = %08x\n", t, val);
		return (EBUSY);
	    }
    } 
    if (bootverbose)
	device_printf(dev, "ready wait time=%dms\n", timeout);
    return (0);
}

static int
ata_ahci_hardreset(device_t dev, int port, uint32_t *signature)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    int offset = ch->unit << 7;

    *signature = 0xffffffff;
    ata_ahci_stop(dev);
    /* Reset port */
    if (!ata_sata_phy_reset(dev, port, 0))
	return (ENOENT);
    /* Wait for clearing busy status. */
    if (ata_ahci_wait_ready(dev, 15000)) {
	device_printf(dev, "hardware reset timeout\n");
	return (EBUSY);
    }
    *signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
    ata_ahci_start(dev);
    return (0);
}

static u_int32_t
ata_ahci_softreset(device_t dev, int port)
{
    struct ata_channel *ch = device_get_softc(dev);
    struct ata_ahci_cmd_tab *ctp =
	(struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
    u_int8_t *fis = ch->dma.work + ATA_AHCI_FB_OFFSET + 0x40;

    if (bootverbose)
	device_printf(dev, "software reset port %d...\n", port);

    /* kick controller into sane state */
    ata_ahci_stop(dev);
    ata_ahci_clo(dev);
    ata_ahci_start(dev);

    /* pull reset active */
    bzero(ctp->cfis, 64);
    ctp->cfis[0] = 0x27;
    ctp->cfis[1] = port & 0x0f;
    //ctp->cfis[7] = ATA_D_LBA | ATA_D_IBM;
    ctp->cfis[15] = (ATA_A_4BIT | ATA_A_RESET);

    if (ata_ahci_issue_cmd(dev, ATA_AHCI_CMD_RESET | ATA_AHCI_CMD_CLR_BUSY,100)) {
	device_printf(dev, "software reset set timeout\n");
	return (-1);
    }

    ata_udelay(50);

    /* pull reset inactive -> device softreset */
    bzero(ctp->cfis, 64);
    ctp->cfis[0] = 0x27;
    ctp->cfis[1] = port & 0x0f;
    //ctp->cfis[7] = ATA_D_LBA | ATA_D_IBM;
    ctp->cfis[15] = ATA_A_4BIT;
    ata_ahci_issue_cmd(dev, 0, 3000);

    if (ata_ahci_wait_ready(dev, 0)) {
	device_printf(dev, "software reset clear timeout\n");
	return (-1);
    }

    return (((u_int32_t)fis[6] << 24) |
	    ((u_int32_t)fis[5] << 16) |
	    ((u_int32_t)fis[4] << 8) |
	     (u_int32_t)fis[12]);
}

static void
ata_ahci_reset(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    u_int32_t signature;
    int offset = ch->unit << 7;

    if (bootverbose)
        device_printf(dev, "AHCI reset...\n");

    /* Disable port interrupts */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);

    if (ata_ahci_hardreset(dev, -1, &signature)) {
	if (bootverbose)
	    device_printf(dev, "AHCI reset done: phy reset found no device\n");
	ch->devices = 0;

	/* enable wanted port interrupts */
	ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
	     (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC));
	return;
    }

    /* enable wanted port interrupts */
    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
	     (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
	      ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
	      ((ch->pm_level == 0) ? ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC : 0) |
	      ATA_AHCI_P_IX_DP | ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB |
	      ATA_AHCI_P_IX_DS | ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
    /*
     * Only probe for PortMultiplier if HW has support.
     * Ignore Marvell, which is not working,
     */
    if ((ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_SPM) &&
	    pci_get_vendor(ctlr->dev) != 0x11ab) {
	signature = ata_ahci_softreset(dev, ATA_PM);
	/* Workaround for some ATI chips, failing to soft-reset
	 * when port multiplicator supported, but absent.
	 * XXX: We can also check PxIS.IPMS==1 here to be sure. */
	if (signature == 0xffffffff)
	    signature = ata_ahci_softreset(dev, 0);
    } else {
	signature = ata_ahci_softreset(dev, 0);
    }
    if (bootverbose)
	device_printf(dev, "SIGNATURE: %08x\n", signature);

    switch (signature >> 16) {
    case 0x0000:
	ch->devices = ATA_ATA_MASTER;
	break;
    case 0x9669:
	ch->devices = ATA_PORTMULTIPLIER;
	ata_pm_identify(dev);
	break;
    case 0xeb14:
	ch->devices = ATA_ATAPI_MASTER;
	break;
    default: /* SOS XXX */
	if (bootverbose)
	    device_printf(dev, "Unknown signature, assuming disk device\n");
	ch->devices = ATA_ATA_MASTER;
    }
    if (bootverbose)
        device_printf(dev, "AHCI reset done: devices=%08x\n", ch->devices);
}

static void
ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
{    
    struct ata_dmasetprd_args *args = xsc;
    struct ata_ahci_dma_prd *prd = args->dmatab;
    int i;

    if (!(args->error = error)) {
	for (i = 0; i < nsegs; i++) {
	    prd[i].dba = htole64(segs[i].ds_addr);
	    prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
	}
    }

    KASSERT(nsegs <= ATA_AHCI_DMA_ENTRIES, ("too many DMA segment entries\n"));
    args->nsegs = nsegs;
}

static void
ata_ahci_dmainit(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);

    /* note start and stop are not used here */
    ch->dma.setprd = ata_ahci_dmasetprd;
    ch->dma.max_iosize = (ATA_AHCI_DMA_ENTRIES - 1) * PAGE_SIZE;
    if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
	ch->dma.max_address = BUS_SPACE_MAXADDR;
    ata_dmainit(dev);
}

static int
ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
{
    bzero(ctp->cfis, 64);
    if (request->flags & ATA_R_ATAPI) {
	bzero(ctp->acmd, 32);
	bcopy(request->u.atapi.ccb, ctp->acmd, 16);
    }
    return ata_request2fis_h2d(request, &ctp->cfis[0]);
}

ATA_DECLARE_DRIVER(ata_ahci);
static device_method_t ata_ahci_ata_methods[] = {
    DEVMETHOD(device_probe,     ata_ahci_ata_probe),
    DEVMETHOD(device_attach,    ata_ahci_ata_attach),
    DEVMETHOD(device_detach,    ata_pci_detach),
    DEVMETHOD(device_suspend,   ata_pci_suspend),
    DEVMETHOD(device_resume,    ata_pci_resume),
    DEVMETHOD(device_shutdown,  bus_generic_shutdown),
    DEVMETHOD(bus_read_ivar,		ata_pci_read_ivar),
    DEVMETHOD(bus_write_ivar,		ata_pci_write_ivar),
    DEVMETHOD(bus_alloc_resource,       ata_pci_alloc_resource),
    DEVMETHOD(bus_release_resource,     ata_pci_release_resource),
    DEVMETHOD(bus_activate_resource,    bus_generic_activate_resource),
    DEVMETHOD(bus_deactivate_resource,  bus_generic_deactivate_resource),
    DEVMETHOD(bus_setup_intr,           ata_pci_setup_intr),
    DEVMETHOD(bus_teardown_intr,        ata_pci_teardown_intr),
    DEVMETHOD_END
};
static driver_t ata_ahci_ata_driver = {
        "atapci",
        ata_ahci_ata_methods,
        sizeof(struct ata_pci_controller)
};
DRIVER_MODULE(ata_ahci_ata, atapci, ata_ahci_ata_driver, ata_pci_devclass,
    NULL, NULL);




#define ATI_PATA	0x02
#define ATI_AHCI	0x04

static int force_ahci = 1;
TUNABLE_INT("hw.ahci.force", &force_ahci);

/*
 * ATI chipset support functions
 */

    if (!(ctlr->chip = ata_match_chip(dev, ids)))
	return ENXIO;

    ata_set_desc(dev);

    switch (ctlr->chip->cfg1) {
    case ATI_PATA:
	ctlr->chipinit = ata_ati_chipinit;

	ctlr->chipinit = ata_sii_chipinit;
	break;
    case ATI_AHCI:
	if (pci_get_subclass(dev) != PCIS_STORAGE_IDE)
		return (ENXIO);
	ctlr->chipinit = ata_ati_chipinit;
		ctlr->chipinit = ata_ati_chipinit;
	break;
    }

    ata_set_desc(dev);
    return (BUS_PROBE_LOW_PRIORITY);
}


}

ATA_DECLARE_DRIVER(ata_ati);
MODULE_DEPEND(ata_ati, ata_ahci, 1, 1, 1);
MODULE_DEPEND(ata_ati, ata_sii, 1, 1, 1);




static void ata_intel_31244_reset(device_t dev);

/* misc defines */
#define INTEL_AHCI	1
#define INTEL_ICH5	2
#define INTEL_6CH	4
#define INTEL_6CH2	8

     { ATA_I6300ESB_S1,  0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" },
     { ATA_I6300ESB_R1,  0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" },
     { ATA_I82801FB,     0,          0, 2, ATA_UDMA5, "ICH6" },
     { ATA_I82801FB_S1,  0,          0, 0, ATA_SA150, "ICH6" },
     { ATA_I82801FB_R1,  0,          0, 0, ATA_SA150, "ICH6" },
     { ATA_I82801FBM,    0,          0, 0, ATA_SA150, "ICH6M" },
     { ATA_I82801GB,     0,          0, 1, ATA_UDMA5, "ICH7" },
     { ATA_I82801GB_S1,  0, INTEL_ICH7, 0, ATA_SA300, "ICH7" },
     { ATA_I82801GB_R1,  0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
     { ATA_I82801GB_AH,  0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
     { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" },
     { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
     { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
     { ATA_I63XXESB2,    0,          0, 1, ATA_UDMA5, "63XXESB2" },
     { ATA_I63XXESB2_S1, 0,          0, 0, ATA_SA300, "63XXESB2" },
     { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
     { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
     { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
     { ATA_I82801HB_S1,  0, INTEL_6CH,  0, ATA_SA300, "ICH8" },
     { ATA_I82801HB_S2,  0, INTEL_6CH2, 0, ATA_SA300, "ICH8" },
     { ATA_I82801HB_R1,  0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
     { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
     { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
     { ATA_I82801HBM,    0,          0, 1, ATA_UDMA5, "ICH8M" },
     { ATA_I82801HBM_S1, 0, INTEL_6CH,  0, ATA_SA300, "ICH8M" },
     { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
     { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
     { ATA_I82801IB_S1,  0, INTEL_6CH,  0, ATA_SA300, "ICH9" },
     { ATA_I82801IB_S2,  0, INTEL_6CH2, 0, ATA_SA300, "ICH9" },
     { ATA_I82801IB_S3,  0, INTEL_6CH2, 0, ATA_SA300, "ICH9" },
     { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
     { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
     { ATA_I82801IB_R1,  0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
     { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },
     { ATA_I82801IBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" },
     { ATA_I82801IBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" },
     { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },
     { ATA_I82801JIB_S1, 0, INTEL_6CH,  0, ATA_SA300, "ICH10" },
     { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
     { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
     { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
     { ATA_I82801JD_S1,  0, INTEL_6CH,  0, ATA_SA300, "ICH10" },
     { ATA_I82801JD_AH,  0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
     { ATA_I82801JD_R1,  0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
     { ATA_I82801JD_S2,  0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
     { ATA_I82801JI_S1,  0, INTEL_6CH,  0, ATA_SA300, "ICH10" },
     { ATA_I82801JI_AH,  0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
     { ATA_I82801JI_R1,  0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
     { ATA_I82801JI_S2,  0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
     { ATA_5Series_S1,   0, INTEL_6CH,  0, ATA_SA300, "5 Series/3400 Series PCH" },
     { ATA_5Series_S2,   0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
     { ATA_5Series_AH1,  0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
     { ATA_5Series_AH2,  0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
     { ATA_5Series_R1,   0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
     { ATA_5Series_S3,   0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
     { ATA_5Series_S4,   0, INTEL_6CH,  0, ATA_SA300, "5 Series/3400 Series PCH" },
     { ATA_5Series_AH3,  0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
     { ATA_5Series_R2,   0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
     { ATA_5Series_S5,   0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
     { ATA_5Series_S6,   0, INTEL_6CH,  0, ATA_SA300, "5 Series/3400 Series PCH" },
     { ATA_5Series_AH4,  0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
     { ATA_CPT_S1,       0, INTEL_6CH,  0, ATA_SA300, "Cougar Point" },
     { ATA_CPT_S2,       0, INTEL_6CH,  0, ATA_SA300, "Cougar Point" },
     { ATA_CPT_AH1,      0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
     { ATA_CPT_AH2,      0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
     { ATA_CPT_R1,       0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
     { ATA_CPT_R2,       0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
     { ATA_CPT_S3,       0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" },
     { ATA_CPT_S4,       0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" },
     { ATA_PBG_S1,       0, INTEL_6CH,  0, ATA_SA300, "Patsburg" },
     { ATA_PBG_AH1,      0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
     { ATA_PBG_R1,       0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
     { ATA_PBG_R2,       0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
     { ATA_PBG_R3,       0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
     { ATA_PBG_S2,       0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" },
     { ATA_PPT_S1,       0, INTEL_6CH,  0, ATA_SA300, "Panther Point" },
     { ATA_PPT_S2,       0, INTEL_6CH,  0, ATA_SA300, "Panther Point" },
     { ATA_PPT_AH1,      0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
     { ATA_PPT_AH2,      0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
     { ATA_PPT_R1,       0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
     { ATA_PPT_R2,       0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
     { ATA_PPT_R3,       0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
     { ATA_PPT_R4,       0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
     { ATA_PPT_S3,       0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" },
     { ATA_PPT_S4,       0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" },
     { ATA_PPT_R5,       0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
     { ATA_PPT_R6,       0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
     { ATA_AVOTON_S1,    0, INTEL_6CH,  0, ATA_SA300, "Avoton" },
     { ATA_AVOTON_S2,    0, INTEL_6CH,  0, ATA_SA300, "Avoton" },
     { ATA_AVOTON_S3,    0, INTEL_6CH2, 0, ATA_SA300, "Avoton" },

     { ATA_AVOTON_S4,    0, INTEL_6CH2, 0, ATA_SA300, "Avoton" },
     { ATA_LPT_S1,       0, INTEL_6CH,  0, ATA_SA300, "Lynx Point" },
     { ATA_LPT_S2,       0, INTEL_6CH,  0, ATA_SA300, "Lynx Point" },
     { ATA_LPT_AH1,      0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
     { ATA_LPT_AH2,      0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
     { ATA_LPT_R1,       0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
     { ATA_LPT_R2,       0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
     { ATA_LPT_R3,       0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
     { ATA_LPT_R4,       0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
     { ATA_LPT_S3,       0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" },
     { ATA_LPT_S4,       0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" },
     { ATA_LPT_R5,       0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
     { ATA_LPT_R6,       0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
     { ATA_WCPT_S1,      0, INTEL_6CH,  0, ATA_SA300, "Wildcat Point" },
     { ATA_WCPT_S2,      0, INTEL_6CH,  0, ATA_SA300, "Wildcat Point" },
     { ATA_WCPT_AH1,     0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
     { ATA_WCPT_AH2,     0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
     { ATA_WCPT_R1,      0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
     { ATA_WCPT_R2,      0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
     { ATA_WCPT_R3,      0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
     { ATA_WCPT_R4,      0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
     { ATA_WCPT_S3,      0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" },
     { ATA_WCPT_S4,      0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" },
     { ATA_WCPT_R5,      0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
     { ATA_WCPT_R6,      0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
     { ATA_WELLS_S1,     0, INTEL_6CH,  0, ATA_SA300, "Wellsburg" },
     { ATA_WELLS_S2,     0, INTEL_6CH2, 0, ATA_SA300, "Wellsburg" },
     { ATA_WELLS_S3,     0, INTEL_6CH,  0, ATA_SA300, "Wellsburg" },

     { ATA_LPTLP_S4,     0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" },
     { ATA_I31244,       0,          0, 2, ATA_SA150, "31244" },
     { ATA_ISCH,         0,          0, 1, ATA_UDMA5, "SCH" },
     { ATA_DH89XXCC,     0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" },
     { ATA_COLETOCRK_S1, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" },
     { ATA_COLETOCRK_S2, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" },
     { ATA_COLETOCRK_AH1,0, INTEL_AHCI, 0, ATA_SA300, "COLETOCRK" },
     { 0, 0, 0, 0, 0, 0}};

    if (pci_get_vendor(dev) != ATA_INTEL_ID)

	ctlr->ch_detach = ata_pci_ch_detach;
	ctlr->reset = ata_intel_reset;

	/* 
	 * if we have AHCI capability and AHCI or RAID mode enabled
	 * in BIOS we try for AHCI mode
	 */ 
	if ((ctlr->chip->cfg1 & INTEL_AHCI) &&
	    (pci_read_config(dev, 0x90, 1) & 0xc0) &&
	    (ata_ahci_chipinit(dev) != ENXIO))
	    return 0;

	/* BAR(5) may point to SATA interface registers */
	if ((ctlr->chip->cfg1 & INTEL_ICH7)) {
		ctlr->r_type2 = SYS_RES_MEMORY;

}

ATA_DECLARE_DRIVER(ata_intel);
MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1);

Lines 100-110 ata_jmicron_chipinit(device_t dev) Link Here

(-)sys/dev/ata/chipsets/ata-jmicron.c (-6 / +1 lines)
100		100
101	/* do we have multiple PCI functions ? */	101	/* do we have multiple PCI functions ? */
102	if (pci_read_config(dev, 0xdf, 1) & 0x40) {	102	if (pci_read_config(dev, 0xdf, 1) & 0x40) {
103	/* are we on the AHCI part ? */	103	/* If this was not claimed by AHCI, then we are on the PATA part */
104	if (ata_ahci_chipinit(dev) != ENXIO)
105	return 0;
106
107	/* otherwise we are on the PATA part */
108	ctlr->ch_attach = ata_jmicron_ch_attach;	104	ctlr->ch_attach = ata_jmicron_ch_attach;
109	ctlr->ch_detach = ata_pci_ch_detach;	105	ctlr->ch_detach = ata_pci_ch_detach;
110	ctlr->reset = ata_generic_reset;	106	ctlr->reset = ata_generic_reset;
Lines 160-163 ata_jmicron_setmode(device_t dev, int target, int Link Here
160	}	156	}
161		157
162	ATA_DECLARE_DRIVER(ata_jmicron);	158	ATA_DECLARE_DRIVER(ata_jmicron);
163	MODULE_DEPEND(ata_jmicron, ata_ahci, 1, 1, 1);




static int ata_marvell_ch_attach(device_t dev);
static int ata_marvell_setmode(device_t dev, int target, int mode);
static int ata_marvell_dummy_chipinit(device_t dev);
static int ata_marvell_edma_ch_attach(device_t dev);
static int ata_marvell_edma_ch_detach(device_t dev);
static int ata_marvell_edma_status(device_t dev);
static int ata_marvell_edma_begin_transaction(struct ata_request *request);
static int ata_marvell_edma_end_transaction(struct ata_request *request);
static void ata_marvell_edma_reset(device_t dev);
static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
static void ata_marvell_edma_dmainit(device_t dev);

/* misc defines */
#define MV_50XX		50
#define MV_60XX		60
#define MV_6042		62
#define MV_7042		72
#define MV_61XX		61
#define MV_91XX		91


{
    struct ata_pci_controller *ctlr = device_get_softc(dev);
    static const struct ata_chip_id ids[] =
    {{ ATA_M88SE6101, 0, 0, MV_61XX, ATA_UDMA6, "88SE6101" },
     { ATA_M88SX5041, 0, 4, MV_50XX, ATA_SA150, "88SX5041" },
     { ATA_M88SX5080, 0, 8, MV_50XX, ATA_SA150, "88SX5080" },
     { ATA_M88SX5081, 0, 8, MV_50XX, ATA_SA150, "88SX5081" },
     { ATA_M88SX6041, 0, 4, MV_60XX, ATA_SA300, "88SX6041" },
     { ATA_M88SX6042, 0, 4, MV_6042, ATA_SA300, "88SX6042" },
     { ATA_M88SX6081, 0, 8, MV_60XX, ATA_SA300, "88SX6081" },
     { ATA_M88SX7042, 0, 4, MV_7042, ATA_SA300, "88SX7042" },
     { ATA_M88SE6101, 0, 0, MV_61XX, ATA_UDMA6, "88SE6101" },
     { ATA_M88SE6102, 0, 0, MV_61XX, ATA_UDMA6, "88SE6102" },
     { ATA_M88SE6111, 0, 1, MV_61XX, ATA_UDMA6, "88SE6111" },
     { ATA_M88SE6121, 0, 2, MV_61XX, ATA_UDMA6, "88SE6121" },

    ata_set_desc(dev);

    switch (ctlr->chip->cfg2) {
    case MV_50XX:
    case MV_60XX:
    case MV_6042:
    case MV_7042:
	ctlr->chipinit = ata_marvell_edma_chipinit;
	break;
    case MV_61XX:
	ctlr->chipinit = ata_marvell_chipinit;
	break;

        return (0);
}

int
ata_marvell_edma_chipinit(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(dev);

    if (ata_setup_interrupt(dev, ata_generic_intr))
	return ENXIO;

    ctlr->r_type1 = SYS_RES_MEMORY;
    ctlr->r_rid1 = PCIR_BAR(0);
    if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
						&ctlr->r_rid1, RF_ACTIVE)))
	return ENXIO;

    /* mask all host controller interrupts */
    ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);

    /* mask all PCI interrupts */
    ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);

    ctlr->ch_attach = ata_marvell_edma_ch_attach;
    ctlr->ch_detach = ata_marvell_edma_ch_detach;
    ctlr->reset = ata_marvell_edma_reset;
    ctlr->setmode = ata_sata_setmode;
    ctlr->getrev = ata_sata_getrev;
    ctlr->channels = ctlr->chip->cfg1;

    /* clear host controller interrupts */
    ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
    if (ctlr->chip->cfg1 > 4)
	ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);

    /* clear PCI interrupts */
    ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);

    /* unmask PCI interrupts we want */
    ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);

    /* unmask host controller interrupts we want */
    ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
	     /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));

    return 0;
}

static int
ata_marvell_edma_ch_attach(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    u_int64_t work;
    int i;

    ata_marvell_edma_dmainit(dev);
    work = ch->dma.work_bus;
    /* clear work area */
    bzero(ch->dma.work, 1024+256);
    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
	BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

    /* set legacy ATA resources */
    for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
	ch->r_io[i].res = ctlr->r_res1;
	ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
    }
    ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
    ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
    ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
    ata_default_registers(dev);

    /* set SATA resources */
    switch (ctlr->chip->cfg2) {
    case MV_50XX:
	ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
	ch->r_io[ATA_SSTATUS].offset =  0x00100 + ATA_MV_HOST_BASE(ch);
	ch->r_io[ATA_SERROR].res = ctlr->r_res1;
	ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
	ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
	ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
	break;
    case MV_60XX:
    case MV_6042:
    case MV_7042:
	ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
	ch->r_io[ATA_SSTATUS].offset =  0x02300 + ATA_MV_EDMA_BASE(ch);
	ch->r_io[ATA_SERROR].res = ctlr->r_res1;
	ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
	ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
	ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
	ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
	ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
	break;
    }

    ch->flags |= ATA_NO_SLAVE;
    ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
    ch->flags |= ATA_SATA;
    ata_generic_hw(dev);
    ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
    ch->hw.end_transaction = ata_marvell_edma_end_transaction;
    ch->hw.status = ata_marvell_edma_status;

    /* disable the EDMA machinery */
    ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
    DELAY(100000);       /* SOS should poll for disabled */

    /* set configuration to non-queued 128b read transfers stop on error */
    ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));

    /* request queue base high */
    ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);

    /* request queue in ptr */
    ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);

    /* request queue out ptr */
    ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);

    /* response queue base high */
    work += 1024;
    ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);

    /* response queue in ptr */
    ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);

    /* response queue out ptr */
    ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);

    /* clear SATA error register */
    ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));

    /* clear any outstanding error interrupts */
    ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);

    /* unmask all error interrupts */
    ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
    
    /* enable EDMA machinery */
    ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
    return 0;
}

static int
ata_marvell_edma_ch_detach(device_t dev)
{
    struct ata_channel *ch = device_get_softc(dev);

    if (ch->dma.work_tag && ch->dma.work_map)
	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
    ata_dmafini(dev);
    return (0);
}

static int
ata_marvell_edma_status(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
    int shift = (ch->unit << 1) + (ch->unit > 3);

    if (cause & (1 << shift)) {

	/* clear interrupt(s) */
	ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);

	/* do we have any PHY events ? */
	ata_sata_phy_check_events(dev, -1);
    }

    /* do we have any device action ? */
    return (cause & (2 << shift));
}

/* must be called with ATA channel locked and state_mtx held */
static int
ata_marvell_edma_begin_transaction(struct ata_request *request)
{
    struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
    struct ata_channel *ch = device_get_softc(request->parent);
    u_int32_t req_in;
    u_int8_t *bytep;
    int i;
    int error, slot;

    /* only DMA R/W goes through the EMDA machine */
    if (request->u.ata.command != ATA_READ_DMA &&
	request->u.ata.command != ATA_WRITE_DMA &&
	request->u.ata.command != ATA_READ_DMA48 &&
	request->u.ata.command != ATA_WRITE_DMA48) {

	/* disable the EDMA machinery */
	if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
	    ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
	return ata_begin_transaction(request);
    }

    /* check sanity, setup SG list and DMA engine */
    if ((error = ch->dma.load(request, NULL, NULL))) {
	device_printf(request->parent, "setting up DMA failed\n");
	request->result = error;
	return ATA_OP_FINISHED;
    }

    /* get next free request queue slot */
    req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
    slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
    bytep = (u_int8_t *)(ch->dma.work);
    bytep += (slot << 5);

    /* fill in this request */
    le32enc(bytep + 0 * sizeof(u_int32_t),
	request->dma->sg_bus & 0xffffffff);
    le32enc(bytep + 1 * sizeof(u_int32_t),
	(u_int64_t)request->dma->sg_bus >> 32);
    if (ctlr->chip->cfg2 != MV_6042 && ctlr->chip->cfg2 != MV_7042) {
	    le16enc(bytep + 4 * sizeof(u_int16_t),
		(request->flags & ATA_R_READ ? 0x01 : 0x00) | (request->tag << 1));

	    i = 10;
	    bytep[i++] = (request->u.ata.count >> 8) & 0xff;
	    bytep[i++] = 0x10 | ATA_COUNT;
	    bytep[i++] = request->u.ata.count & 0xff;
	    bytep[i++] = 0x10 | ATA_COUNT;

	    bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
	    bytep[i++] = 0x10 | ATA_SECTOR;
	    bytep[i++] = request->u.ata.lba & 0xff;
	    bytep[i++] = 0x10 | ATA_SECTOR;

	    bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
	    bytep[i++] = 0x10 | ATA_CYL_LSB;
	    bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
	    bytep[i++] = 0x10 | ATA_CYL_LSB;

	    bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
	    bytep[i++] = 0x10 | ATA_CYL_MSB;
	    bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
	    bytep[i++] = 0x10 | ATA_CYL_MSB;

	    bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
	    bytep[i++] = 0x10 | ATA_DRIVE;

	    bytep[i++] = request->u.ata.command;
	    bytep[i++] = 0x90 | ATA_COMMAND;
    } else {
	    le32enc(bytep + 2 * sizeof(u_int32_t),
		(request->flags & ATA_R_READ ? 0x01 : 0x00) | (request->tag << 1));

	    i = 16;
	    bytep[i++] = 0;
	    bytep[i++] = 0;
	    bytep[i++] = request->u.ata.command;
	    bytep[i++] = request->u.ata.feature & 0xff;

	    bytep[i++] = request->u.ata.lba & 0xff;
	    bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
	    bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
	    bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0x0f);

	    bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
	    bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
	    bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
	    bytep[i++] = (request->u.ata.feature >> 8) & 0xff;

	    bytep[i++] = request->u.ata.count & 0xff;
	    bytep[i++] = (request->u.ata.count >> 8) & 0xff;
	    bytep[i++] = 0;
	    bytep[i++] = 0;
    }

    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
	BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

    /* enable EDMA machinery if needed */
    if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
	ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
	while (!(ATA_INL(ctlr->r_res1,
			 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
	    DELAY(10);
    }

    /* tell EDMA it has a new request */
    slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
    req_in &= 0xfffffc00;
    req_in += (slot << 5);
    ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
   
    return ATA_OP_CONTINUES;
}

/* must be called with ATA channel locked and state_mtx held */
static int
ata_marvell_edma_end_transaction(struct ata_request *request)
{
    struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
    struct ata_channel *ch = device_get_softc(request->parent);
    int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
    u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
    int res;

    /* EDMA interrupt */
    if ((icr & (0x0001 << (ch->unit & 3)))) {
	struct ata_marvell_response *response;
	u_int32_t rsp_in, rsp_out;
	int slot;

	/* stop timeout */
	callout_stop(&request->callout);

	/* get response ptr's */
	rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
	rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
	slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
	rsp_out &= 0xffffff00;
	rsp_out += (slot << 3);
	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
	response = (struct ata_marvell_response *)
		   (ch->dma.work + 1024 + (slot << 3));

	/* record status for this request */
	request->status = response->dev_status;
	request->error = 0; 

	/* ack response */
	ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);

	/* update progress */
	if (!(request->status & ATA_S_ERROR) &&
	    !(request->flags & ATA_R_TIMEOUT))
	    request->donecount = request->bytecount;

	/* unload SG list */
	ch->dma.unload(request);

	res = ATA_OP_FINISHED;
    }

    /* legacy ATA interrupt */
    else {
	res = ata_end_transaction(request);
    }

    /* ack interrupt */
    ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
    return res;
}

static void
ata_marvell_edma_reset(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);

    /* disable the EDMA machinery */
    ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
    while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
	DELAY(10);

    /* clear SATA error register */
    ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));

    /* clear any outstanding error interrupts */
    ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);

    /* unmask all error interrupts */
    ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);

    /* enable channel and test for devices */
    if (ata_sata_phy_reset(dev, -1, 1))
	ata_generic_reset(dev);
    else
	ch->devices = 0;

    /* enable EDMA machinery */
    ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
}

static void
ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
			   int error)
{
    struct ata_dmasetprd_args *args = xsc;
    struct ata_marvell_dma_prdentry *prd = args->dmatab;
    int i;

    if ((args->error = error))
	return;

    for (i = 0; i < nsegs; i++) {
	prd[i].addrlo = htole32(segs[i].ds_addr);
	prd[i].count = htole32(segs[i].ds_len);
	prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
	prd[i].reserved = 0;
    }
    prd[i - 1].count |= htole32(ATA_DMA_EOT);
    KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
    args->nsegs = nsegs;
}

static void
ata_marvell_edma_dmainit(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);

    /* note start and stop are not used here */
    ch->dma.setprd = ata_marvell_edma_dmasetprd;
	
    /* if 64bit support present adjust max address used */
    if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
	ch->dma.max_address = BUS_SPACE_MAXADDR;

    /* chip does not reliably do 64K DMA transfers */
    if (ctlr->chip->cfg2 == MV_50XX || ctlr->chip->cfg2 == MV_60XX)
	ch->dma.max_iosize = 64 * DEV_BSIZE;
    ata_dmainit(dev);
}

ATA_DECLARE_DRIVER(ata_marvell);




#define NV4             0x01
#define NVQ             0x02
#define NVAHCI          0x04
#define NVNOFORCE       0x08

static int force_ahci = 1;
TUNABLE_INT("hw.ahci.force", &force_ahci);

/*
 * nVidia chipset support functions
 */

     { ATA_NFORCE_MCP79_AA, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
     { ATA_NFORCE_MCP79_AB, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
     { ATA_NFORCE_MCP89_A0, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
     { ATA_NFORCE_MCP89_A1, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
     { ATA_NFORCE_MCP89_A2, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
     { ATA_NFORCE_MCP89_A3, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
     { ATA_NFORCE_MCP89_A4, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },

    if (!(ctlr->chip = ata_match_chip(dev, ids)))
	return ENXIO;

    if ((ctlr->chip->cfg1 & NVAHCI) &&
	    pci_get_subclass(dev) != PCIS_STORAGE_IDE)
	return (ENXIO);

    ata_set_desc(dev);
    ctlr->chipinit = ata_nvidia_chipinit;
	((force_ahci == 1 && (ctlr->chip->cfg1 & NVNOFORCE) == 0) ||
	 pci_get_subclass(dev) != PCIS_STORAGE_IDE))
	ctlr->chipinit = ata_ahci_chipinit;
    else
	ctlr->chipinit = ata_nvidia_chipinit;
    return (BUS_PROBE_LOW_PRIORITY);
}


}

ATA_DECLARE_DRIVER(ata_nvidia);
MODULE_DEPEND(ata_nvidia, ata_ahci, 1, 1, 1);




static int ata_sii_status(device_t dev);
static void ata_sii_reset(device_t dev);
static int ata_sii_setmode(device_t dev, int target, int mode);
static int ata_siiprb_ch_attach(device_t dev);
static int ata_siiprb_ch_detach(device_t dev);
static int ata_siiprb_status(device_t dev);
static int ata_siiprb_begin_transaction(struct ata_request *request);
static int ata_siiprb_end_transaction(struct ata_request *request);
static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result);
static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result);
static u_int32_t ata_siiprb_softreset(device_t dev, int port);
static void ata_siiprb_reset(device_t dev);
static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
static void ata_siiprb_dmainit(device_t dev);

/* misc defines */
#define SII_MEMIO	1
#define SII_PRBIO	2
#define SII_INTR	0x01
#define SII_SETCLK	0x02
#define SII_BUG		0x04

     { ATA_SII3512,   0x00, SII_MEMIO, SII_BUG,    ATA_SA150, "3512" },
     { ATA_SII3112,   0x00, SII_MEMIO, SII_BUG,    ATA_SA150, "3112" },
     { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG,    ATA_SA150, "3112" },
     { ATA_SII3124,   0x00, SII_PRBIO, SII_4CH,    ATA_SA300, "3124" },
     { ATA_SII3132,   0x00, SII_PRBIO, 0,          ATA_SA300, "3132" },
     { ATA_SII3132_1, 0x00, SII_PRBIO, 0,          ATA_SA300, "3132" },
     { ATA_SII3132_2, 0x00, SII_PRBIO, 0,          ATA_SA300, "3132" },
     { ATA_SII0680,   0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" },
     { ATA_CMD649,    0x00, 0,         SII_INTR,   ATA_UDMA5, "(CMD) 649" },
     { ATA_CMD648,    0x00, 0,         SII_INTR,   ATA_UDMA4, "(CMD) 648" },

	return ENXIO;

    switch (ctlr->chip->cfg1) {
    case SII_PRBIO:
	ctlr->r_type1 = SYS_RES_MEMORY;
	ctlr->r_rid1 = PCIR_BAR(0);
	if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
						    &ctlr->r_rid1, RF_ACTIVE)))
	    return ENXIO;

	ctlr->r_rid2 = PCIR_BAR(2);
	ctlr->r_type2 = SYS_RES_MEMORY;
	if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
						    &ctlr->r_rid2, RF_ACTIVE))){
	    bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
	    return ENXIO;
	}
#ifdef __sparc64__
	if (!bus_space_map(rman_get_bustag(ctlr->r_res2),
	    rman_get_bushandle(ctlr->r_res2), rman_get_size(ctlr->r_res2),
	    BUS_SPACE_MAP_LINEAR, NULL)) {
	    	bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,
		    ctlr->r_res1);
		bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2,
		    ctlr->r_res2);
		return (ENXIO);
	}
#endif
	ctlr->ch_attach = ata_siiprb_ch_attach;
	ctlr->ch_detach = ata_siiprb_ch_detach;
	ctlr->reset = ata_siiprb_reset;
	ctlr->setmode = ata_sata_setmode;
	ctlr->getrev = ata_sata_getrev;
	ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;

	/* reset controller */
	ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
	DELAY(10000);
	ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
	break;

    case SII_MEMIO:
	ctlr->r_type2 = SYS_RES_MEMORY;
	ctlr->r_rid2 = PCIR_BAR(5);

	return (mode);
}

struct ata_siiprb_dma_prdentry {
    u_int64_t addr;
    u_int32_t count;
    u_int32_t control;
} __packed;

#define ATA_SIIPRB_DMA_ENTRIES		129
struct ata_siiprb_ata_command {
    struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
} __packed;

struct ata_siiprb_atapi_command {
    u_int8_t ccb[16];
    struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
} __packed;

struct ata_siiprb_command {
    u_int16_t control;
    u_int16_t protocol_override;
    u_int32_t transfer_count;
    u_int8_t fis[24];
    union {
	struct ata_siiprb_ata_command ata;
	struct ata_siiprb_atapi_command atapi;
    } u;
} __packed;

static int
ata_siiprb_ch_attach(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    int offset = ch->unit * 0x2000;

    ata_siiprb_dmainit(dev);

    /* set the SATA resources */
    ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
    ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
    ch->r_io[ATA_SERROR].res = ctlr->r_res2;
    ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
    ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
    ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
    ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
    ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
   
    ch->hw.status = ata_siiprb_status;
    ch->hw.begin_transaction = ata_siiprb_begin_transaction;
    ch->hw.end_transaction = ata_siiprb_end_transaction;
    ch->hw.command = NULL;	/* not used here */
    ch->hw.softreset = ata_siiprb_softreset;
    ch->hw.pm_read = ata_siiprb_pm_read;
    ch->hw.pm_write = ata_siiprb_pm_write;
    ch->flags |= ATA_NO_SLAVE;
    ch->flags |= ATA_SATA;
    return 0;
}

static int
ata_siiprb_ch_detach(device_t dev)
{
    struct ata_channel *ch = device_get_softc(dev);

    if (ch->dma.work_tag && ch->dma.work_map)
	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
	    BUS_DMASYNC_POSTWRITE);
    ata_dmafini(dev);
    return 0;
}

static int
ata_siiprb_status(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
    int offset = ch->unit * 0x2000;

    if (action & (1 << ch->unit)) {
	u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);

	/* do we have any PHY events ? */
	ata_sata_phy_check_events(dev, -1);

	/* clear interrupt(s) */
	ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);

	/* do we have any device action ? */
	return (istatus & 0x00000003);
    }
    return 0;
}

static int
ata_siiprb_begin_transaction(struct ata_request *request)
{
    struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
    struct ata_channel *ch = device_get_softc(request->parent);
    struct ata_siiprb_command *prb;
    struct ata_siiprb_dma_prdentry *prd;
    int offset = ch->unit * 0x2000;
    u_int64_t prb_bus;

    /* SOS XXX */
    if (request->u.ata.command == ATA_DEVICE_RESET) {
        request->result = 0;
        return ATA_OP_FINISHED;
    }

    /* get a piece of the workspace for this request */
    prb = (struct ata_siiprb_command *)ch->dma.work;

    /* clear the prb structure */
    bzero(prb, sizeof(struct ata_siiprb_command));

    /* setup the FIS for this request */
    if (!ata_request2fis_h2d(request, &prb->fis[0])) {
        device_printf(request->parent, "setting up SATA FIS failed\n");
        request->result = EIO;
        return ATA_OP_FINISHED;
    }

    /* setup transfer type */
    if (request->flags & ATA_R_ATAPI) {
	bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
	if (request->flags & ATA_R_ATAPI16)
	    ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
	else
	    ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
	if (request->flags & ATA_R_READ)
	    prb->control = htole16(0x0010);
	if (request->flags & ATA_R_WRITE)
	    prb->control = htole16(0x0020);
	prd = &prb->u.atapi.prd[0];
    }
    else
	prd = &prb->u.ata.prd[0];

    /* if request moves data setup and load SG list */
    if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
	if (ch->dma.load(request, prd, NULL)) {
	    device_printf(request->parent, "setting up DMA failed\n");
	    request->result = EIO;
	    return ATA_OP_FINISHED;
	}
    }

    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);

    /* activate the prb */
    prb_bus = ch->dma.work_bus;
    ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
    ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32);

    /* start the timeout */
    callout_reset(&request->callout, request->timeout * hz,
                  (timeout_t*)ata_timeout, request);
    return ATA_OP_CONTINUES;
}

static int
ata_siiprb_end_transaction(struct ata_request *request)
{
    struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
    struct ata_channel *ch = device_get_softc(request->parent);
    struct ata_siiprb_command *prb;
    int offset = ch->unit * 0x2000;
    int error, timeout;

    /* kill the timeout */
    callout_stop(&request->callout);

    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);

    prb = (struct ata_siiprb_command *)
	((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);

    /* any controller errors flagged ? */
    if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
	if (bootverbose)
	    printf("ata_siiprb_end_transaction %s error=%08x\n",
		   ata_cmd2str(request), error);

	/* if device error status get details */
	if (error == 1 || error == 2) {
	    request->status = prb->fis[2];
	    if (request->status & ATA_S_ERROR)
		request->error = prb->fis[3];
	}

 	/* SOS XXX handle other controller errors here */

	/* initialize port */
	ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);

	/* poll for port ready */
	for (timeout = 0; timeout < 1000; timeout++) {
	    DELAY(1000);
            if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
        	break;
	}
	if (bootverbose) {
	    if (timeout >= 1000)
		device_printf(ch->dev, "port initialize timeout\n");
	    else
		device_printf(ch->dev, "port initialize time=%dms\n", timeout);
	}
    }

    /* Read back registers to the request struct. */
    if ((request->flags & ATA_R_ATAPI) == 0 &&
	((request->status & ATA_S_ERROR) ||
	 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT)))) {
	request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8);
	request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) |
			     ((u_int64_t)prb->fis[6] << 16);
	if (request->flags & ATA_R_48BIT)
	    request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) |
				  ((u_int64_t)prb->fis[9] << 32) |
				  ((u_int64_t)prb->fis[10] << 40);
	else
	    request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24);
    }

    /* update progress */
    if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
	if (request->flags & ATA_R_READ)
	    request->donecount = le32toh(prb->transfer_count);
	else
	    request->donecount = request->bytecount;
    }

    /* release SG list etc */
    ch->dma.unload(request);

    return ATA_OP_FINISHED;
}

static int
ata_siiprb_issue_cmd(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    u_int64_t prb_bus = ch->dma.work_bus;
    u_int32_t status;
    int offset = ch->unit * 0x2000;
    int timeout;

    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);

    /* issue command to chip */
    ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
    ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32);

    /* poll for command finished */
    for (timeout = 0; timeout < 10000; timeout++) {
        DELAY(1000);
        if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
            break;
    }

    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);

    // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000);
    ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff);

    if (timeout >= 1000)
	return EIO;

    if (bootverbose)
	device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n",
		      timeout, status);
    return 0;
}

static int
ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
    int offset = ch->unit * 0x2000;

    if (port < 0) {
	*result = ATA_IDX_INL(ch, reg);
	return (0);
    }
    if (port < ATA_PM) {
	switch (reg) {
	case ATA_SSTATUS:
	    reg = 0;
	    break;
	case ATA_SERROR:
	    reg = 1;
	    break;
	case ATA_SCONTROL:
	    reg = 2;
	    break;
	default:
	    return (EINVAL);
	}
    }
    bzero(prb, sizeof(struct ata_siiprb_command));
    prb->fis[0] = 0x27;	/* host to device */
    prb->fis[1] = 0x8f;	/* command FIS to PM port */
    prb->fis[2] = ATA_READ_PM;
    prb->fis[3] = reg;
    prb->fis[7] = port;
    if (ata_siiprb_issue_cmd(dev)) {
	device_printf(dev, "error reading PM port\n");
	return EIO;
    }
    prb = (struct ata_siiprb_command *)
	((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
    *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
    return 0;
}

static int
ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
    int offset = ch->unit * 0x2000;

    if (port < 0) {
	ATA_IDX_OUTL(ch, reg, value);
	return (0);
    }
    if (port < ATA_PM) {
	switch (reg) {
	case ATA_SSTATUS:
	    reg = 0;
	    break;
	case ATA_SERROR:
	    reg = 1;
	    break;
	case ATA_SCONTROL:
	    reg = 2;
	    break;
	default:
	    return (EINVAL);
	}
    }
    bzero(prb, sizeof(struct ata_siiprb_command));
    prb->fis[0] = 0x27;	/* host to device */
    prb->fis[1] = 0x8f;	/* command FIS to PM port */
    prb->fis[2] = ATA_WRITE_PM;
    prb->fis[3] = reg;
    prb->fis[7] = port;
    prb->fis[12] = value & 0xff;
    prb->fis[4] = (value >> 8) & 0xff;
    prb->fis[5] = (value >> 16) & 0xff;
    prb->fis[6] = (value >> 24) & 0xff;
    if (ata_siiprb_issue_cmd(dev)) {
	device_printf(dev, "error writing PM port\n");
	return ATA_E_ABORT;
    }
    prb = (struct ata_siiprb_command *)
	((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
    return prb->fis[3];
}

static u_int32_t
ata_siiprb_softreset(device_t dev, int port)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
    u_int32_t signature;
    int offset = ch->unit * 0x2000;

    /* setup the workspace for a soft reset command */
    bzero(prb, sizeof(struct ata_siiprb_command));
    prb->control = htole16(0x0080);
    prb->fis[1] = port & 0x0f;

    /* issue soft reset */
    if (ata_siiprb_issue_cmd(dev))
	return -1;

    ata_udelay(150000);

    /* get possible signature */
    prb = (struct ata_siiprb_command *)
	((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
    signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);

    /* clear error bits/interrupt */
    ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);

    return signature;
}

static void
ata_siiprb_reset(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
    struct ata_channel *ch = device_get_softc(dev);
    int offset = ch->unit * 0x2000;
    u_int32_t status, signature;
    int timeout;

    /* disable interrupts */
    ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff);

    /* reset channel HW */
    ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
    DELAY(1000);
    ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
    DELAY(10000);

    /* poll for channel ready */
    for (timeout = 0; timeout < 1000; timeout++) {
        if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
            break;
        DELAY(1000);
    }

    if (bootverbose) {
	if (timeout >= 1000)
	    device_printf(dev, "channel HW reset timeout\n");
	else
	    device_printf(dev, "channel HW reset time=%dms\n", timeout);
    }

    /* reset phy */
    if (!ata_sata_phy_reset(dev, -1, 1)) {
	if (bootverbose)
	    device_printf(dev, "phy reset found no device\n");
	ch->devices = 0;
	goto finish;
    }

    /* issue soft reset */
    signature = ata_siiprb_softreset(dev, ATA_PM);
    if (bootverbose)
	device_printf(dev, "SIGNATURE=%08x\n", signature);

    /* figure out whats there */
    switch (signature >> 16) {
    case 0x0000:
	ch->devices = ATA_ATA_MASTER;
	break;
    case 0x9669:
	ch->devices = ATA_PORTMULTIPLIER;
	ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */
	//SOS XXX need to clear all PM status and interrupts!!!!
	ata_pm_identify(dev);
	break;
    case 0xeb14:
	ch->devices = ATA_ATAPI_MASTER;
	break;
    default:
	ch->devices = 0;
    }
    if (bootverbose)
        device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices);

finish:
    /* clear interrupt(s) */
    ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);

    /* require explicit interrupt ack */
    ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);

    /* 64bit mode */
    ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);

    /* enable interrupts wanted */
    ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
}

static void
ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
{
    struct ata_dmasetprd_args *args = xsc;
    struct ata_siiprb_dma_prdentry *prd = args->dmatab;
    int i;

    if ((args->error = error))
	return;

    for (i = 0; i < nsegs; i++) {
	prd[i].addr = htole64(segs[i].ds_addr);
	prd[i].count = htole32(segs[i].ds_len);
    }
    prd[i - 1].control = htole32(ATA_DMA_EOT);
    KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n"));
    args->nsegs = nsegs;
}

static void
ata_siiprb_dmainit(device_t dev)
{
    struct ata_channel *ch = device_get_softc(dev);

    /* note start and stop are not used here */
    ch->dma.setprd = ata_siiprb_dmasetprd;
    ch->dma.max_address = BUS_SPACE_MAXADDR;
    ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE;
    ata_dmainit(dev);
}

ATA_DECLARE_DRIVER(ata_sii);




#define VIACLK          0x01
#define VIABUG          0x02
#define VIABAR          0x04
#define VIAAHCI         0x08
#define VIASATA         0x10

/*

     { ATA_VIA8237S,  0x00, 7,      0x00,    ATA_SA150, "8237S" },
     { ATA_VIA8237_5372, 0x00, 7,   0x00,    ATA_SA300, "8237" },
     { ATA_VIA8237_7372, 0x00, 7,   0x00,    ATA_SA300, "8237" },
     { ATA_VIA8251,   0x00, 0,      VIAAHCI, ATA_SA300, "8251" },
     { 0, 0, 0, 0, 0, 0 }};

    if (pci_get_vendor(dev) != ATA_VIA_ID)

    if (ata_setup_interrupt(dev, ata_generic_intr))
	return ENXIO;

    /* AHCI SATA */
    if (ctlr->chip->cfg2 & VIAAHCI) {
	if (ata_ahci_chipinit(dev) != ENXIO)
	    return (0);
    }
    /* 2 SATA with "SATA registers" at PCI config space + PATA on secondary */
    if (ctlr->chip->cfg2 & VIASATA) {
	ctlr->ch_attach = ata_via_sata_ch_attach;

}

ATA_DECLARE_DRIVER(ata_via);
MODULE_DEPEND(ata_via, ata_ahci, 1, 1, 1);

Lines 1-5 Link Here

(-)sys/modules/ata/atapci/chipsets/Makefile (-1 / +1 lines)
1	# $FreeBSD$	1	# $FreeBSD$
2		2
3	SUBDIR += ataacard ataacerlabs ataadaptec ataahci ataamd ataati atacenatek atacypress atacyrix atahighpoint ataintel ataite atajmicron atamarvell atamicron atanational atanetcell atanvidia atapromise ataserverworks atasiliconimage atasis atavia	3	SUBDIR += ataacard ataacerlabs ataamd ataati atacenatek atacypress atacyrix atahighpoint ataintel ataite atajmicron atamarvell atamicron atanational atanetcell atanvidia atapromise ataserverworks atasiliconimage atasis atavia
4		4
5	.include <bsd.subdir.mk>	5	.include <bsd.subdir.mk>

Lines 1-9 Link Here

(-)sys/modules/ata/atapci/chipsets/ataadaptec/Makefile (-9 lines)
1	# $FreeBSD$
2
3	.PATH: ${.CURDIR}/../../../../../dev/ata/chipsets
4
5	KMOD= ataadaptec
6	SRCS= ata-adaptec.c
7	SRCS+= ata_if.h bus_if.h device_if.h pci_if.h
8
9	.include <bsd.kmod.mk>

Lines 1-9 Link Here

(-)sys/modules/ata/atapci/chipsets/ataahci/Makefile (-9 lines)
1	# $FreeBSD$
2
3	.PATH: ${.CURDIR}/../../../../../dev/ata/chipsets
4
5	KMOD= ataahci
6	SRCS= ata-ahci.c
7	SRCS+= ata_if.h bus_if.h device_if.h pci_if.h
8
9	.include <bsd.kmod.mk>

Return to bug 199495

Lines 138-149 device for localization and status reporting purpo Link Here

(-)share/man/man4/ahci.4 (-6 lines)
138	Supporting AHCI controllers may transmit that information to the backplane	138	Supporting AHCI controllers may transmit that information to the backplane
139	controllers via SGPIO interface. Backplane controllers interpret received	139	controllers via SGPIO interface. Backplane controllers interpret received
140	statuses in some way (IBPI standard) to report them using present indicators.	140	statuses in some way (IBPI standard) to report them using present indicators.
141	.Pp
142	AHCI hardware is also supported by ataahci driver from
143	.Xr ata 4
144	subsystem.
145	If both drivers are loaded at the same time, this one will be
146	given precedence as the more functional of the two.
147	.Sh HARDWARE	141	.Sh HARDWARE
148	The	142	The
149	.Nm	143	.Nm

Lines 24-30 Link Here

(-)share/man/man4/ata.4 (-26 / +8 lines)
24	.\"	24	.\"
25	.\" $FreeBSD$	25	.\" $FreeBSD$
26	.\"	26	.\"
27	.Dd October 3, 2012	27	.Dd March 23, 2015
28	.Dt ATA 4	28	.Dt ATA 4
29	.Os	29	.Os
30	.Sh NAME	30	.Sh NAME
Lines 50-57 atapci_load="YES" Link Here
50		50
51	ataacard_load="YES"	51	ataacard_load="YES"
52	ataacerlabs_load="YES"	52	ataacerlabs_load="YES"
53	ataadaptec_load="YES"
54	ataahci_load="YES"
55	ataamd_load="YES"	53	ataamd_load="YES"
56	ataati_load="YES"	54	ataati_load="YES"
57	atacenatek_load="YES"	55	atacenatek_load="YES"
Lines 76-91 atavia_load="YES" Link Here
76	The first line is for the common hardware independent code, and is a	74	The first line is for the common hardware independent code, and is a
77	prerequisite for the other modules.	75	prerequisite for the other modules.
78	The next three lines are generic bus-specific drivers.	76	The next three lines are generic bus-specific drivers.
79	Of the rest, ataahci is the AHCI driver.	77	The rest are vendor-specific PCI drivers.
80	The others are vendor-specific PCI drivers.
81	.Pp	78	.Pp
82	The following tunables are settable from the	79	The following tunables are settable from the
83	.Xr loader 8 :	80	.Xr loader 8 :
84	.Bl -ohang	81	.Bl -ohang
85	.It Va hw.ahci.force
86	set to nonzero value for forcing drivers to attach to some known AHCI-capable
87	chips even if they are configured for legacy IDE emulation (the default is 1,
88	force the attach).
89	.It Va hw.ata.ata_dma_check_80pin	82	.It Va hw.ata.ata_dma_check_80pin
90	set to 0 to disable the 80pin cable check (the default is 1, check the cable).	83	set to 0 to disable the 80pin cable check (the default is 1, check the cable).
91	.It Va hint.atapci.X.msi	84	.It Va hint.atapci.X.msi
Lines 106-118 Interface Power Management is disabled. Link Here
106	This is the default value.	99	This is the default value.
107	.It 1	100	.It 1
108	The device is allowed to initiate a PM state change; the host is passive.	101	The device is allowed to initiate a PM state change; the host is passive.
109	.It 2
110	The host initiates a PARTIAL PM state transition every time a port becomes idle.
111	.It 3
112	host initiates SLUMBER PM state transition every time port becomes idle.
113	.El
114	.Pp
115	Modes 2 and 3 are only supported for AHCI.
116	.It Va hint.ata. Ns Ar X Ns Va .dev Ns Ar X Ns Va .sata_rev	102	.It Va hint.ata. Ns Ar X Ns Va .dev Ns Ar X Ns Va .sata_rev
117	limits the initial SATA revision (speed) for the specified device	103	limits the initial SATA revision (speed) for the specified device
118	on the specified channel.	104	on the specified channel.
Lines 198-205 IT8211F, IT8212F, IT8213F. Link Here
198	.It JMicron:	184	.It JMicron:
199	JMB360, JMB361, JMB363, JMB365, JMB366, JMB368.	185	JMB360, JMB361, JMB363, JMB365, JMB366, JMB368.
200	.It Marvell	186	.It Marvell
201	88SX5040, 88SX5041, 88SX5080, 88SX5081, 88SX6041, 88SX6042, 88SX6081, 88SE6101,	187	88SE6101, 88SE6102, 88SE6111, 88SE6121, 88SE6141, 88SE6145.
202	88SE6102, 88SE6111, 88SE6121, 88SE6141, 88SE6145, 88SX7042.
203	.It National:	188	.It National:
204	SC1100.	189	SC1100.
205	.It NetCell:	190	.It NetCell:
Lines 216-222 PDC40718, PDC40719. Link Here
216	.It ServerWorks:	201	.It ServerWorks:
217	HT1000, ROSB4, CSB5, CSB6, K2, Frodo4, Frodo8.	202	HT1000, ROSB4, CSB5, CSB6, K2, Frodo4, Frodo8.
218	.It Silicon Image:	203	.It Silicon Image:
219	SiI0680, SiI3112, SiI3114, SiI3124, SiI3132, SiI3512.	204	SiI0680, SiI3112, SiI3114, SiI3512.
220	.It SiS:	205	.It SiS:
221	SIS180, SIS181, SIS182, SIS5513, SIS530, SIS540, SIS550, SIS620, SIS630,	206	SIS180, SIS181, SIS182, SIS5513, SIS530, SIS540, SIS550, SIS620, SIS630,
222	SIS630S, SIS633, SIS635, SIS730, SIS733, SIS735, SIS745, SIS961, SIS962,	207	SIS630S, SIS633, SIS635, SIS730, SIS733, SIS735, SIS745, SIS961, SIS962,
Lines 227-239 VT82C686A, VT82C686B, VT8231, VT8233, VT8233A, VT8 Link Here
227	VT8237A, VT8237S, VT8251, CX700, VX800, VX855, VX900.	212	VT8237A, VT8237S, VT8251, CX700, VX800, VX855, VX900.
228	.El	213	.El
229	.Pp	214	.Pp
230	Some of above chips are also supported by the more featured	215	Some of above chips can be configured for AHCI mode.
231	.Xr ahci 4 ,	216	In such case they are supported by
232	.Xr mvs 4 ,	217	.Xr ahci 4
233	and	218	driver instead.
234	.Xr siis 4
235	drivers.
236	If both drivers are loaded at the same time, those will have precedence.
237	.Pp	219	.Pp
238	Unknown ATA chipsets are supported in PIO modes, and if the standard	220	Unknown ATA chipsets are supported in PIO modes, and if the standard
239	busmaster DMA registers are present and contain valid setup, DMA is	221	busmaster DMA registers are present and contain valid setup, DMA is

Lines 24-30 Link Here

(-)share/man/man4/mvs.4 (-8 / +1 lines)
24	.\"	24	.\"
25	.\" $FreeBSD$	25	.\" $FreeBSD$
26	.\"	26	.\"
27	.Dd March 3, 2013	27	.Dd March 23, 2015
28	.Dt MVS 4	28	.Dt MVS 4
29	.Os	29	.Os
30	.Sh NAME	30	.Sh NAME
Lines 109-121 Port Multipliers (including FIS-based switching, w Link Here
109	hardware command queues (up to 31 command per port),	109	hardware command queues (up to 31 command per port),
110	Native Command Queuing, SATA interface Power Management, device hot-plug	110	Native Command Queuing, SATA interface Power Management, device hot-plug
111	and Message Signaled Interrupts.	111	and Message Signaled Interrupts.
112	.Pp
113	The same hardware is also supported by the atamarvell and ataadaptec
114	drivers from the
115	.Xr ata 4
116	subsystem.
117	If both drivers are loaded at the same time, this one will be
118	given precedence as the more functional of the two.
119	.Sh HARDWARE	112	.Sh HARDWARE
120	The	113	The
121	.Nm	114	.Nm

Lines 24-30 Link Here

(-)share/man/man4/siis.4 (-7 / +1 lines)
24	.\"	24	.\"
25	.\" $FreeBSD$	25	.\" $FreeBSD$
26	.\"	26	.\"
27	.Dd April 8, 2011	27	.Dd March 23, 2015
28	.Dt SIIS 4	28	.Dt SIIS 4
29	.Os	29	.Os
30	.Sh NAME	30	.Sh NAME
Lines 98-109 The activity LEDs of the adapters supported by the Link Here
98	driver can be controlled via the	98	driver can be controlled via the
99	.Xr led 4	99	.Xr led 4
100	API for localization or status reporting purposes.	100	API for localization or status reporting purposes.
101	.Pp
102	Same hardware is also supported by the atasiliconimage driver from
103	.Xr ata 4
104	subsystem.
105	If both drivers are loaded at the same time, this one will be
106	given precedence as the more functional of the two.
107	.Sh HARDWARE	101	.Sh HARDWARE
108	The	102	The
109	.Nm	103	.Nm

Lines 680-691 dev/ata/ata-card.c optional ata pccard \| atapccar Link Here

(-)sys/conf/files (-5 / +1 lines)
680	dev/ata/ata-cbus.c optional ata pc98 \| atapc98	680	dev/ata/ata-cbus.c optional ata pc98 \| atapc98
681	dev/ata/ata-isa.c optional ata isa \| ataisa	681	dev/ata/ata-isa.c optional ata isa \| ataisa
682	dev/ata/ata-pci.c optional ata pci \| atapci	682	dev/ata/ata-pci.c optional ata pci \| atapci
683	dev/ata/chipsets/ata-ahci.c optional ata pci \| ataahci \| ataacerlabs \| \
684	ataati \| ataintel \| atajmicron \| \
685	atavia \| atanvidia
686	dev/ata/chipsets/ata-acard.c optional ata pci \| ataacard	683	dev/ata/chipsets/ata-acard.c optional ata pci \| ataacard
687	dev/ata/chipsets/ata-acerlabs.c optional ata pci \| ataacerlabs	684	dev/ata/chipsets/ata-acerlabs.c optional ata pci \| ataacerlabs
688	dev/ata/chipsets/ata-adaptec.c optional ata pci \| ataadaptec
689	dev/ata/chipsets/ata-amd.c optional ata pci \| ataamd	685	dev/ata/chipsets/ata-amd.c optional ata pci \| ataamd
690	dev/ata/chipsets/ata-ati.c optional ata pci \| ataati	686	dev/ata/chipsets/ata-ati.c optional ata pci \| ataati
691	dev/ata/chipsets/ata-cenatek.c optional ata pci \| atacenatek	687	dev/ata/chipsets/ata-cenatek.c optional ata pci \| atacenatek
Lines 695-701 dev/ata/chipsets/ata-highpoint.c optional ata pci Link Here
695	dev/ata/chipsets/ata-intel.c optional ata pci \| ataintel	691	dev/ata/chipsets/ata-intel.c optional ata pci \| ataintel
696	dev/ata/chipsets/ata-ite.c optional ata pci \| ataite	692	dev/ata/chipsets/ata-ite.c optional ata pci \| ataite
697	dev/ata/chipsets/ata-jmicron.c optional ata pci \| atajmicron	693	dev/ata/chipsets/ata-jmicron.c optional ata pci \| atajmicron
698	dev/ata/chipsets/ata-marvell.c optional ata pci \| atamarvell \| ataadaptec	694	dev/ata/chipsets/ata-marvell.c optional ata pci \| atamarvell
699	dev/ata/chipsets/ata-micron.c optional ata pci \| atamicron	695	dev/ata/chipsets/ata-micron.c optional ata pci \| atamicron
700	dev/ata/chipsets/ata-national.c optional ata pci \| atanational	696	dev/ata/chipsets/ata-national.c optional ata pci \| atanational
701	dev/ata/chipsets/ata-netcell.c optional ata pci \| atanetcell	697	dev/ata/chipsets/ata-netcell.c optional ata pci \| atanetcell

Lines 150-288 Link Here

(-)sys/dev/ata/ata-all.h (-133 lines)
150		150
151	#define ATA_SACTIVE 16	151	#define ATA_SACTIVE 16
152		152
153	/* SATA AHCI v1.0 register defines */
154	#define ATA_AHCI_CAP 0x00
155	#define ATA_AHCI_CAP_NPMASK 0x0000001f
156	#define ATA_AHCI_CAP_SXS 0x00000020
157	#define ATA_AHCI_CAP_EMS 0x00000040
158	#define ATA_AHCI_CAP_CCCS 0x00000080
159	#define ATA_AHCI_CAP_NCS 0x00001F00
160	#define ATA_AHCI_CAP_NCS_SHIFT 8
161	#define ATA_AHCI_CAP_PSC 0x00002000
162	#define ATA_AHCI_CAP_SSC 0x00004000
163	#define ATA_AHCI_CAP_PMD 0x00008000
164	#define ATA_AHCI_CAP_FBSS 0x00010000
165	#define ATA_AHCI_CAP_SPM 0x00020000
166	#define ATA_AHCI_CAP_SAM 0x00080000
167	#define ATA_AHCI_CAP_ISS 0x00F00000
168	#define ATA_AHCI_CAP_ISS_SHIFT 20
169	#define ATA_AHCI_CAP_SCLO 0x01000000
170	#define ATA_AHCI_CAP_SAL 0x02000000
171	#define ATA_AHCI_CAP_SALP 0x04000000
172	#define ATA_AHCI_CAP_SSS 0x08000000
173	#define ATA_AHCI_CAP_SMPS 0x10000000
174	#define ATA_AHCI_CAP_SSNTF 0x20000000
175	#define ATA_AHCI_CAP_SNCQ 0x40000000
176	#define ATA_AHCI_CAP_64BIT 0x80000000
177
178	#define ATA_AHCI_GHC 0x04
179	#define ATA_AHCI_GHC_AE 0x80000000
180	#define ATA_AHCI_GHC_IE 0x00000002
181	#define ATA_AHCI_GHC_HR 0x00000001
182
183	#define ATA_AHCI_IS 0x08
184	#define ATA_AHCI_PI 0x0c
185	#define ATA_AHCI_VS 0x10
186
187	#define ATA_AHCI_OFFSET 0x80
188
189	#define ATA_AHCI_P_CLB 0x100
190	#define ATA_AHCI_P_CLBU 0x104
191	#define ATA_AHCI_P_FB 0x108
192	#define ATA_AHCI_P_FBU 0x10c
193	#define ATA_AHCI_P_IS 0x110
194	#define ATA_AHCI_P_IE 0x114
195	#define ATA_AHCI_P_IX_DHR 0x00000001
196	#define ATA_AHCI_P_IX_PS 0x00000002
197	#define ATA_AHCI_P_IX_DS 0x00000004
198	#define ATA_AHCI_P_IX_SDB 0x00000008
199	#define ATA_AHCI_P_IX_UF 0x00000010
200	#define ATA_AHCI_P_IX_DP 0x00000020
201	#define ATA_AHCI_P_IX_PC 0x00000040
202	#define ATA_AHCI_P_IX_DI 0x00000080
203
204	#define ATA_AHCI_P_IX_PRC 0x00400000
205	#define ATA_AHCI_P_IX_IPM 0x00800000
206	#define ATA_AHCI_P_IX_OF 0x01000000
207	#define ATA_AHCI_P_IX_INF 0x04000000
208	#define ATA_AHCI_P_IX_IF 0x08000000
209	#define ATA_AHCI_P_IX_HBD 0x10000000
210	#define ATA_AHCI_P_IX_HBF 0x20000000
211	#define ATA_AHCI_P_IX_TFE 0x40000000
212	#define ATA_AHCI_P_IX_CPD 0x80000000
213
214	#define ATA_AHCI_P_CMD 0x118
215	#define ATA_AHCI_P_CMD_ST 0x00000001
216	#define ATA_AHCI_P_CMD_SUD 0x00000002
217	#define ATA_AHCI_P_CMD_POD 0x00000004
218	#define ATA_AHCI_P_CMD_CLO 0x00000008
219	#define ATA_AHCI_P_CMD_FRE 0x00000010
220	#define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00
221	#define ATA_AHCI_P_CMD_ISS 0x00002000
222	#define ATA_AHCI_P_CMD_FR 0x00004000
223	#define ATA_AHCI_P_CMD_CR 0x00008000
224	#define ATA_AHCI_P_CMD_CPS 0x00010000
225	#define ATA_AHCI_P_CMD_PMA 0x00020000
226	#define ATA_AHCI_P_CMD_HPCP 0x00040000
227	#define ATA_AHCI_P_CMD_ISP 0x00080000
228	#define ATA_AHCI_P_CMD_CPD 0x00100000
229	#define ATA_AHCI_P_CMD_ATAPI 0x01000000
230	#define ATA_AHCI_P_CMD_DLAE 0x02000000
231	#define ATA_AHCI_P_CMD_ALPE 0x04000000
232	#define ATA_AHCI_P_CMD_ASP 0x08000000
233	#define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000
234	#define ATA_AHCI_P_CMD_NOOP 0x00000000
235	#define ATA_AHCI_P_CMD_ACTIVE 0x10000000
236	#define ATA_AHCI_P_CMD_PARTIAL 0x20000000
237	#define ATA_AHCI_P_CMD_SLUMBER 0x60000000
238
239	#define ATA_AHCI_P_TFD 0x120
240	#define ATA_AHCI_P_SIG 0x124
241	#define ATA_AHCI_P_SSTS 0x128
242	#define ATA_AHCI_P_SCTL 0x12c
243	#define ATA_AHCI_P_SERR 0x130
244	#define ATA_AHCI_P_SACT 0x134
245	#define ATA_AHCI_P_CI 0x138
246	#define ATA_AHCI_P_SNTF 0x13C
247	#define ATA_AHCI_P_FBS 0x140
248
249	#define ATA_AHCI_CL_SIZE 32
250	#define ATA_AHCI_CL_OFFSET 0
251	#define ATA_AHCI_FB_OFFSET (ATA_AHCI_CL_SIZE * 32)
252	#define ATA_AHCI_CT_OFFSET (ATA_AHCI_FB_OFFSET + 4096)
253	#define ATA_AHCI_CT_SIZE (2176 + 128)
254
255	struct ata_ahci_dma_prd {
256	u_int64_t dba;
257	u_int32_t reserved;
258	u_int32_t dbc; /* 0 based */
259	#define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */
260	#define ATA_AHCI_PRD_IPC (1<<31)
261	} __packed;
262
263	struct ata_ahci_cmd_tab {
264	u_int8_t cfis[64];
265	u_int8_t acmd[32];
266	u_int8_t reserved[32];
267	#define ATA_AHCI_DMA_ENTRIES 129
268	struct ata_ahci_dma_prd prd_tab[ATA_AHCI_DMA_ENTRIES];
269	} __packed;
270
271	struct ata_ahci_cmd_list {
272	u_int16_t cmd_flags;
273	#define ATA_AHCI_CMD_ATAPI 0x0020
274	#define ATA_AHCI_CMD_WRITE 0x0040
275	#define ATA_AHCI_CMD_PREFETCH 0x0080
276	#define ATA_AHCI_CMD_RESET 0x0100
277	#define ATA_AHCI_CMD_BIST 0x0200
278	#define ATA_AHCI_CMD_CLR_BUSY 0x0400
279
280	u_int16_t prd_length; /* PRD entries */
281	u_int32_t bytecount;
282	u_int64_t cmd_table_phys; /* 128byte aligned */
283	} __packed;
284
285
286	/* DMA register defines */	153	/* DMA register defines */
287	#define ATA_DMA_ENTRIES 256	154	#define ATA_DMA_ENTRIES 256
288	#define ATA_DMA_EOT 0x80000000	155	#define ATA_DMA_EOT 0x80000000

Lines 169-177 struct ata_pci_controller { Link Here

(-)sys/dev/ata/ata-pci.h (-76 lines)
169	#define ATA_I6300ESB_R1 0x25b08086	169	#define ATA_I6300ESB_R1 0x25b08086
170	#define ATA_I63XXESB2 0x269e8086	170	#define ATA_I63XXESB2 0x269e8086
171	#define ATA_I63XXESB2_S1 0x26808086	171	#define ATA_I63XXESB2_S1 0x26808086
172	#define ATA_I63XXESB2_S2 0x26818086
173	#define ATA_I63XXESB2_R1 0x26828086
174	#define ATA_I63XXESB2_R2 0x26838086
175	#define ATA_I82801FB 0x266f8086	172	#define ATA_I82801FB 0x266f8086
176	#define ATA_I82801FB_S1 0x26518086	173	#define ATA_I82801FB_S1 0x26518086
177	#define ATA_I82801FB_R1 0x26528086	174	#define ATA_I82801FB_R1 0x26528086
Lines 178-261 struct ata_pci_controller { Link Here
178	#define ATA_I82801FBM 0x26538086	175	#define ATA_I82801FBM 0x26538086
179	#define ATA_I82801GB 0x27df8086	176	#define ATA_I82801GB 0x27df8086
180	#define ATA_I82801GB_S1 0x27c08086	177	#define ATA_I82801GB_S1 0x27c08086
181	#define ATA_I82801GB_AH 0x27c18086
182	#define ATA_I82801GB_R1 0x27c38086
183	#define ATA_I82801GBM_S1 0x27c48086	178	#define ATA_I82801GBM_S1 0x27c48086
184	#define ATA_I82801GBM_AH 0x27c58086
185	#define ATA_I82801GBM_R1 0x27c68086
186	#define ATA_I82801HB_S1 0x28208086	179	#define ATA_I82801HB_S1 0x28208086
187	#define ATA_I82801HB_AH6 0x28218086
188	#define ATA_I82801HB_R1 0x28228086
189	#define ATA_I82801HB_AH4 0x28248086
190	#define ATA_I82801HB_S2 0x28258086	180	#define ATA_I82801HB_S2 0x28258086
191	#define ATA_I82801HBM 0x28508086	181	#define ATA_I82801HBM 0x28508086
192	#define ATA_I82801HBM_S1 0x28288086	182	#define ATA_I82801HBM_S1 0x28288086
193	#define ATA_I82801HBM_S2 0x28298086
194	#define ATA_I82801HBM_S3 0x282a8086
195	#define ATA_I82801IB_S1 0x29208086	183	#define ATA_I82801IB_S1 0x29208086
196	#define ATA_I82801IB_S3 0x29218086	184	#define ATA_I82801IB_S3 0x29218086
197	#define ATA_I82801IB_AH6 0x29228086
198	#define ATA_I82801IB_AH4 0x29238086
199	#define ATA_I82801IB_R1 0x29258086	185	#define ATA_I82801IB_R1 0x29258086
200	#define ATA_I82801IB_S2 0x29268086	186	#define ATA_I82801IB_S2 0x29268086
201	#define ATA_I82801IBM_S1 0x29288086	187	#define ATA_I82801IBM_S1 0x29288086
202	#define ATA_I82801IBM_AH 0x29298086
203	#define ATA_I82801IBM_R1 0x292a8086
204	#define ATA_I82801IBM_S2 0x292d8086	188	#define ATA_I82801IBM_S2 0x292d8086
205	#define ATA_I82801JIB_S1 0x3a208086	189	#define ATA_I82801JIB_S1 0x3a208086
206	#define ATA_I82801JIB_AH 0x3a228086
207	#define ATA_I82801JIB_R1 0x3a258086
208	#define ATA_I82801JIB_S2 0x3a268086	190	#define ATA_I82801JIB_S2 0x3a268086
209	#define ATA_I82801JD_S1 0x3a008086	191	#define ATA_I82801JD_S1 0x3a008086
210	#define ATA_I82801JD_AH 0x3a028086
211	#define ATA_I82801JD_R1 0x3a058086
212	#define ATA_I82801JD_S2 0x3a068086	192	#define ATA_I82801JD_S2 0x3a068086
213	#define ATA_I82801JI_S1 0x3a208086	193	#define ATA_I82801JI_S1 0x3a208086
214	#define ATA_I82801JI_AH 0x3a228086
215	#define ATA_I82801JI_R1 0x3a258086
216	#define ATA_I82801JI_S2 0x3a268086	194	#define ATA_I82801JI_S2 0x3a268086
217		195
218	#define ATA_5Series_S1 0x3b208086	196	#define ATA_5Series_S1 0x3b208086
219	#define ATA_5Series_S2 0x3b218086	197	#define ATA_5Series_S2 0x3b218086
220	#define ATA_5Series_AH1 0x3b228086
221	#define ATA_5Series_AH2 0x3b238086
222	#define ATA_5Series_R1 0x3b258086
223	#define ATA_5Series_S3 0x3b268086	198	#define ATA_5Series_S3 0x3b268086
224	#define ATA_5Series_S4 0x3b288086	199	#define ATA_5Series_S4 0x3b288086
225	#define ATA_5Series_AH3 0x3b298086
226	#define ATA_5Series_R2 0x3b2c8086
227	#define ATA_5Series_S5 0x3b2d8086	200	#define ATA_5Series_S5 0x3b2d8086
228	#define ATA_5Series_S6 0x3b2e8086	201	#define ATA_5Series_S6 0x3b2e8086
229	#define ATA_5Series_AH4 0x3b2f8086
230		202
231	#define ATA_CPT_S1 0x1c008086	203	#define ATA_CPT_S1 0x1c008086
232	#define ATA_CPT_S2 0x1c018086	204	#define ATA_CPT_S2 0x1c018086
233	#define ATA_CPT_AH1 0x1c028086
234	#define ATA_CPT_AH2 0x1c038086
235	#define ATA_CPT_R1 0x1c048086
236	#define ATA_CPT_R2 0x1c058086
237	#define ATA_CPT_S3 0x1c088086	205	#define ATA_CPT_S3 0x1c088086
238	#define ATA_CPT_S4 0x1c098086	206	#define ATA_CPT_S4 0x1c098086
239		207
240	#define ATA_PBG_S1 0x1d008086	208	#define ATA_PBG_S1 0x1d008086
241	#define ATA_PBG_AH1 0x1d028086
242	#define ATA_PBG_R1 0x1d048086
243	#define ATA_PBG_R2 0x1d068086
244	#define ATA_PBG_R3 0x28268086
245	#define ATA_PBG_S2 0x1d088086	209	#define ATA_PBG_S2 0x1d088086
246		210
247	#define ATA_PPT_S1 0x1e008086	211	#define ATA_PPT_S1 0x1e008086
248	#define ATA_PPT_S2 0x1e018086	212	#define ATA_PPT_S2 0x1e018086
249	#define ATA_PPT_AH1 0x1e028086
250	#define ATA_PPT_AH2 0x1e038086
251	#define ATA_PPT_R1 0x1e048086
252	#define ATA_PPT_R2 0x1e058086
253	#define ATA_PPT_R3 0x1e068086
254	#define ATA_PPT_R4 0x1e078086
255	#define ATA_PPT_S3 0x1e088086	213	#define ATA_PPT_S3 0x1e088086
256	#define ATA_PPT_S4 0x1e098086	214	#define ATA_PPT_S4 0x1e098086
257	#define ATA_PPT_R5 0x1e0e8086
258	#define ATA_PPT_R6 0x1e0f8086
259		215
260	#define ATA_AVOTON_S1 0x1f208086	216	#define ATA_AVOTON_S1 0x1f208086
261	#define ATA_AVOTON_S2 0x1f218086	217	#define ATA_AVOTON_S2 0x1f218086
Lines 264-292 struct ata_pci_controller { Link Here
264		220
265	#define ATA_LPT_S1 0x8c008086	221	#define ATA_LPT_S1 0x8c008086
266	#define ATA_LPT_S2 0x8c018086	222	#define ATA_LPT_S2 0x8c018086
267	#define ATA_LPT_AH1 0x8c028086
268	#define ATA_LPT_AH2 0x8c038086
269	#define ATA_LPT_R1 0x8c048086
270	#define ATA_LPT_R2 0x8c058086
271	#define ATA_LPT_R3 0x8c068086
272	#define ATA_LPT_R4 0x8c078086
273	#define ATA_LPT_S3 0x8c088086	223	#define ATA_LPT_S3 0x8c088086
274	#define ATA_LPT_S4 0x8c098086	224	#define ATA_LPT_S4 0x8c098086
275	#define ATA_LPT_R5 0x8c0e8086
276	#define ATA_LPT_R6 0x8c0f8086
277		225
278	#define ATA_WCPT_S1 0x8c808086	226	#define ATA_WCPT_S1 0x8c808086
279	#define ATA_WCPT_S2 0x8c818086	227	#define ATA_WCPT_S2 0x8c818086
280	#define ATA_WCPT_AH1 0x8c828086
281	#define ATA_WCPT_AH2 0x8c838086
282	#define ATA_WCPT_R1 0x8c848086
283	#define ATA_WCPT_R2 0x8c858086
284	#define ATA_WCPT_R3 0x8c868086
285	#define ATA_WCPT_R4 0x8c878086
286	#define ATA_WCPT_S3 0x8c888086	228	#define ATA_WCPT_S3 0x8c888086
287	#define ATA_WCPT_S4 0x8c898086	229	#define ATA_WCPT_S4 0x8c898086
288	#define ATA_WCPT_R5 0x8c8e8086
289	#define ATA_WCPT_R6 0x8c8f8086
290		230
291	#define ATA_WELLS_S1 0x8d008086	231	#define ATA_WELLS_S1 0x8d008086
292	#define ATA_WELLS_S2 0x8d088086	232	#define ATA_WELLS_S2 0x8d088086
Lines 300-308 struct ata_pci_controller { Link Here
300		240
301	#define ATA_I31244 0x32008086	241	#define ATA_I31244 0x32008086
302	#define ATA_ISCH 0x811a8086	242	#define ATA_ISCH 0x811a8086
303	#define ATA_DH89XXCC 0x23238086
304		243
305	#define ATA_COLETOCRK_AH1 0x23a38086
306	#define ATA_COLETOCRK_S1 0x23a18086	244	#define ATA_COLETOCRK_S1 0x23a18086
307	#define ATA_COLETOCRK_S2 0x23a68086	245	#define ATA_COLETOCRK_S2 0x23a68086
308		246
Lines 322-335 struct ata_pci_controller { Link Here
322	#define ATA_JMB368_2 0x0368197b	260	#define ATA_JMB368_2 0x0368197b
323		261
324	#define ATA_MARVELL_ID 0x11ab	262	#define ATA_MARVELL_ID 0x11ab
325	#define ATA_M88SX5040 0x504011ab
326	#define ATA_M88SX5041 0x504111ab
327	#define ATA_M88SX5080 0x508011ab
328	#define ATA_M88SX5081 0x508111ab
329	#define ATA_M88SX6041 0x604111ab
330	#define ATA_M88SX6042 0x604211ab
331	#define ATA_M88SX6081 0x608111ab
332	#define ATA_M88SX7042 0x704211ab
333	#define ATA_M88SE6101 0x610111ab	263	#define ATA_M88SE6101 0x610111ab
334	#define ATA_M88SE6102 0x610211ab	264	#define ATA_M88SE6102 0x610211ab
335	#define ATA_M88SE6111 0x611111ab	265	#define ATA_M88SE6111 0x611111ab
Lines 505-514 struct ata_pci_controller { Link Here
505	#define ATA_SII3512 0x35121095	435	#define ATA_SII3512 0x35121095
506	#define ATA_SII3112 0x31121095	436	#define ATA_SII3112 0x31121095
507	#define ATA_SII3112_1 0x02401095	437	#define ATA_SII3112_1 0x02401095
508	#define ATA_SII3124 0x31241095
509	#define ATA_SII3132 0x31321095
510	#define ATA_SII3132_1 0x02421095
511	#define ATA_SII3132_2 0x02441095
512	#define ATA_SII0680 0x06801095	438	#define ATA_SII0680 0x06801095
513	#define ATA_CMD646 0x06461095	439	#define ATA_CMD646 0x06461095
514	#define ATA_CMD648 0x06481095	440	#define ATA_CMD648 0x06481095
Lines 631-638 const struct ata_chip_id *ata_find_chip(device_t d Link Here
631	int ata_mode2idx(int mode);	557	int ata_mode2idx(int mode);
632		558
633	/* global prototypes from chipsets/ata-.c /	559	/* global prototypes from chipsets/ata-.c /
634	int ata_ahci_chipinit(device_t);
635	int ata_marvell_edma_chipinit(device_t);
636	int ata_sii_chipinit(device_t);	560	int ata_sii_chipinit(device_t);
637		561
638	/* externs */	562	/* externs */

Lines 1-82 Link Here

(-)sys/dev/ata/chipsets/ata-adaptec.c (-82 lines)
1	/*-
2	* Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3	* All rights reserved.
4	*
5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions
7	* are met:
8	* 1. Redistributions of source code must retain the above copyright
9	* notice, this list of conditions and the following disclaimer,
10	* without modification, immediately at the beginning of the file.
11	* 2. Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25	*/
26
27	#include <sys/cdefs.h>
28	__FBSDID("$FreeBSD$");
29
30	#include <sys/param.h>
31	#include <sys/module.h>
32	#include <sys/systm.h>
33	#include <sys/kernel.h>
34	#include <sys/ata.h>
35	#include <sys/bus.h>
36	#include <sys/endian.h>
37	#include <sys/malloc.h>
38	#include <sys/lock.h>
39	#include <sys/mutex.h>
40	#include <sys/sema.h>
41	#include <sys/taskqueue.h>
42	#include <vm/uma.h>
43	#include <machine/stdarg.h>
44	#include <machine/resource.h>
45	#include <machine/bus.h>
46	#include <sys/rman.h>
47	#include <dev/pci/pcivar.h>
48	#include <dev/pci/pcireg.h>
49	#include <dev/ata/ata-all.h>
50	#include <dev/ata/ata-pci.h>
51	#include <ata_if.h>
52
53	/* misc defines */
54	#define MV_60XX 60 //must match ata_marvell.c's definition
55	#define MV_7042 72 //must match ata_marvell.c's definition
56
57	/*
58	* Adaptec chipset support functions
59	*/
60	static int
61	ata_adaptec_probe(device_t dev)
62	{
63	struct ata_pci_controller *ctlr = device_get_softc(dev);
64	static const struct ata_chip_id ids[] =
65	{{ ATA_ADAPTEC_1420, 0, 4, MV_60XX, ATA_SA300, "1420SA" },
66	{ ATA_ADAPTEC_1430, 0, 4, MV_7042, ATA_SA300, "1430SA" },
67	{ 0, 0, 0, 0, 0, 0}};
68
69	if (pci_get_vendor(dev) != ATA_ADAPTEC_ID)
70	return ENXIO;
71
72	if (!(ctlr->chip = ata_match_chip(dev, ids)))
73	return ENXIO;
74
75	ata_set_desc(dev);
76	ctlr->chipinit = ata_marvell_edma_chipinit;
77
78	return (BUS_PROBE_LOW_PRIORITY);
79	}
80
81	ATA_DECLARE_DRIVER(ata_adaptec);
82	MODULE_DEPEND(ata_adaptec, ata_marvell, 1, 1, 1);

Lines 64-72 static int ata_ati_setmode(device_t dev, int targe Link Here

(-)sys/dev/ata/chipsets/ata-ati.c (-10 / +5 lines)
64	#define ATI_PATA 0x02	64	#define ATI_PATA 0x02
65	#define ATI_AHCI 0x04	65	#define ATI_AHCI 0x04
66		66
67	static int force_ahci = 1;
68	TUNABLE_INT("hw.ahci.force", &force_ahci);
69
70	/*	67	/*
71	* ATI chipset support functions	68	* ATI chipset support functions
72	*/	69	*/
Lines 104-111 ata_ati_probe(device_t dev) Link Here
104	if (!(ctlr->chip = ata_match_chip(dev, ids)))	101	if (!(ctlr->chip = ata_match_chip(dev, ids)))
105	return ENXIO;	102	return ENXIO;
106		103
107	ata_set_desc(dev);
108
109	switch (ctlr->chip->cfg1) {	104	switch (ctlr->chip->cfg1) {
110	case ATI_PATA:	105	case ATI_PATA:
111	ctlr->chipinit = ata_ati_chipinit;	106	ctlr->chipinit = ata_ati_chipinit;
Lines 117-128 ata_ati_probe(device_t dev) Link Here
117	ctlr->chipinit = ata_sii_chipinit;	112	ctlr->chipinit = ata_sii_chipinit;
118	break;	113	break;
119	case ATI_AHCI:	114	case ATI_AHCI:
120	if (force_ahci == 1 \|\| pci_get_subclass(dev) != PCIS_STORAGE_IDE)	115	if (pci_get_subclass(dev) != PCIS_STORAGE_IDE)
121	ctlr->chipinit = ata_ahci_chipinit;	116	return (ENXIO);
122	else	117	ctlr->chipinit = ata_ati_chipinit;
123	ctlr->chipinit = ata_ati_chipinit;
124	break;	118	break;
125	}	119	}
		120
		121	ata_set_desc(dev);
126	return (BUS_PROBE_LOW_PRIORITY);	122	return (BUS_PROBE_LOW_PRIORITY);
127	}	123	}
128		124
Lines 264-268 ata_ati_setmode(device_t dev, int target, int mode Link Here
264	}	260	}
265		261
266	ATA_DECLARE_DRIVER(ata_ati);	262	ATA_DECLARE_DRIVER(ata_ati);
267	MODULE_DEPEND(ata_ati, ata_ahci, 1, 1, 1);
268	MODULE_DEPEND(ata_ati, ata_sii, 1, 1, 1);	263	MODULE_DEPEND(ata_ati, ata_sii, 1, 1, 1);

Lines 80-86 static void ata_intel_31244_tf_write(struct ata_re Link Here

(-)sys/dev/ata/chipsets/ata-intel.c (-77 / +3 lines)
80	static void ata_intel_31244_reset(device_t dev);	80	static void ata_intel_31244_reset(device_t dev);
81		81
82	/* misc defines */	82	/* misc defines */
83	#define INTEL_AHCI 1
84	#define INTEL_ICH5 2	83	#define INTEL_ICH5 2
85	#define INTEL_6CH 4	84	#define INTEL_6CH 4
86	#define INTEL_6CH2 8	85	#define INTEL_6CH2 8
Lines 127-216 ata_intel_probe(device_t dev) Link Here
127	{ ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" },	126	{ ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" },
128	{ ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" },	127	{ ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" },
129	{ ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" },	128	{ ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" },
130	{ ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" },	129	{ ATA_I82801FB_S1, 0, 0, 0, ATA_SA150, "ICH6" },
131	{ ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" },	130	{ ATA_I82801FB_R1, 0, 0, 0, ATA_SA150, "ICH6" },
132	{ ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" },	131	{ ATA_I82801FBM, 0, 0, 0, ATA_SA150, "ICH6M" },
133	{ ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" },	132	{ ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" },
134	{ ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" },	133	{ ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" },
135	{ ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
136	{ ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
137	{ ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" },	134	{ ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" },
138	{ ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
139	{ ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
140	{ ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" },	135	{ ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" },
141	{ ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" },	136	{ ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" },
142	{ ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
143	{ ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
144	{ ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
145	{ ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" },	137	{ ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" },
146	{ ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" },	138	{ ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" },
147	{ ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
148	{ ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
149	{ ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
150	{ ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" },	139	{ ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" },
151	{ ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" },	140	{ ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" },
152	{ ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
153	{ ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
154	{ ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" },	141	{ ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" },
155	{ ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" },	142	{ ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" },
156	{ ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" },	143	{ ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" },
157	{ ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
158	{ ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
159	{ ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
160	{ ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },	144	{ ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },
161	{ ATA_I82801IBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" },
162	{ ATA_I82801IBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" },
163	{ ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },	145	{ ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },
164	{ ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },	146	{ ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },
165	{ ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
166	{ ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
167	{ ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },	147	{ ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
168	{ ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },	148	{ ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },
169	{ ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
170	{ ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
171	{ ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },	149	{ ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
172	{ ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },	150	{ ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },
173	{ ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
174	{ ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
175	{ ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },	151	{ ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
176	{ ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },	152	{ ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },
177	{ ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },	153	{ ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
178	{ ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
179	{ ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
180	{ ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
181	{ ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },	154	{ ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
182	{ ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },	155	{ ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },
183	{ ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
184	{ ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
185	{ ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },	156	{ ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
186	{ ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },	157	{ ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },
187	{ ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
188	{ ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" },	158	{ ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" },
189	{ ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" },	159	{ ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" },
190	{ ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
191	{ ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
192	{ ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
193	{ ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
194	{ ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" },	160	{ ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" },
195	{ ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" },	161	{ ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" },
196	{ ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" },	162	{ ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" },
197	{ ATA_PBG_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
198	{ ATA_PBG_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
199	{ ATA_PBG_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
200	{ ATA_PBG_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
201	{ ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" },	163	{ ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" },
202	{ ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" },	164	{ ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" },
203	{ ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" },	165	{ ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" },
204	{ ATA_PPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
205	{ ATA_PPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
206	{ ATA_PPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
207	{ ATA_PPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
208	{ ATA_PPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
209	{ ATA_PPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
210	{ ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" },	166	{ ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" },
211	{ ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" },	167	{ ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" },
212	{ ATA_PPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
213	{ ATA_PPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
214	{ ATA_AVOTON_S1, 0, INTEL_6CH, 0, ATA_SA300, "Avoton" },	168	{ ATA_AVOTON_S1, 0, INTEL_6CH, 0, ATA_SA300, "Avoton" },
215	{ ATA_AVOTON_S2, 0, INTEL_6CH, 0, ATA_SA300, "Avoton" },	169	{ ATA_AVOTON_S2, 0, INTEL_6CH, 0, ATA_SA300, "Avoton" },
216	{ ATA_AVOTON_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" },	170	{ ATA_AVOTON_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" },
Lines 217-244 ata_intel_probe(device_t dev) Link Here
217	{ ATA_AVOTON_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" },	171	{ ATA_AVOTON_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" },
218	{ ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" },	172	{ ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" },
219	{ ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" },	173	{ ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" },
220	{ ATA_LPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
221	{ ATA_LPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
222	{ ATA_LPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
223	{ ATA_LPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
224	{ ATA_LPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
225	{ ATA_LPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
226	{ ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" },	174	{ ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" },
227	{ ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" },	175	{ ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" },
228	{ ATA_LPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
229	{ ATA_LPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
230	{ ATA_WCPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Wildcat Point" },	176	{ ATA_WCPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Wildcat Point" },
231	{ ATA_WCPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Wildcat Point" },	177	{ ATA_WCPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Wildcat Point" },
232	{ ATA_WCPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
233	{ ATA_WCPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
234	{ ATA_WCPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
235	{ ATA_WCPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
236	{ ATA_WCPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
237	{ ATA_WCPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
238	{ ATA_WCPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" },	178	{ ATA_WCPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" },
239	{ ATA_WCPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" },	179	{ ATA_WCPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" },
240	{ ATA_WCPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
241	{ ATA_WCPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
242	{ ATA_WELLS_S1, 0, INTEL_6CH, 0, ATA_SA300, "Wellsburg" },	180	{ ATA_WELLS_S1, 0, INTEL_6CH, 0, ATA_SA300, "Wellsburg" },
243	{ ATA_WELLS_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Wellsburg" },	181	{ ATA_WELLS_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Wellsburg" },
244	{ ATA_WELLS_S3, 0, INTEL_6CH, 0, ATA_SA300, "Wellsburg" },	182	{ ATA_WELLS_S3, 0, INTEL_6CH, 0, ATA_SA300, "Wellsburg" },
Lines 249-258 ata_intel_probe(device_t dev) Link Here
249	{ ATA_LPTLP_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" },	187	{ ATA_LPTLP_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" },
250	{ ATA_I31244, 0, 0, 2, ATA_SA150, "31244" },	188	{ ATA_I31244, 0, 0, 2, ATA_SA150, "31244" },
251	{ ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" },	189	{ ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" },
252	{ ATA_DH89XXCC, 0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" },
253	{ ATA_COLETOCRK_S1, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" },	190	{ ATA_COLETOCRK_S1, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" },
254	{ ATA_COLETOCRK_S2, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" },	191	{ ATA_COLETOCRK_S2, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" },
255	{ ATA_COLETOCRK_AH1,0, INTEL_AHCI, 0, ATA_SA300, "COLETOCRK" },
256	{ 0, 0, 0, 0, 0, 0}};	192	{ 0, 0, 0, 0, 0, 0}};
257		193
258	if (pci_get_vendor(dev) != ATA_INTEL_ID)	194	if (pci_get_vendor(dev) != ATA_INTEL_ID)
Lines 326-340 ata_intel_chipinit(device_t dev) Link Here
326	ctlr->ch_detach = ata_pci_ch_detach;	262	ctlr->ch_detach = ata_pci_ch_detach;
327	ctlr->reset = ata_intel_reset;	263	ctlr->reset = ata_intel_reset;
328		264
329	/*
330	* if we have AHCI capability and AHCI or RAID mode enabled
331	* in BIOS we try for AHCI mode
332	*/
333	if ((ctlr->chip->cfg1 & INTEL_AHCI) &&
334	(pci_read_config(dev, 0x90, 1) & 0xc0) &&
335	(ata_ahci_chipinit(dev) != ENXIO))
336	return 0;
337
338	/* BAR(5) may point to SATA interface registers */	265	/* BAR(5) may point to SATA interface registers */
339	if ((ctlr->chip->cfg1 & INTEL_ICH7)) {	266	if ((ctlr->chip->cfg1 & INTEL_ICH7)) {
340	ctlr->r_type2 = SYS_RES_MEMORY;	267	ctlr->r_type2 = SYS_RES_MEMORY;
Lines 995-998 ata_intel_31244_reset(device_t dev) Link Here
995	}	922	}
996		923
997	ATA_DECLARE_DRIVER(ata_intel);	924	ATA_DECLARE_DRIVER(ata_intel);
998	MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1);

Lines 55-74 static int ata_marvell_chipinit(device_t dev); Link Here

(-)sys/dev/ata/chipsets/ata-marvell.c (-448 / +1 lines)
55	static int ata_marvell_ch_attach(device_t dev);	55	static int ata_marvell_ch_attach(device_t dev);
56	static int ata_marvell_setmode(device_t dev, int target, int mode);	56	static int ata_marvell_setmode(device_t dev, int target, int mode);
57	static int ata_marvell_dummy_chipinit(device_t dev);	57	static int ata_marvell_dummy_chipinit(device_t dev);
58	static int ata_marvell_edma_ch_attach(device_t dev);
59	static int ata_marvell_edma_ch_detach(device_t dev);
60	static int ata_marvell_edma_status(device_t dev);
61	static int ata_marvell_edma_begin_transaction(struct ata_request *request);
62	static int ata_marvell_edma_end_transaction(struct ata_request *request);
63	static void ata_marvell_edma_reset(device_t dev);
64	static void ata_marvell_edma_dmasetprd(void xsc, bus_dma_segment_t segs, int nsegs, int error);
65	static void ata_marvell_edma_dmainit(device_t dev);
66		58
67	/* misc defines */	59	/* misc defines */
68	#define MV_50XX 50
69	#define MV_60XX 60
70	#define MV_6042 62
71	#define MV_7042 72
72	#define MV_61XX 61	60	#define MV_61XX 61
73	#define MV_91XX 91	61	#define MV_91XX 91
74		62
Lines 99-113 ata_marvell_probe(device_t dev) Link Here
99	{	87	{
100	struct ata_pci_controller *ctlr = device_get_softc(dev);	88	struct ata_pci_controller *ctlr = device_get_softc(dev);
101	static const struct ata_chip_id ids[] =	89	static const struct ata_chip_id ids[] =
102	{{ ATA_M88SX5040, 0, 4, MV_50XX, ATA_SA150, "88SX5040" },	90	{{ ATA_M88SE6101, 0, 0, MV_61XX, ATA_UDMA6, "88SE6101" },
103	{ ATA_M88SX5041, 0, 4, MV_50XX, ATA_SA150, "88SX5041" },
104	{ ATA_M88SX5080, 0, 8, MV_50XX, ATA_SA150, "88SX5080" },
105	{ ATA_M88SX5081, 0, 8, MV_50XX, ATA_SA150, "88SX5081" },
106	{ ATA_M88SX6041, 0, 4, MV_60XX, ATA_SA300, "88SX6041" },
107	{ ATA_M88SX6042, 0, 4, MV_6042, ATA_SA300, "88SX6042" },
108	{ ATA_M88SX6081, 0, 8, MV_60XX, ATA_SA300, "88SX6081" },
109	{ ATA_M88SX7042, 0, 4, MV_7042, ATA_SA300, "88SX7042" },
110	{ ATA_M88SE6101, 0, 0, MV_61XX, ATA_UDMA6, "88SE6101" },
111	{ ATA_M88SE6102, 0, 0, MV_61XX, ATA_UDMA6, "88SE6102" },	91	{ ATA_M88SE6102, 0, 0, MV_61XX, ATA_UDMA6, "88SE6102" },
112	{ ATA_M88SE6111, 0, 1, MV_61XX, ATA_UDMA6, "88SE6111" },	92	{ ATA_M88SE6111, 0, 1, MV_61XX, ATA_UDMA6, "88SE6111" },
113	{ ATA_M88SE6121, 0, 2, MV_61XX, ATA_UDMA6, "88SE6121" },	93	{ ATA_M88SE6121, 0, 2, MV_61XX, ATA_UDMA6, "88SE6121" },
Lines 126-137 ata_marvell_probe(device_t dev) Link Here
126	ata_set_desc(dev);	106	ata_set_desc(dev);
127		107
128	switch (ctlr->chip->cfg2) {	108	switch (ctlr->chip->cfg2) {
129	case MV_50XX:
130	case MV_60XX:
131	case MV_6042:
132	case MV_7042:
133	ctlr->chipinit = ata_marvell_edma_chipinit;
134	break;
135	case MV_61XX:	109	case MV_61XX:
136	ctlr->chipinit = ata_marvell_chipinit;	110	ctlr->chipinit = ata_marvell_chipinit;
137	break;	111	break;
Lines 205-629 ata_marvell_dummy_chipinit(device_t dev) Link Here
205	return (0);	179	return (0);
206	}	180	}
207		181
208	int
209	ata_marvell_edma_chipinit(device_t dev)
210	{
211	struct ata_pci_controller *ctlr = device_get_softc(dev);
212
213	if (ata_setup_interrupt(dev, ata_generic_intr))
214	return ENXIO;
215
216	ctlr->r_type1 = SYS_RES_MEMORY;
217	ctlr->r_rid1 = PCIR_BAR(0);
218	if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
219	&ctlr->r_rid1, RF_ACTIVE)))
220	return ENXIO;
221
222	/* mask all host controller interrupts */
223	ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
224
225	/* mask all PCI interrupts */
226	ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
227
228	ctlr->ch_attach = ata_marvell_edma_ch_attach;
229	ctlr->ch_detach = ata_marvell_edma_ch_detach;
230	ctlr->reset = ata_marvell_edma_reset;
231	ctlr->setmode = ata_sata_setmode;
232	ctlr->getrev = ata_sata_getrev;
233	ctlr->channels = ctlr->chip->cfg1;
234
235	/* clear host controller interrupts */
236	ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
237	if (ctlr->chip->cfg1 > 4)
238	ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
239
240	/* clear PCI interrupts */
241	ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
242
243	/* unmask PCI interrupts we want */
244	ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
245
246	/* unmask host controller interrupts we want */
247	ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/HC0/ \| 0x0001fe00/HC1/ \|
248	/(1<<19) \| (1<<20) \| (1<<21) \|/(1<<22) \| (1<<24) \| (0x7f << 25));
249
250	return 0;
251	}
252
253	static int
254	ata_marvell_edma_ch_attach(device_t dev)
255	{
256	struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
257	struct ata_channel *ch = device_get_softc(dev);
258	u_int64_t work;
259	int i;
260
261	ata_marvell_edma_dmainit(dev);
262	work = ch->dma.work_bus;
263	/* clear work area */
264	bzero(ch->dma.work, 1024+256);
265	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
266	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
267
268	/* set legacy ATA resources */
269	for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
270	ch->r_io[i].res = ctlr->r_res1;
271	ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
272	}
273	ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
274	ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
275	ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
276	ata_default_registers(dev);
277
278	/* set SATA resources */
279	switch (ctlr->chip->cfg2) {
280	case MV_50XX:
281	ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
282	ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
283	ch->r_io[ATA_SERROR].res = ctlr->r_res1;
284	ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
285	ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
286	ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
287	break;
288	case MV_60XX:
289	case MV_6042:
290	case MV_7042:
291	ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
292	ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
293	ch->r_io[ATA_SERROR].res = ctlr->r_res1;
294	ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
295	ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
296	ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
297	ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
298	ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
299	break;
300	}
301
302	ch->flags \|= ATA_NO_SLAVE;
303	ch->flags \|= ATA_USE_16BIT; /* XXX SOS needed ? */
304	ch->flags \|= ATA_SATA;
305	ata_generic_hw(dev);
306	ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
307	ch->hw.end_transaction = ata_marvell_edma_end_transaction;
308	ch->hw.status = ata_marvell_edma_status;
309
310	/* disable the EDMA machinery */
311	ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
312	DELAY(100000); /* SOS should poll for disabled */
313
314	/* set configuration to non-queued 128b read transfers stop on error */
315	ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) \| (1<<13));
316
317	/* request queue base high */
318	ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
319
320	/* request queue in ptr */
321	ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
322
323	/* request queue out ptr */
324	ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
325
326	/* response queue base high */
327	work += 1024;
328	ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
329
330	/* response queue in ptr */
331	ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
332
333	/* response queue out ptr */
334	ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
335
336	/* clear SATA error register */
337	ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
338
339	/* clear any outstanding error interrupts */
340	ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
341
342	/* unmask all error interrupts */
343	ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
344
345	/* enable EDMA machinery */
346	ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
347	return 0;
348	}
349
350	static int
351	ata_marvell_edma_ch_detach(device_t dev)
352	{
353	struct ata_channel *ch = device_get_softc(dev);
354
355	if (ch->dma.work_tag && ch->dma.work_map)
356	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
357	BUS_DMASYNC_POSTREAD \| BUS_DMASYNC_POSTWRITE);
358	ata_dmafini(dev);
359	return (0);
360	}
361
362	static int
363	ata_marvell_edma_status(device_t dev)
364	{
365	struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
366	struct ata_channel *ch = device_get_softc(dev);
367	u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
368	int shift = (ch->unit << 1) + (ch->unit > 3);
369
370	if (cause & (1 << shift)) {
371
372	/* clear interrupt(s) */
373	ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
374
375	/* do we have any PHY events ? */
376	ata_sata_phy_check_events(dev, -1);
377	}
378
379	/* do we have any device action ? */
380	return (cause & (2 << shift));
381	}
382
383	/* must be called with ATA channel locked and state_mtx held */
384	static int
385	ata_marvell_edma_begin_transaction(struct ata_request *request)
386	{
387	struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
388	struct ata_channel *ch = device_get_softc(request->parent);
389	u_int32_t req_in;
390	u_int8_t *bytep;
391	int i;
392	int error, slot;
393
394	/* only DMA R/W goes through the EMDA machine */
395	if (request->u.ata.command != ATA_READ_DMA &&
396	request->u.ata.command != ATA_WRITE_DMA &&
397	request->u.ata.command != ATA_READ_DMA48 &&
398	request->u.ata.command != ATA_WRITE_DMA48) {
399
400	/* disable the EDMA machinery */
401	if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
402	ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
403	return ata_begin_transaction(request);
404	}
405
406	/* check sanity, setup SG list and DMA engine */
407	if ((error = ch->dma.load(request, NULL, NULL))) {
408	device_printf(request->parent, "setting up DMA failed\n");
409	request->result = error;
410	return ATA_OP_FINISHED;
411	}
412
413	/* get next free request queue slot */
414	req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
415	slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
416	bytep = (u_int8_t *)(ch->dma.work);
417	bytep += (slot << 5);
418
419	/* fill in this request */
420	le32enc(bytep + 0 * sizeof(u_int32_t),
421	request->dma->sg_bus & 0xffffffff);
422	le32enc(bytep + 1 * sizeof(u_int32_t),
423	(u_int64_t)request->dma->sg_bus >> 32);
424	if (ctlr->chip->cfg2 != MV_6042 && ctlr->chip->cfg2 != MV_7042) {
425	le16enc(bytep + 4 * sizeof(u_int16_t),
426	(request->flags & ATA_R_READ ? 0x01 : 0x00) \| (request->tag << 1));
427
428	i = 10;
429	bytep[i++] = (request->u.ata.count >> 8) & 0xff;
430	bytep[i++] = 0x10 \| ATA_COUNT;
431	bytep[i++] = request->u.ata.count & 0xff;
432	bytep[i++] = 0x10 \| ATA_COUNT;
433
434	bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
435	bytep[i++] = 0x10 \| ATA_SECTOR;
436	bytep[i++] = request->u.ata.lba & 0xff;
437	bytep[i++] = 0x10 \| ATA_SECTOR;
438
439	bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
440	bytep[i++] = 0x10 \| ATA_CYL_LSB;
441	bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
442	bytep[i++] = 0x10 \| ATA_CYL_LSB;
443
444	bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
445	bytep[i++] = 0x10 \| ATA_CYL_MSB;
446	bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
447	bytep[i++] = 0x10 \| ATA_CYL_MSB;
448
449	bytep[i++] = ATA_D_LBA \| ATA_D_IBM \| ((request->u.ata.lba >> 24) & 0xf);
450	bytep[i++] = 0x10 \| ATA_DRIVE;
451
452	bytep[i++] = request->u.ata.command;
453	bytep[i++] = 0x90 \| ATA_COMMAND;
454	} else {
455	le32enc(bytep + 2 * sizeof(u_int32_t),
456	(request->flags & ATA_R_READ ? 0x01 : 0x00) \| (request->tag << 1));
457
458	i = 16;
459	bytep[i++] = 0;
460	bytep[i++] = 0;
461	bytep[i++] = request->u.ata.command;
462	bytep[i++] = request->u.ata.feature & 0xff;
463
464	bytep[i++] = request->u.ata.lba & 0xff;
465	bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
466	bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
467	bytep[i++] = ATA_D_LBA \| ATA_D_IBM \| ((request->u.ata.lba >> 24) & 0x0f);
468
469	bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
470	bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
471	bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
472	bytep[i++] = (request->u.ata.feature >> 8) & 0xff;
473
474	bytep[i++] = request->u.ata.count & 0xff;
475	bytep[i++] = (request->u.ata.count >> 8) & 0xff;
476	bytep[i++] = 0;
477	bytep[i++] = 0;
478	}
479
480	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
481	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
482
483	/* enable EDMA machinery if needed */
484	if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
485	ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
486	while (!(ATA_INL(ctlr->r_res1,
487	0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
488	DELAY(10);
489	}
490
491	/* tell EDMA it has a new request */
492	slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
493	req_in &= 0xfffffc00;
494	req_in += (slot << 5);
495	ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
496
497	return ATA_OP_CONTINUES;
498	}
499
500	/* must be called with ATA channel locked and state_mtx held */
501	static int
502	ata_marvell_edma_end_transaction(struct ata_request *request)
503	{
504	struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
505	struct ata_channel *ch = device_get_softc(request->parent);
506	int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
507	u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
508	int res;
509
510	/* EDMA interrupt */
511	if ((icr & (0x0001 << (ch->unit & 3)))) {
512	struct ata_marvell_response *response;
513	u_int32_t rsp_in, rsp_out;
514	int slot;
515
516	/* stop timeout */
517	callout_stop(&request->callout);
518
519	/* get response ptr's */
520	rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
521	rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
522	slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
523	rsp_out &= 0xffffff00;
524	rsp_out += (slot << 3);
525	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
526	BUS_DMASYNC_POSTREAD \| BUS_DMASYNC_POSTWRITE);
527	response = (struct ata_marvell_response *)
528	(ch->dma.work + 1024 + (slot << 3));
529
530	/* record status for this request */
531	request->status = response->dev_status;
532	request->error = 0;
533
534	/* ack response */
535	ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
536
537	/* update progress */
538	if (!(request->status & ATA_S_ERROR) &&
539	!(request->flags & ATA_R_TIMEOUT))
540	request->donecount = request->bytecount;
541
542	/* unload SG list */
543	ch->dma.unload(request);
544
545	res = ATA_OP_FINISHED;
546	}
547
548	/* legacy ATA interrupt */
549	else {
550	res = ata_end_transaction(request);
551	}
552
553	/* ack interrupt */
554	ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
555	return res;
556	}
557
558	static void
559	ata_marvell_edma_reset(device_t dev)
560	{
561	struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
562	struct ata_channel *ch = device_get_softc(dev);
563
564	/* disable the EDMA machinery */
565	ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
566	while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
567	DELAY(10);
568
569	/* clear SATA error register */
570	ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
571
572	/* clear any outstanding error interrupts */
573	ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
574
575	/* unmask all error interrupts */
576	ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
577
578	/* enable channel and test for devices */
579	if (ata_sata_phy_reset(dev, -1, 1))
580	ata_generic_reset(dev);
581	else
582	ch->devices = 0;
583
584	/* enable EDMA machinery */
585	ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
586	}
587
588	static void
589	ata_marvell_edma_dmasetprd(void xsc, bus_dma_segment_t segs, int nsegs,
590	int error)
591	{
592	struct ata_dmasetprd_args *args = xsc;
593	struct ata_marvell_dma_prdentry *prd = args->dmatab;
594	int i;
595
596	if ((args->error = error))
597	return;
598
599	for (i = 0; i < nsegs; i++) {
600	prd[i].addrlo = htole32(segs[i].ds_addr);
601	prd[i].count = htole32(segs[i].ds_len);
602	prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
603	prd[i].reserved = 0;
604	}
605	prd[i - 1].count \|= htole32(ATA_DMA_EOT);
606	KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
607	args->nsegs = nsegs;
608	}
609
610	static void
611	ata_marvell_edma_dmainit(device_t dev)
612	{
613	struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
614	struct ata_channel *ch = device_get_softc(dev);
615
616	/* note start and stop are not used here */
617	ch->dma.setprd = ata_marvell_edma_dmasetprd;
618
619	/* if 64bit support present adjust max address used */
620	if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
621	ch->dma.max_address = BUS_SPACE_MAXADDR;
622
623	/* chip does not reliably do 64K DMA transfers */
624	if (ctlr->chip->cfg2 == MV_50XX \|\| ctlr->chip->cfg2 == MV_60XX)
625	ch->dma.max_iosize = 64 * DEV_BSIZE;
626	ata_dmainit(dev);
627	}
628
629	ATA_DECLARE_DRIVER(ata_marvell);	182	ATA_DECLARE_DRIVER(ata_marvell);

Lines 62-72 static int ata_nvidia_setmode(device_t dev, int ta Link Here

(-)sys/dev/ata/chipsets/ata-nvidia.c (-12 / +6 lines)
62	#define NV4 0x01	62	#define NV4 0x01
63	#define NVQ 0x02	63	#define NVQ 0x02
64	#define NVAHCI 0x04	64	#define NVAHCI 0x04
65	#define NVNOFORCE 0x08
66		65
67	static int force_ahci = 1;
68	TUNABLE_INT("hw.ahci.force", &force_ahci);
69
70	/*	66	/*
71	* nVidia chipset support functions	67	* nVidia chipset support functions
72	*/	68	*/
Lines 161-167 ata_nvidia_probe(device_t dev) Link Here
161	{ ATA_NFORCE_MCP79_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" },	157	{ ATA_NFORCE_MCP79_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" },
162	{ ATA_NFORCE_MCP79_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" },	158	{ ATA_NFORCE_MCP79_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" },
163	{ ATA_NFORCE_MCP89_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" },	159	{ ATA_NFORCE_MCP89_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" },
164	{ ATA_NFORCE_MCP89_A1, 0, NVAHCI\|NVNOFORCE, 0, ATA_SA300, "nForce MCP89" },	160	{ ATA_NFORCE_MCP89_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" },
165	{ ATA_NFORCE_MCP89_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" },	161	{ ATA_NFORCE_MCP89_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" },
166	{ ATA_NFORCE_MCP89_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" },	162	{ ATA_NFORCE_MCP89_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" },
167	{ ATA_NFORCE_MCP89_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" },	163	{ ATA_NFORCE_MCP89_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" },
Lines 180-192 ata_nvidia_probe(device_t dev) Link Here
180	if (!(ctlr->chip = ata_match_chip(dev, ids)))	176	if (!(ctlr->chip = ata_match_chip(dev, ids)))
181	return ENXIO;	177	return ENXIO;
182		178
		179	if ((ctlr->chip->cfg1 & NVAHCI) &&
		180	pci_get_subclass(dev) != PCIS_STORAGE_IDE)
		181	return (ENXIO);
		182
183	ata_set_desc(dev);	183	ata_set_desc(dev);
184	if ((ctlr->chip->cfg1 & NVAHCI) &&	184	ctlr->chipinit = ata_nvidia_chipinit;
185	((force_ahci == 1 && (ctlr->chip->cfg1 & NVNOFORCE) == 0) \|\|
186	pci_get_subclass(dev) != PCIS_STORAGE_IDE))
187	ctlr->chipinit = ata_ahci_chipinit;
188	else
189	ctlr->chipinit = ata_nvidia_chipinit;
190	return (BUS_PROBE_LOW_PRIORITY);	185	return (BUS_PROBE_LOW_PRIORITY);
191	}	186	}
192		187
Lines 351-354 ata_nvidia_setmode(device_t dev, int target, int m Link Here
351	}	346	}
352		347
353	ATA_DECLARE_DRIVER(ata_nvidia);	348	ATA_DECLARE_DRIVER(ata_nvidia);
354	MODULE_DEPEND(ata_nvidia, ata_ahci, 1, 1, 1);

Lines 59-79 static int ata_sii_ch_detach(device_t dev); Link Here

(-)sys/dev/ata/chipsets/ata-siliconimage.c (-559 lines)
59	static int ata_sii_status(device_t dev);	59	static int ata_sii_status(device_t dev);
60	static void ata_sii_reset(device_t dev);	60	static void ata_sii_reset(device_t dev);
61	static int ata_sii_setmode(device_t dev, int target, int mode);	61	static int ata_sii_setmode(device_t dev, int target, int mode);
62	static int ata_siiprb_ch_attach(device_t dev);
63	static int ata_siiprb_ch_detach(device_t dev);
64	static int ata_siiprb_status(device_t dev);
65	static int ata_siiprb_begin_transaction(struct ata_request *request);
66	static int ata_siiprb_end_transaction(struct ata_request *request);
67	static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result);
68	static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result);
69	static u_int32_t ata_siiprb_softreset(device_t dev, int port);
70	static void ata_siiprb_reset(device_t dev);
71	static void ata_siiprb_dmasetprd(void xsc, bus_dma_segment_t segs, int nsegs, int error);
72	static void ata_siiprb_dmainit(device_t dev);
73		62
74	/* misc defines */	63	/* misc defines */
75	#define SII_MEMIO 1	64	#define SII_MEMIO 1
76	#define SII_PRBIO 2
77	#define SII_INTR 0x01	65	#define SII_INTR 0x01
78	#define SII_SETCLK 0x02	66	#define SII_SETCLK 0x02
79	#define SII_BUG 0x04	67	#define SII_BUG 0x04
Lines 94-103 ata_sii_probe(device_t dev) Link Here
94	{ ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" },	82	{ ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" },
95	{ ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },	83	{ ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
96	{ ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },	84	{ ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
97	{ ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" },
98	{ ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
99	{ ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
100	{ ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
101	{ ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" },	85	{ ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" },
102	{ ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" },	86	{ ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" },
103	{ ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" },	87	{ ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" },
Lines 125-168 ata_sii_chipinit(device_t dev) Link Here
125	return ENXIO;	109	return ENXIO;
126		110
127	switch (ctlr->chip->cfg1) {	111	switch (ctlr->chip->cfg1) {
128	case SII_PRBIO:
129	ctlr->r_type1 = SYS_RES_MEMORY;
130	ctlr->r_rid1 = PCIR_BAR(0);
131	if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
132	&ctlr->r_rid1, RF_ACTIVE)))
133	return ENXIO;
134
135	ctlr->r_rid2 = PCIR_BAR(2);
136	ctlr->r_type2 = SYS_RES_MEMORY;
137	if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
138	&ctlr->r_rid2, RF_ACTIVE))){
139	bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
140	return ENXIO;
141	}
142	#ifdef __sparc64__
143	if (!bus_space_map(rman_get_bustag(ctlr->r_res2),
144	rman_get_bushandle(ctlr->r_res2), rman_get_size(ctlr->r_res2),
145	BUS_SPACE_MAP_LINEAR, NULL)) {
146	bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,
147	ctlr->r_res1);
148	bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2,
149	ctlr->r_res2);
150	return (ENXIO);
151	}
152	#endif
153	ctlr->ch_attach = ata_siiprb_ch_attach;
154	ctlr->ch_detach = ata_siiprb_ch_detach;
155	ctlr->reset = ata_siiprb_reset;
156	ctlr->setmode = ata_sata_setmode;
157	ctlr->getrev = ata_sata_getrev;
158	ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
159
160	/* reset controller */
161	ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
162	DELAY(10000);
163	ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
164	break;
165
166	case SII_MEMIO:	112	case SII_MEMIO:
167	ctlr->r_type2 = SYS_RES_MEMORY;	113	ctlr->r_type2 = SYS_RES_MEMORY;
168	ctlr->r_rid2 = PCIR_BAR(5);	114	ctlr->r_rid2 = PCIR_BAR(5);
Lines 446-954 ata_sii_setmode(device_t dev, int target, int mode Link Here
446	return (mode);	392	return (mode);
447	}	393	}
448		394
449	struct ata_siiprb_dma_prdentry {
450	u_int64_t addr;
451	u_int32_t count;
452	u_int32_t control;
453	} __packed;
454
455	#define ATA_SIIPRB_DMA_ENTRIES 129
456	struct ata_siiprb_ata_command {
457	struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
458	} __packed;
459
460	struct ata_siiprb_atapi_command {
461	u_int8_t ccb[16];
462	struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
463	} __packed;
464
465	struct ata_siiprb_command {
466	u_int16_t control;
467	u_int16_t protocol_override;
468	u_int32_t transfer_count;
469	u_int8_t fis[24];
470	union {
471	struct ata_siiprb_ata_command ata;
472	struct ata_siiprb_atapi_command atapi;
473	} u;
474	} __packed;
475
476	static int
477	ata_siiprb_ch_attach(device_t dev)
478	{
479	struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
480	struct ata_channel *ch = device_get_softc(dev);
481	int offset = ch->unit * 0x2000;
482
483	ata_siiprb_dmainit(dev);
484
485	/* set the SATA resources */
486	ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
487	ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
488	ch->r_io[ATA_SERROR].res = ctlr->r_res2;
489	ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
490	ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
491	ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
492	ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
493	ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
494
495	ch->hw.status = ata_siiprb_status;
496	ch->hw.begin_transaction = ata_siiprb_begin_transaction;
497	ch->hw.end_transaction = ata_siiprb_end_transaction;
498	ch->hw.command = NULL; /* not used here */
499	ch->hw.softreset = ata_siiprb_softreset;
500	ch->hw.pm_read = ata_siiprb_pm_read;
501	ch->hw.pm_write = ata_siiprb_pm_write;
502	ch->flags \|= ATA_NO_SLAVE;
503	ch->flags \|= ATA_SATA;
504	return 0;
505	}
506
507	static int
508	ata_siiprb_ch_detach(device_t dev)
509	{
510	struct ata_channel *ch = device_get_softc(dev);
511
512	if (ch->dma.work_tag && ch->dma.work_map)
513	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
514	BUS_DMASYNC_POSTWRITE);
515	ata_dmafini(dev);
516	return 0;
517	}
518
519	static int
520	ata_siiprb_status(device_t dev)
521	{
522	struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
523	struct ata_channel *ch = device_get_softc(dev);
524	u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
525	int offset = ch->unit * 0x2000;
526
527	if (action & (1 << ch->unit)) {
528	u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
529
530	/* do we have any PHY events ? */
531	ata_sata_phy_check_events(dev, -1);
532
533	/* clear interrupt(s) */
534	ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
535
536	/* do we have any device action ? */
537	return (istatus & 0x00000003);
538	}
539	return 0;
540	}
541
542	static int
543	ata_siiprb_begin_transaction(struct ata_request *request)
544	{
545	struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
546	struct ata_channel *ch = device_get_softc(request->parent);
547	struct ata_siiprb_command *prb;
548	struct ata_siiprb_dma_prdentry *prd;
549	int offset = ch->unit * 0x2000;
550	u_int64_t prb_bus;
551
552	/* SOS XXX */
553	if (request->u.ata.command == ATA_DEVICE_RESET) {
554	request->result = 0;
555	return ATA_OP_FINISHED;
556	}
557
558	/* get a piece of the workspace for this request */
559	prb = (struct ata_siiprb_command *)ch->dma.work;
560
561	/* clear the prb structure */
562	bzero(prb, sizeof(struct ata_siiprb_command));
563
564	/* setup the FIS for this request */
565	if (!ata_request2fis_h2d(request, &prb->fis[0])) {
566	device_printf(request->parent, "setting up SATA FIS failed\n");
567	request->result = EIO;
568	return ATA_OP_FINISHED;
569	}
570
571	/* setup transfer type */
572	if (request->flags & ATA_R_ATAPI) {
573	bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
574	if (request->flags & ATA_R_ATAPI16)
575	ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
576	else
577	ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
578	if (request->flags & ATA_R_READ)
579	prb->control = htole16(0x0010);
580	if (request->flags & ATA_R_WRITE)
581	prb->control = htole16(0x0020);
582	prd = &prb->u.atapi.prd[0];
583	}
584	else
585	prd = &prb->u.ata.prd[0];
586
587	/* if request moves data setup and load SG list */
588	if (request->flags & (ATA_R_READ \| ATA_R_WRITE)) {
589	if (ch->dma.load(request, prd, NULL)) {
590	device_printf(request->parent, "setting up DMA failed\n");
591	request->result = EIO;
592	return ATA_OP_FINISHED;
593	}
594	}
595
596	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
597
598	/* activate the prb */
599	prb_bus = ch->dma.work_bus;
600	ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
601	ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32);
602
603	/* start the timeout */
604	callout_reset(&request->callout, request->timeout * hz,
605	(timeout_t*)ata_timeout, request);
606	return ATA_OP_CONTINUES;
607	}
608
609	static int
610	ata_siiprb_end_transaction(struct ata_request *request)
611	{
612	struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
613	struct ata_channel *ch = device_get_softc(request->parent);
614	struct ata_siiprb_command *prb;
615	int offset = ch->unit * 0x2000;
616	int error, timeout;
617
618	/* kill the timeout */
619	callout_stop(&request->callout);
620
621	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
622
623	prb = (struct ata_siiprb_command *)
624	((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
625
626	/* any controller errors flagged ? */
627	if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
628	if (bootverbose)
629	printf("ata_siiprb_end_transaction %s error=%08x\n",
630	ata_cmd2str(request), error);
631
632	/* if device error status get details */
633	if (error == 1 \|\| error == 2) {
634	request->status = prb->fis[2];
635	if (request->status & ATA_S_ERROR)
636	request->error = prb->fis[3];
637	}
638
639	/* SOS XXX handle other controller errors here */
640
641	/* initialize port */
642	ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
643
644	/* poll for port ready */
645	for (timeout = 0; timeout < 1000; timeout++) {
646	DELAY(1000);
647	if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
648	break;
649	}
650	if (bootverbose) {
651	if (timeout >= 1000)
652	device_printf(ch->dev, "port initialize timeout\n");
653	else
654	device_printf(ch->dev, "port initialize time=%dms\n", timeout);
655	}
656	}
657
658	/* Read back registers to the request struct. */
659	if ((request->flags & ATA_R_ATAPI) == 0 &&
660	((request->status & ATA_S_ERROR) \|\|
661	(request->flags & (ATA_R_CONTROL \| ATA_R_NEEDRESULT)))) {
662	request->u.ata.count = prb->fis[12] \| ((u_int16_t)prb->fis[13] << 8);
663	request->u.ata.lba = prb->fis[4] \| ((u_int64_t)prb->fis[5] << 8) \|
664	((u_int64_t)prb->fis[6] << 16);
665	if (request->flags & ATA_R_48BIT)
666	request->u.ata.lba \|= ((u_int64_t)prb->fis[8] << 24) \|
667	((u_int64_t)prb->fis[9] << 32) \|
668	((u_int64_t)prb->fis[10] << 40);
669	else
670	request->u.ata.lba \|= ((u_int64_t)(prb->fis[7] & 0x0f) << 24);
671	}
672
673	/* update progress */
674	if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
675	if (request->flags & ATA_R_READ)
676	request->donecount = le32toh(prb->transfer_count);
677	else
678	request->donecount = request->bytecount;
679	}
680
681	/* release SG list etc */
682	ch->dma.unload(request);
683
684	return ATA_OP_FINISHED;
685	}
686
687	static int
688	ata_siiprb_issue_cmd(device_t dev)
689	{
690	struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
691	struct ata_channel *ch = device_get_softc(dev);
692	u_int64_t prb_bus = ch->dma.work_bus;
693	u_int32_t status;
694	int offset = ch->unit * 0x2000;
695	int timeout;
696
697	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
698
699	/* issue command to chip */
700	ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
701	ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32);
702
703	/* poll for command finished */
704	for (timeout = 0; timeout < 10000; timeout++) {
705	DELAY(1000);
706	if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
707	break;
708	}
709
710	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
711
712	// SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000);
713	ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff);
714
715	if (timeout >= 1000)
716	return EIO;
717
718	if (bootverbose)
719	device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n",
720	timeout, status);
721	return 0;
722	}
723
724	static int
725	ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result)
726	{
727	struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
728	struct ata_channel *ch = device_get_softc(dev);
729	struct ata_siiprb_command prb = (struct ata_siiprb_command )ch->dma.work;
730	int offset = ch->unit * 0x2000;
731
732	if (port < 0) {
733	*result = ATA_IDX_INL(ch, reg);
734	return (0);
735	}
736	if (port < ATA_PM) {
737	switch (reg) {
738	case ATA_SSTATUS:
739	reg = 0;
740	break;
741	case ATA_SERROR:
742	reg = 1;
743	break;
744	case ATA_SCONTROL:
745	reg = 2;
746	break;
747	default:
748	return (EINVAL);
749	}
750	}
751	bzero(prb, sizeof(struct ata_siiprb_command));
752	prb->fis[0] = 0x27; /* host to device */
753	prb->fis[1] = 0x8f; /* command FIS to PM port */
754	prb->fis[2] = ATA_READ_PM;
755	prb->fis[3] = reg;
756	prb->fis[7] = port;
757	if (ata_siiprb_issue_cmd(dev)) {
758	device_printf(dev, "error reading PM port\n");
759	return EIO;
760	}
761	prb = (struct ata_siiprb_command *)
762	((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
763	*result = prb->fis[12]\|(prb->fis[4]<<8)\|(prb->fis[5]<<16)\|(prb->fis[6]<<24);
764	return 0;
765	}
766
767	static int
768	ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value)
769	{
770	struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
771	struct ata_channel *ch = device_get_softc(dev);
772	struct ata_siiprb_command prb = (struct ata_siiprb_command )ch->dma.work;
773	int offset = ch->unit * 0x2000;
774
775	if (port < 0) {
776	ATA_IDX_OUTL(ch, reg, value);
777	return (0);
778	}
779	if (port < ATA_PM) {
780	switch (reg) {
781	case ATA_SSTATUS:
782	reg = 0;
783	break;
784	case ATA_SERROR:
785	reg = 1;
786	break;
787	case ATA_SCONTROL:
788	reg = 2;
789	break;
790	default:
791	return (EINVAL);
792	}
793	}
794	bzero(prb, sizeof(struct ata_siiprb_command));
795	prb->fis[0] = 0x27; /* host to device */
796	prb->fis[1] = 0x8f; /* command FIS to PM port */
797	prb->fis[2] = ATA_WRITE_PM;
798	prb->fis[3] = reg;
799	prb->fis[7] = port;
800	prb->fis[12] = value & 0xff;
801	prb->fis[4] = (value >> 8) & 0xff;
802	prb->fis[5] = (value >> 16) & 0xff;
803	prb->fis[6] = (value >> 24) & 0xff;
804	if (ata_siiprb_issue_cmd(dev)) {
805	device_printf(dev, "error writing PM port\n");
806	return ATA_E_ABORT;
807	}
808	prb = (struct ata_siiprb_command *)
809	((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
810	return prb->fis[3];
811	}
812
813	static u_int32_t
814	ata_siiprb_softreset(device_t dev, int port)
815	{
816	struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
817	struct ata_channel *ch = device_get_softc(dev);
818	struct ata_siiprb_command prb = (struct ata_siiprb_command )ch->dma.work;
819	u_int32_t signature;
820	int offset = ch->unit * 0x2000;
821
822	/* setup the workspace for a soft reset command */
823	bzero(prb, sizeof(struct ata_siiprb_command));
824	prb->control = htole16(0x0080);
825	prb->fis[1] = port & 0x0f;
826
827	/* issue soft reset */
828	if (ata_siiprb_issue_cmd(dev))
829	return -1;
830
831	ata_udelay(150000);
832
833	/* get possible signature */
834	prb = (struct ata_siiprb_command *)
835	((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
836	signature=prb->fis[12]\|(prb->fis[4]<<8)\|(prb->fis[5]<<16)\|(prb->fis[6]<<24);
837
838	/* clear error bits/interrupt */
839	ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);
840
841	return signature;
842	}
843
844	static void
845	ata_siiprb_reset(device_t dev)
846	{
847	struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
848	struct ata_channel *ch = device_get_softc(dev);
849	int offset = ch->unit * 0x2000;
850	u_int32_t status, signature;
851	int timeout;
852
853	/* disable interrupts */
854	ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff);
855
856	/* reset channel HW */
857	ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
858	DELAY(1000);
859	ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
860	DELAY(10000);
861
862	/* poll for channel ready */
863	for (timeout = 0; timeout < 1000; timeout++) {
864	if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
865	break;
866	DELAY(1000);
867	}
868
869	if (bootverbose) {
870	if (timeout >= 1000)
871	device_printf(dev, "channel HW reset timeout\n");
872	else
873	device_printf(dev, "channel HW reset time=%dms\n", timeout);
874	}
875
876	/* reset phy */
877	if (!ata_sata_phy_reset(dev, -1, 1)) {
878	if (bootverbose)
879	device_printf(dev, "phy reset found no device\n");
880	ch->devices = 0;
881	goto finish;
882	}
883
884	/* issue soft reset */
885	signature = ata_siiprb_softreset(dev, ATA_PM);
886	if (bootverbose)
887	device_printf(dev, "SIGNATURE=%08x\n", signature);
888
889	/* figure out whats there */
890	switch (signature >> 16) {
891	case 0x0000:
892	ch->devices = ATA_ATA_MASTER;
893	break;
894	case 0x9669:
895	ch->devices = ATA_PORTMULTIPLIER;
896	ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */
897	//SOS XXX need to clear all PM status and interrupts!!!!
898	ata_pm_identify(dev);
899	break;
900	case 0xeb14:
901	ch->devices = ATA_ATAPI_MASTER;
902	break;
903	default:
904	ch->devices = 0;
905	}
906	if (bootverbose)
907	device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices);
908
909	finish:
910	/* clear interrupt(s) */
911	ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
912
913	/* require explicit interrupt ack */
914	ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
915
916	/* 64bit mode */
917	ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
918
919	/* enable interrupts wanted */
920	ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
921	}
922
923	static void
924	ata_siiprb_dmasetprd(void xsc, bus_dma_segment_t segs, int nsegs, int error)
925	{
926	struct ata_dmasetprd_args *args = xsc;
927	struct ata_siiprb_dma_prdentry *prd = args->dmatab;
928	int i;
929
930	if ((args->error = error))
931	return;
932
933	for (i = 0; i < nsegs; i++) {
934	prd[i].addr = htole64(segs[i].ds_addr);
935	prd[i].count = htole32(segs[i].ds_len);
936	}
937	prd[i - 1].control = htole32(ATA_DMA_EOT);
938	KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n"));
939	args->nsegs = nsegs;
940	}
941
942	static void
943	ata_siiprb_dmainit(device_t dev)
944	{
945	struct ata_channel *ch = device_get_softc(dev);
946
947	/* note start and stop are not used here */
948	ch->dma.setprd = ata_siiprb_dmasetprd;
949	ch->dma.max_address = BUS_SPACE_MAXADDR;
950	ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE;
951	ata_dmainit(dev);
952	}
953
954	ATA_DECLARE_DRIVER(ata_sii);	395	ATA_DECLARE_DRIVER(ata_sii);

Lines 78-84 static int ata_via_sata_status(device_t dev); Link Here

(-)sys/dev/ata/chipsets/ata-via.c (-8 lines)
78	#define VIACLK 0x01	78	#define VIACLK 0x01
79	#define VIABUG 0x02	79	#define VIABUG 0x02
80	#define VIABAR 0x04	80	#define VIABAR 0x04
81	#define VIAAHCI 0x08
82	#define VIASATA 0x10	81	#define VIASATA 0x10
83		82
84	/*	83	/*
Lines 120-126 ata_via_probe(device_t dev) Link Here
120	{ ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" },	119	{ ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" },
121	{ ATA_VIA8237_5372, 0x00, 7, 0x00, ATA_SA300, "8237" },	120	{ ATA_VIA8237_5372, 0x00, 7, 0x00, ATA_SA300, "8237" },
122	{ ATA_VIA8237_7372, 0x00, 7, 0x00, ATA_SA300, "8237" },	121	{ ATA_VIA8237_7372, 0x00, 7, 0x00, ATA_SA300, "8237" },
123	{ ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" },
124	{ 0, 0, 0, 0, 0, 0 }};	122	{ 0, 0, 0, 0, 0, 0 }};
125		123
126	if (pci_get_vendor(dev) != ATA_VIA_ID)	124	if (pci_get_vendor(dev) != ATA_VIA_ID)
Lines 152-162 ata_via_chipinit(device_t dev) Link Here
152	if (ata_setup_interrupt(dev, ata_generic_intr))	150	if (ata_setup_interrupt(dev, ata_generic_intr))
153	return ENXIO;	151	return ENXIO;
154		152
155	/* AHCI SATA */
156	if (ctlr->chip->cfg2 & VIAAHCI) {
157	if (ata_ahci_chipinit(dev) != ENXIO)
158	return (0);
159	}
160	/* 2 SATA with "SATA registers" at PCI config space + PATA on secondary */	153	/* 2 SATA with "SATA registers" at PCI config space + PATA on secondary */
161	if (ctlr->chip->cfg2 & VIASATA) {	154	if (ctlr->chip->cfg2 & VIASATA) {
162	ctlr->ch_attach = ata_via_sata_ch_attach;	155	ctlr->ch_attach = ata_via_sata_ch_attach;
Lines 554-557 ata_via_sata_status(device_t dev) Link Here
554	}	547	}
555		548
556	ATA_DECLARE_DRIVER(ata_via);	549	ATA_DECLARE_DRIVER(ata_via);
557	MODULE_DEPEND(ata_via, ata_ahci, 1, 1, 1);