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Lines 36-41
__FBSDID("$FreeBSD$");
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#include <sys/malloc.h> |
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#include <sys/malloc.h> |
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#include <sys/module.h> |
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#include <sys/module.h> |
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#include <sys/linker.h> |
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#include <sys/linker.h> |
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#include <sys/nv.h> |
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#include <sys/fcntl.h> |
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#include <sys/fcntl.h> |
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#include <sys/conf.h> |
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#include <sys/conf.h> |
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#include <sys/kernel.h> |
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#include <sys/kernel.h> |
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Lines 61-66
__FBSDID("$FreeBSD$");
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#include <dev/pci/pcireg.h> |
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#include <dev/pci/pcireg.h> |
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#include <dev/pci/pcivar.h> |
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#include <dev/pci/pcivar.h> |
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#include <dev/pci/pci_private.h> |
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#include <dev/pci/pci_private.h> |
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#include <dev/pci/pci_iov_private.h> |
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#include <dev/usb/controller/xhcireg.h> |
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#include <dev/usb/controller/xhcireg.h> |
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#include <dev/usb/controller/ehcireg.h> |
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#include <dev/usb/controller/ehcireg.h> |
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Lines 74-79
__FBSDID("$FreeBSD$");
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(((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ |
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(((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ |
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((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) |
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((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) |
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#define PCIR_IS_IOV(cfg, reg) \ |
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(((cfg)->iov != NULL) && \ |
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((reg) >= (cfg)->iov->iov_pos + PCIR_SRIOV_BAR(0)) && \ |
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((reg) <= (cfg)->iov->iov_pos + PCIR_SRIOV_BAR(PCIR_MAX_BAR_0))) |
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static int pci_has_quirk(uint32_t devid, int quirk); |
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static int pci_has_quirk(uint32_t devid, int quirk); |
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static pci_addr_t pci_mapbase(uint64_t mapreg); |
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static pci_addr_t pci_mapbase(uint64_t mapreg); |
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static const char *pci_maptype(uint64_t mapreg); |
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static const char *pci_maptype(uint64_t mapreg); |
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Lines 2597-2603
pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp,
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struct pci_devinfo *dinfo; |
2604 |
struct pci_devinfo *dinfo; |
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pci_addr_t map, testval; |
2605 |
pci_addr_t map, testval; |
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int ln2range; |
2606 |
int ln2range; |
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uint16_t cmd; |
2607 |
uint32_t restore_reg; |
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2608 |
uint16_t cmd, mask; |
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2609 |
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| 2602 |
/* |
2610 |
/* |
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* The device ROM BAR is special. It is always a 32-bit |
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* The device ROM BAR is special. It is always a 32-bit |
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Lines 2627-2635
pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp,
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* determining the BAR's length since we will be placing it in |
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* determining the BAR's length since we will be placing it in |
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* a weird state. |
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* a weird state. |
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*/ |
2637 |
*/ |
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cmd = pci_read_config(dev, PCIR_COMMAND, 2); |
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#ifdef PCI_IOV |
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pci_write_config(dev, PCIR_COMMAND, |
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if (PCIR_IS_IOV(&dinfo->cfg, reg)) { |
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cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); |
2640 |
restore_reg = dinfo->cfg.iov->iov_pos + PCIR_SRIOV_CTL; |
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2641 |
mask = PCIM_SRIOV_VF_MSE; |
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} else |
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#endif |
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{ |
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restore_reg = PCIR_COMMAND; |
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mask = PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN; |
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} |
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cmd = pci_read_config(dev, restore_reg, 2); |
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pci_write_config(dev, restore_reg, cmd & ~mask, 2); |
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2650 |
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/* |
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/* |
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* Determine the BAR's length by writing all 1's. The bottom |
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* Determine the BAR's length by writing all 1's. The bottom |
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Lines 2651-2657
pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp,
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pci_write_config(dev, reg, map, 4); |
2668 |
pci_write_config(dev, reg, map, 4); |
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if (ln2range == 64) |
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if (ln2range == 64) |
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pci_write_config(dev, reg + 4, map >> 32, 4); |
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pci_write_config(dev, reg + 4, map >> 32, 4); |
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pci_write_config(dev, PCIR_COMMAND, cmd, 2); |
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pci_write_config(dev, restore_reg, cmd, 2); |
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2672 |
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*mapp = map; |
2673 |
*mapp = map; |
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*testvalp = testval; |
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*testvalp = testval; |