View | Details | Raw Unified | Return to bug 202517
Collapse All | Expand All

(-)sys/dev/pci/pci.c (-5 / +22 lines)
Lines 36-41 __FBSDID("$FreeBSD$"); Link Here
36
#include <sys/malloc.h>
36
#include <sys/malloc.h>
37
#include <sys/module.h>
37
#include <sys/module.h>
38
#include <sys/linker.h>
38
#include <sys/linker.h>
39
#include <sys/nv.h>
39
#include <sys/fcntl.h>
40
#include <sys/fcntl.h>
40
#include <sys/conf.h>
41
#include <sys/conf.h>
41
#include <sys/kernel.h>
42
#include <sys/kernel.h>
Lines 61-66 __FBSDID("$FreeBSD$"); Link Here
61
#include <dev/pci/pcireg.h>
62
#include <dev/pci/pcireg.h>
62
#include <dev/pci/pcivar.h>
63
#include <dev/pci/pcivar.h>
63
#include <dev/pci/pci_private.h>
64
#include <dev/pci/pci_private.h>
65
#include <dev/pci/pci_iov_private.h>
64
66
65
#include <dev/usb/controller/xhcireg.h>
67
#include <dev/usb/controller/xhcireg.h>
66
#include <dev/usb/controller/ehcireg.h>
68
#include <dev/usb/controller/ehcireg.h>
Lines 74-79 __FBSDID("$FreeBSD$"); Link Here
74
	(((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) ||	\
76
	(((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) ||	\
75
	 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
77
	 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
76
78
79
#define PCIR_IS_IOV(cfg, reg)						\
80
	(((cfg)->iov != NULL) &&					\
81
	 ((reg) >= (cfg)->iov->iov_pos + PCIR_SRIOV_BAR(0)) &&		\
82
	 ((reg) <= (cfg)->iov->iov_pos + PCIR_SRIOV_BAR(PCIR_MAX_BAR_0)))
83
77
static int		pci_has_quirk(uint32_t devid, int quirk);
84
static int		pci_has_quirk(uint32_t devid, int quirk);
78
static pci_addr_t	pci_mapbase(uint64_t mapreg);
85
static pci_addr_t	pci_mapbase(uint64_t mapreg);
79
static const char	*pci_maptype(uint64_t mapreg);
86
static const char	*pci_maptype(uint64_t mapreg);
Lines 2597-2603 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, Link Here
2597
	struct pci_devinfo *dinfo;
2604
	struct pci_devinfo *dinfo;
2598
	pci_addr_t map, testval;
2605
	pci_addr_t map, testval;
2599
	int ln2range;
2606
	int ln2range;
2600
	uint16_t cmd;
2607
	uint32_t restore_reg;
2608
	uint16_t cmd, mask;
2601
2609
2602
	/*
2610
	/*
2603
	 * The device ROM BAR is special.  It is always a 32-bit
2611
	 * The device ROM BAR is special.  It is always a 32-bit
Lines 2627-2635 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, Link Here
2627
	 * determining the BAR's length since we will be placing it in
2635
	 * determining the BAR's length since we will be placing it in
2628
	 * a weird state.
2636
	 * a weird state.
2629
	 */
2637
	 */
2630
	cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2638
#ifdef PCI_IOV
2631
	pci_write_config(dev, PCIR_COMMAND,
2639
	if (PCIR_IS_IOV(&dinfo->cfg, reg)) {
2632
	    cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
2640
	    restore_reg = dinfo->cfg.iov->iov_pos + PCIR_SRIOV_CTL;
2641
	    mask = PCIM_SRIOV_VF_MSE;
2642
	} else
2643
#endif
2644
	{
2645
	    restore_reg = PCIR_COMMAND;
2646
	    mask = PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN;
2647
	}
2648
	cmd = pci_read_config(dev, restore_reg, 2);
2649
	pci_write_config(dev, restore_reg, cmd & ~mask, 2);
2633
2650
2634
	/*
2651
	/*
2635
	 * Determine the BAR's length by writing all 1's.  The bottom
2652
	 * Determine the BAR's length by writing all 1's.  The bottom
Lines 2651-2657 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, Link Here
2651
	pci_write_config(dev, reg, map, 4);
2668
	pci_write_config(dev, reg, map, 4);
2652
	if (ln2range == 64)
2669
	if (ln2range == 64)
2653
		pci_write_config(dev, reg + 4, map >> 32, 4);
2670
		pci_write_config(dev, reg + 4, map >> 32, 4);
2654
	pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2671
	pci_write_config(dev, restore_reg, cmd, 2);
2655
2672
2656
	*mapp = map;
2673
	*mapp = map;
2657
	*testvalp = testval;
2674
	*testvalp = testval;

Return to bug 202517