TEST_TARGET=	fulltest

--- freebsd/map-k8.c.orig	2016-01-26 16:59:11 UTC

+++ freebsd/map-k8.c

@@ -27,95 +27,95 @@

 Native_Event_LabelDescription_t K8Processor_info[] =

 {

-	{ "k8-bu-cpu-clk-unhalted", "Count the number of clock cycles when the CPU is not in the HLT or STPCLCK states" },

-	{ "k8-bu-fill-request-l2-miss", "Count fill requests that missed in the L2 cache."},

-	{ "k8-bu-internal-l2-request", "Count internally generated requests to the L2 cache." },

-	{ "k8-dc-access", "Count data cache accesses including microcode scratchpad accesses."},

-	{ "k8-dc-copyback", "Count data cache copyback operations."},

-	{ "k8-dc-dcache-accesses-by-locks", "Count data cache accesses by lock instructions." },

-	{ "k8-dc-dispatched-prefetch-instructions", "Count the number of dispatched prefetch instructions." },

-	{ "k8-dc-l1-dtlb-miss-and-l2-dtlb-hit", "Count L1 DTLB misses that are L2 DTLB hits." },

-	{ "k8-dc-l1-dtlb-miss-and-l2-dtlb-miss", "Count L1 DTLB misses that are also misses in the L2 DTLB." },

-	{ "k8-dc-microarchitectural-early-cancel-of-an-access", "Count microarchitectural early cancels of data cache accesses." },

-	{ "k8-dc-microarchitectural-late-cancel-of-an-access", "Count microarchitectural late cancels of data cache accesses." },

-	{ "k8-dc-misaligned-data-reference", "Count misaligned data references." },

-	{ "k8-dc-miss", "Count data cache misses."},

-	{ "k8-dc-one-bit-ecc-error", "Count one bit ECC errors found by the scrubber." },

-	{ "k8-dc-refill-from-l2", "Count data cache refills from L2 cache." },

-	{ "k8-dc-refill-from-system", "Count data cache refills from system memory." },

-	{ "k8-fp-dispatched-fpu-ops", "Count the number of dispatched FPU ops." },

-	{ "k8-fp-cycles-with-no-fpu-ops-retired", "Count cycles when no FPU ops were retired." },

-	{ "k8-fp-dispatched-fpu-fast-flag-ops", "Count dispatched FPU ops that use the fast flag interface." },

-	{ "k8-fr-decoder-empty", "Count cycles when there was nothing to dispatch." },

-	{ "k8-fr-dispatch-stalls", "Count all dispatch stalls." },

-	{ "k8-fr-dispatch-stall-for-segment-load", "Count dispatch stalls for segment loads." },

-	{ "k8-fr-dispatch-stall-for-serialization", "Count dispatch stalls for serialization." },

-	{ "k8-fr-dispatch-stall-from-branch-abort-to-retire", "Count dispatch stalls from branch abort to retiral." },

-	{ "k8-fr-dispatch-stall-when-fpu-is-full", "Count dispatch stalls when the FPU is full." },

-	{ "k8-fr-dispatch-stall-when-ls-is-full", "Count dispatch stalls when the load/store unit is full." },

-	{ "k8-fr-dispatch-stall-when-reorder-buffer-is-full", "Count dispatch stalls when the reorder buffer is full." },

-	{ "k8-fr-dispatch-stall-when-reservation-stations-are-full", "Count dispatch stalls when reservation stations are full." },

-	{ "k8-fr-dispatch-stall-when-waiting-for-all-to-be-quiet", "Count dispatch stalls when waiting for all to be quiet." },

-	{ "k8-fr-dispatch-stall-when-waiting-far-xfer-or-resync-branch-pending", "Count dispatch stalls when a far control transfer or a resync branch is pending." },

-	{ "k8-fr-fpu-exceptions", "Count FPU exceptions." },

-	{ "k8-fr-interrupts-masked-cycles", "Count cycles when interrupts were masked." },

-	{ "k8-fr-interrupts-masked-while-pending-cycles", "Count cycles while interrupts were masked while pending" },

-	{ "k8-fr-number-of-breakpoints-for-dr0", "Count the number of breakpoints for DR0." },

-	{ "k8-fr-number-of-breakpoints-for-dr1", "Count the number of breakpoints for DR1." },

-	{ "k8-fr-number-of-breakpoints-for-dr2", "Count the number of breakpoints for DR2." },

-	{ "k8-fr-number-of-breakpoints-for-dr3", "Count the number of breakpoints for DR3." },

-	{ "k8-fr-retired-branches", "Count retired branches including exceptions and interrupts." },

-	{ "k8-fr-retired-branches-mispredicted", "Count mispredicted retired branches." },

-	{ "k8-fr-retired-far-control-transfers", "Count retired far control transfers" },

-	{ "k8-fr-retired-fastpath-double-op-instructions", "Count retired fastpath double op instructions." },

-	{ "k8-fr-retired-fpu-instructions", "Count retired FPU instructions." },

-	{ "k8-fr-retired-near-returns", "Count retired near returns." },

-	{ "k8-fr-retired-near-returns-mispredicted", "Count mispredicted near returns." },

-	{ "k8-fr-retired-resyncs", "Count retired resyncs" },

-	{ "k8-fr-retired-taken-hardware-interrupts", "Count retired taken hardware interrupts."},

-	{ "k8-fr-retired-taken-branches", "Count retired taken branches." },

-	{ "k8-fr-retired-taken-branches-mispredicted", "Count retired taken branches that were mispredicted." },

-	{ "k8-fr-retired-taken-branches-mispredicted-by-addr-miscompare", "Count retired taken branches that were mispredicted only due to an address miscompare." },

-	{ "k8-fr-retired-uops", "Count retired uops." },

-	{ "k8-fr-retired-x86-instructions", "Count retired x86 instructions including exceptions and interrupts"},

-	{ "k8-ic-fetch", "Count instruction cache fetches." },

-	{ "k8-ic-instruction-fetch-stall", "Count cycles in stalls due to instruction fetch." },

-	{ "k8-ic-l1-itlb-miss-and-l2-itlb-hit", "Count L1 ITLB misses that are L2 ITLB hits." },

-	{ "k8-ic-l1-itlb-miss-and-l2-itlb-miss", "Count ITLB misses that miss in both L1 and L2 ITLBs." },

-	{ "k8-ic-microarchitectural-resync-by-snoop", "Count microarchitectural resyncs caused by snoops." },

-	{ "k8-ic-miss", "Count instruction cache misses." },

-	{ "k8-ic-refill-from-l2", "Count instruction cache refills from L2 cache." },

-	{ "k8-ic-refill-from-system", "Count instruction cache refills from system memory." },

-	{ "k8-ic-return-stack-hits", "Count hits to the return stack." },

-	{ "k8-ic-return-stack-overflow", "Count overflows of the return stack." },

-	{ "k8-ls-buffer2-full", "Count load/store buffer2 full events." },

-	{ "k8-ls-locked-operation", "Count locked operations." },

-	{ "k8-ls-microarchitectural-late-cancel", "Count microarchitectural late cancels of operations in the load/store unit" },

-	{ "k8-ls-microarchitectural-resync-by-self-modifying-code", "Count microarchitectural resyncs caused by self-modifying code." },

-	{ "k8-ls-microarchitectural-resync-by-snoop", "Count microarchitectural resyncs caused by snoops." },

-	{ "k8-ls-retired-cflush-instructions", "Count retired CFLUSH instructions." },

-	{ "k8-ls-retired-cpuid-instructions", "Count retired CPUID instructions." },

-	{ "k8-ls-segment-register-load", "Count segment register loads." },

-	{ "k8-nb-memory-controller-bypass-saturation", "Count memory controller bypass counter saturation events." },

-	{ "k8-nb-memory-controller-dram-slots-missed", "Count memory controller DRAM command slots missed (in MemClks)." },

-	{ "k8-nb-memory-controller-page-access-event", "Count memory controller page access events." },

-	{ "k8-nb-memory-controller-page-table-overflow", "Count memory control page table overflow events." },

-	{ "k8-nb-probe-result", "Count probe events." },

-	{ "k8-nb-sized-commands", "Count sized commands issued." },

-	{ "k8-nb-memory-controller-turnaround", "Count memory control turnaround events." },

-	{ "k8-nb-ht-bus0-bandwidth", "Count events on the HyperTransport(tm) bus #0" },

-	{ "k8-nb-ht-bus1-bandwidth", "Count events on the HyperTransport(tm) bus #1" },

-	{ "k8-nb-ht-bus2-bandwidth", "Count events on the HyperTransport(tm) bus #2" },

+	{ "BU_CPU_CLK_UNHALTED", "Count the number of clock cycles when the CPU is not in the HLT or STPCLCK states" },

+	{ "BU_FILL_REQUEST_L2_MISS", "Count fill requests that missed in the L2 cache."},

+	{ "BU_INTERNAL_L2_REQUEST", "Count internally generated requests to the L2 cache." },

+	{ "DC_ACCESS", "Count data cache accesses including microcode scratchpad accesses."},

+	{ "DC_COPYBACK", "Count data cache copyback operations."},

+	{ "DC_DCACHE_ACCESSES_BY_LOCKS", "Count data cache accesses by lock instructions." },

+	{ "DC_DISPATCHED_PREFETCH_INSTRUCTIONS", "Count the number of dispatched prefetch instructions." },

+	{ "DC_L1_DTLB_MISS_AND_L2_DTLB_HIT", "Count L1 DTLB misses that are L2 DTLB hits." },

+	{ "DC_L1_DTLB_MISS_AND_L2_DTLB_MISS", "Count L1 DTLB misses that are also misses in the L2 DTLB." },

+	{ "DC_MICROARCHITECTURAL_EARLY_CANCEL", "Count microarchitectural early cancels of data cache accesses." },

+	{ "DC_MICROARCHITECTURAL_LATE_CANCEL", "Count microarchitectural late cancels of data cache accesses." },

+	{ "DC_MISALIGNED_DATA_REFERENCE", "Count misaligned data references." },

+	{ "DC_MISS", "Count data cache misses."},

+	{ "DC_ONE_BIT_ECC_ERROR", "Count one bit ECC errors found by the scrubber." },

+	{ "DC_REFILL_FROM_L2", "Count data cache refills from L2 cache." },

+	{ "DC_REFILL_FROM_SYSTEM", "Count data cache refills from system memory." },

+	{ "FP_DISPATCHED_FPU_OPS", "Count the number of dispatched FPU ops." },

+	{ "FP_CYCLES_WITH_NO_FPU_OPS_RETIRED", "Count cycles when no FPU ops were retired." },

+	{ "FP_DISPATCHED_FPU_FAST_FLAG_OPS", "Count dispatched FPU ops that use the fast flag interface." },

+	{ "FR_DECODER_EMPTY", "Count cycles when there was nothing to dispatch." },

+	{ "FR_DISPATCH_STALLS", "Count all dispatch stalls." },

+	{ "FR_DISPATCH_STALL_FOR_SEGMENT_LOAD", "Count dispatch stalls for segment loads." },

+	{ "FR_DISPATCH_STALL_FOR_SERIALIZATION", "Count dispatch stalls for serialization." },

+	{ "FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE", "Count dispatch stalls from branch abort to retiral." },

+	{ "FR_DISPATCH_STALL_WHEN_FPU_IS_FULL", "Count dispatch stalls when the FPU is full." },

+	{ "FR_DISPATCH_STALL_WHEN_LS_IS_FULL", "Count dispatch stalls when the load/store unit is full." },

+	{ "FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL", "Count dispatch stalls when the reorder buffer is full." },

+	{ "FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL", "Count dispatch stalls when reservation stations are full." },

+	{ "FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET", "Count dispatch stalls when waiting for all to be quiet." },

+	{ "FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING", "Count dispatch stalls when a far control transfer or a resync branch is pending." },

+	{ "FR_FPU_EXCEPTIONS", "Count FPU exceptions." },

+	{ "FR_INTERRUPTS_MASKED_CYCLES", "Count cycles when interrupts were masked." },

+	{ "FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES", "Count cycles while interrupts were masked while pending" },

+	{ "FR_NUMBER_OF_BREAKPOINTS_FOR_DR0", "Count the number of breakpoints for DR0." },

+	{ "FR_NUMBER_OF_BREAKPOINTS_FOR_DR1", "Count the number of breakpoints for DR1." },

+	{ "FR_NUMBER_OF_BREAKPOINTS_FOR_DR2", "Count the number of breakpoints for DR2." },

+	{ "FR_NUMBER_OF_BREAKPOINTS_FOR_DR3", "Count the number of breakpoints for DR3." },

+	{ "FR_RETIRED_BRANCHES", "Count retired branches including exceptions and interrupts." },

+	{ "FR_RETIRED_BRANCHES_MISPREDICTED", "Count mispredicted retired branches." },

+	{ "FR_RETIRED_FAR_CONTROL_TRANSFERS", "Count retired far control transfers" },

+	{ "FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS", "Count retired fastpath double op instructions." },

+	{ "FR_RETIRED_FPU_INSTRUCTIONS", "Count retired FPU instructions." },

+	{ "FR_RETIRED_NEAR_RETURNS", "Count retired near returns." },

+	{ "FR_RETIRED_NEAR_RETURNS_MISPREDICTED", "Count mispredicted near returns." },

+	{ "FR_RETIRED_RESYNCS", "Count retired resyncs" },

+	{ "FR_TAKEN_HARDWARE_INTERRUPTS", "Count retired taken hardware interrupts."},

+	{ "FR_RETIRED_TAKEN_BRANCHES", "Count retired taken branches." },

+	{ "FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED", "Count retired taken branches that were mispredicted." },

+	{ "FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE", "Count retired taken branches that were mispredicted only due to an address miscompare." },

+	{ "FR_RETIRED_UOPS", "Count retired uops." },

+	{ "FR_RETIRED_X86_INSTRUCTIONS", "Count retired x86 instructions including exceptions and interrupts"},

+	{ "IC_FETCH", "Count instruction cache fetches." },

+	{ "IC_INSTRUCTION_FETCH_STALL", "Count cycles in stalls due to instruction fetch." },

+	{ "IC_L1_ITLB_MISS_AND_L2_ITLB_HIT", "Count L1 ITLB misses that are L2 ITLB hits." },

+	{ "IC_L1_ITLB_MISS_AND_L2_ITLB_MISS", "Count ITLB misses that miss in both L1 and L2 ITLBs." },

+	{ "IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP", "Count microarchitectural resyncs caused by snoops." },

+	{ "IC_MISS", "Count instruction cache misses." },

+	{ "IC_REFILL_FROM_L2", "Count instruction cache refills from L2 cache." },

+	{ "IC_REFILL_FROM_SYSTEM", "Count instruction cache refills from system memory." },

+	{ "IC_RETURN_STACK_HIT", "Count hits to the return stack." },

+	{ "IC_RETURN_STACK_OVERFLOW", "Count overflows of the return stack." },

+	{ "LS_BUFFER2_FULL", "Count load/store buffer2 full events." },

+	{ "LS_LOCKED_OPERATION", "Count locked operations." },

+	{ "LS_MICROARCHITECTURAL_LATE_CANCEL", "Count microarchitectural late cancels of operations in the load/store unit" },

+	{ "LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE", "Count microarchitectural resyncs caused by self_modifying code." },

+	{ "LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP", "Count microarchitectural resyncs caused by snoops." },

+	{ "LS_RETIRED_CFLUSH_INSTRUCTIONS", "Count retired CFLUSH instructions." },

+	{ "LS_RETIRED_CPUID_INSTRUCTIONS", "Count retired CPUID instructions." },

+	{ "LS_SEGMENT_REGISTER_LOAD", "Count segment register loads." },

+	{ "NB_MEMORY_CONTROLLER_BYPASS_SATURATION", "Count memory controller bypass counter saturation events." },

+	{ "NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED", "Count memory controller DRAM command slots missed (in MemClks)." },

+	{ "NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT", "Count memory controller page access events." },

+	{ "NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW", "Count memory control page table overflow events." },

+	{ "NB_PROBE_RESULT", "Count probe events." },

+	{ "NB_SIZED_COMMANDS", "Count sized commands issued." },

+	{ "NB_MEMORY_CONTROLLER_TURNAROUND", "Count memory control turnaround events." },

+	{ "NB_HT_BUS0_BANDWIDTH", "Count events on the HyperTransport(tm) bus #0" },

+	{ "NB_HT_BUS1_BANDWIDTH", "Count events on the HyperTransport(tm) bus #1" },

+	{ "NB_HT_BUS2_BANDWIDTH", "Count events on the HyperTransport(tm) bus #2" },

 	/* Special counters with some masks activated */

-	{ "k8-dc-refill-from-l2,mask=+modified,+owner,+exclusive,+shared", "Count data cache refills from L2 cache (in MOES state)." },

-	{ "k8-dc-refill-from-l2,mask=+owner,+exclusive,+shared", "Count data cache refills from L2 cache (in OES state)." },

-	{ "k8-dc-refill-from-l2,mask=+modified", "Count data cache refills from L2 cache (in M state)." },

-	{ "k8-dc-refill-from-system,mask=+modified,+owner,+exclusive,+shared", "Count data cache refills from system memory (in MOES state)." },

-	{ "k8-dc-refill-from-system,mask=+owner,+exclusive,+shared", "Count data cache refills from system memory (in OES state)." },

-	{ "k8-dc-refill-from-system,mask=+modified", "Count data cache refills from system memory (in M state)." },

-	{ "k8-fp-dispatched-fpu-ops,mask=+multiply-pipe-junk-ops", "Count the number of dispatched FPU multiplies." },

-	{ "k8-fp-dispatched-fpu-ops,mask=+add-pipe-junk-ops", "Count the number of dispatched FPU adds." },

-	{ "k8-fp-dispatched-fpu-ops,mask=+multiply-pipe-junk-ops,+add-pipe-junk-ops", "Count the number of dispatched FPU adds and multiplies." },

+	{ "DC_REFILL_FROM_L2_MOES,mask=+modified,+owner,+exclusive,+shared", "Count data cache refills from L2 cache (in MOES state)." },

+	{ "DC_REFILL_FROM_L2_OES,mask=+owner,+exclusive,+shared", "Count data cache refills from L2 cache (in OES state)." },

+	{ "DC_REFILL_FROM_L2_M,mask=+modified", "Count data cache refills from L2 cache (in M state)." },

+	{ "DC_REFILL_FROM_SYSTEM_MOES,mask=+modified,+owner,+exclusive,+shared", "Count data cache refills from system memory (in MOES state)." },

+	{ "DC_REFILL_FROM_SYSTEM_OES,mask=+owner,+exclusive,+shared", "Count data cache refills from system memory (in OES state)." },

+	{ "DC_REFILL_FROM_SYSTEM_M,mask=+modified", "Count data cache refills from system memory (in M state)." },

+	{ "FP_DISPATCHED_FPU_MULS,mask=+multiply_pipe_junk_ops", "Count the number of dispatched FPU multiplies." },

+	{ "FP_DISPATCHED_FPU_ADDS,mask=+add_pipe_junk_ops", "Count the number of dispatched FPU adds." },

+	{ "FP_DISPATCHED_FPU_ADDS_AND_MULS,mask=+multiply_pipe_junk_ops,+add_pipe_junk_ops", "Count the number of dispatched FPU adds and multiplies." },

 	{ NULL, NULL }

 };

--- freebsd_events.csv.orig	2016-01-26 16:59:11 UTC

+++ freebsd_events.csv

@@ -110,8 +110,8 @@ PRESET,PAPI_BR_INS,NOT_DERIVED,FR_RETIRE

 PRESET,PAPI_RES_STL,NOT_DERIVED,FR_DISPATCH_STALLS

 PRESET,PAPI_TOT_CYC,NOT_DERIVED,BU_CPU_CLK_UNHALTED

 PRESET,PAPI_TOT_INS,NOT_DERIVED,FR_RETIRED_X86_INSTRUCTIONS

-PRESET,PAPI_STL_ICY,FR_DECODER_EMPTY

-PRESET,PAPI_HW_INT,NOT_DERIVED,FR_RETIRED_TAKEN_HARDWARE_INTERRUPTS

+PRESET,PAPI_STL_ICY,NOT_DERIVED,FR_DECODER_EMPTY

+PRESET,PAPI_HW_INT,NOT_DERIVED,FR_TAKEN_HARDWARE_INTERRUPTS

 PRESET,PAPI_BR_TKN,NOT_DERIVED,FR_RETIRED_TAKEN_BRANCHES

 PRESET,PAPI_BR_MSP,NOT_DERIVED,FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED

 PRESET,PAPI_TLB_DM,NOT_DERIVED,DC_L1_DTLB_MISS_AND_L2_DTLB_MISS

@@ -123,26 +123,31 @@ PRESET,PAPI_L1_TCA,DERIVED_ADD,DC_ACCESS

 PRESET,PAPI_L1_ICR,NOT_DERIVED,IC_FETCH

 PRESET,PAPI_L2_ICH,NOT_DERIVED,IC_REFILL_FROM_L2

 PRESET,PAPI_L2_DCH,NOT_DERIVED,DC_REFILL_FROM_L2

-PRESET,PAPI_L2_DCM,NOT_DERIVED,DC_REFILL_FROM_SYSTEM_MOES

-PRESET,PAPI_L2_DCA,DERIVED_ADD,DC_REFILL_FROM_SYSTEM_MOES, DC_REFILL_FROM_L2_MOES

+#PRESET,PAPI_L2_DCM,NOT_DERIVED,DC_REFILL_FROM_SYSTEM_MOES

+#PRESET,PAPI_L2_DCA,DERIVED_ADD,DC_REFILL_FROM_SYSTEM_MOES, DC_REFILL_FROM_L2_MOES

 PRESET,PAPI_L2_ICM,NOT_DERIVED,IC_REFILL_FROM_SYSTEM

-PRESET,PAPI_L2_DCR,NOT_DERIVED,DC_REFILL_FROM_L2_OES

-PRESET,PAPI_L2_DCW,NOT_DERIVED,DC_REFILL_FROM_L2_M

-PRESET,PAPI_L2_DCH,NOT_DERIVED,DC_REFILL_FROM_L2_MOES

-PRESET,PAPI_L1_LDM,NOT_DERIVED,DC_REFILL_FROM_L2_OES

-PRESET,PAPI_L1_STM,NOT_DERIVED,DC_REFILL_FROM_L2_M

-PRESET,PAPI_L2_LDM,NOT_DERIVED,DC_REFILL_FROM_SYSTEM_OES

-PRESET,PAPI_L2_STM,NOT_DERIVED,DC_REFILL_FROM_SYSTEM_M

-PRESET,PAPI_L1_DCM,DERIVED_ADD,DC_REFILL_FROM_SYSTEM_MOES, DC_REFILL_FROM_L2_MOES

+#PRESET,PAPI_L2_DCR,NOT_DERIVED,DC_REFILL_FROM_L2_OES

+#PRESET,PAPI_L2_DCW,NOT_DERIVED,DC_REFILL_FROM_L2_M

+#PRESET,PAPI_L2_DCH,NOT_DERIVED,DC_REFILL_FROM_L2_MOES

+#PRESET,PAPI_L1_LDM,NOT_DERIVED,DC_REFILL_FROM_L2_OES

+#PRESET,PAPI_L1_STM,NOT_DERIVED,DC_REFILL_FROM_L2_M

+#PRESET,PAPI_L2_LDM,NOT_DERIVED,DC_REFILL_FROM_SYSTEM_OES

+#PRESET,PAPI_L2_STM,NOT_DERIVED,DC_REFILL_FROM_SYSTEM_M

+#PRESET,PAPI_L1_DCM,DERIVED_ADD,DC_REFILL_FROM_SYSTEM_MOES, DC_REFILL_FROM_L2_MOES

 PRESET,PAPI_L1_ICM,DERIVED_ADD,IC_REFILL_FROM_L2, IC_REFILL_FROM_SYSTEM

-PRESET,PAPI_L1_TCM,DERIVED_ADD,DC_REFILL_FROM_SYSTEM_MOES,DC_REFILL_FROM_L2_MOES,IC_REFILL_FROM_SYSTEM,IC_REFILL_FROM_L2

-PRESET,PAPI_L2_TCM,DERIVED_ADD,DC_REFILL_FROM_SYSTEM_MOES,IC_REFILL_FROM_SYSTEM

+#PRESET,PAPI_L1_TCM,DERIVED_ADD,DC_REFILL_FROM_SYSTEM_MOES,DC_REFILL_FROM_L2_MOES,IC_REFILL_FROM_SYSTEM,IC_REFILL_FROM_L2

+#PRESET,PAPI_L2_TCM,DERIVED_ADD,DC_REFILL_FROM_SYSTEM_MOES,IC_REFILL_FROM_SYSTEM

+PRESET,PAPI_L1_TCM,DERIVED_ADD,DC_REFILL_FROM_SYSTEM,DC_REFILL_FROM_L2,IC_REFILL_FROM_SYSTEM,IC_REFILL_FROM_L2

+PRESET,PAPI_L2_TCM,DERIVED_ADD,DC_REFILL_FROM_SYSTEM,IC_REFILL_FROM_SYSTEM

 PRESET,PAPI_L2_ICA,DERIVED_ADD,IC_REFILL_FROM_SYSTEM,IC_REFILL_FROM_L2

-PRESET,PAPI_L2_TCH,DERIVED_ADD,IC_REFILL_FROM_L2,DC_REFILL_FROM_L2_MOES

-PRESET,PAPI_L2_TCA,DERIVED_ADD,IC_REFILL_FROM_L2,IC_REFILL_FROM_SYSTEM,DC_REFILL_FROM_L2_MOES,DC_REFILL_FROM_SYSTEM_MOES

-PRESET,PAPI_FML_INS,NOT_DERIVED,FP_DISPATCHED_FPU_MULS

-PRESET,PAPI_FAD_INS,NOT_DERIVED,FP_DISPATCHED_FPU_ADDS

-PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_DISPATCHED_FPU_ADDS_AND_MULS

+#PRESET,PAPI_L2_TCH,DERIVED_ADD,IC_REFILL_FROM_L2,DC_REFILL_FROM_L2_MOES

+#PRESET,PAPI_L2_TCA,DERIVED_ADD,IC_REFILL_FROM_L2,IC_REFILL_FROM_SYSTEM,DC_REFILL_FROM_L2_MOES,DC_REFILL_FROM_SYSTEM_MOES

+PRESET,PAPI_L2_TCH,DERIVED_ADD,IC_REFILL_FROM_L2,DC_REFILL_FROM_L2

+PRESET,PAPI_L2_TCA,DERIVED_ADD,IC_REFILL_FROM_L2,IC_REFILL_FROM_SYSTEM,DC_REFILL_FROM_L2,DC_REFILL_FROM_SYSTEM

+#PRESET,PAPI_FML_INS,NOT_DERIVED,FP_DISPATCHED_FPU_MULS

+#PRESET,PAPI_FAD_INS,NOT_DERIVED,FP_DISPATCHED_FPU_ADDS

+#PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_DISPATCHED_FPU_ADDS_AND_MULS

+PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_DISPATCHED_FPU_OPS

 PRESET,PAPI_FP_INS,NOT_DERIVED,FR_RETIRED_FPU_INSTRUCTIONS

 PRESET,PAPI_FPU_IDL,NOT_DERIVED,FP_CYCLES_WITH_NO_FPU_OPS_RETIRED

%%DATADIR%%/ctests/mpifirst

%%DATADIR%%/ftests/Makefile

%%DATADIR%%/ftests/accum

%%DATADIR%%/ftests/accum.F

%%DATADIR%%/ftests/avail

%%DATADIR%%/ftests/avail.F

%%DATADIR%%/ftests/case1

%%DATADIR%%/ftests/case1.F

%%DATADIR%%/ftests/case2

%%DATADIR%%/ftests/case2.F

%%DATADIR%%/ftests/clockres

%%DATADIR%%/ftests/clockres.F

%%DATADIR%%/ftests/cost

%%DATADIR%%/ftests/cost.F

%%DATADIR%%/ftests/description

%%DATADIR%%/ftests/description.F

%%DATADIR%%/ftests/eventname

%%DATADIR%%/ftests/eventname.F

%%DATADIR%%/ftests/fdmemtest

%%DATADIR%%/ftests/fdmemtest.F

%%DATADIR%%/ftests/first

%%DATADIR%%/ftests/first.F

%%DATADIR%%/ftests/flops

%%DATADIR%%/ftests/flops.F

%%DATADIR%%/ftests/fmatrixlowpapi

%%DATADIR%%/ftests/fmatrixlowpapi.F

%%DATADIR%%/ftests/fmatrixpapi

%%DATADIR%%/ftests/fmatrixpapi.F

%%DATADIR%%/ftests/fmatrixpapi2

%%DATADIR%%/ftests/fmatrixpapi2.F

%%DATADIR%%/ftests/fmultiplex1

%%DATADIR%%/ftests/fmultiplex1.F

%%DATADIR%%/ftests/fmultiplex2

%%DATADIR%%/ftests/fmultiplex2.F

%%DATADIR%%/ftests/highlevel

%%DATADIR%%/ftests/highlevel.F

%%DATADIR%%/ftests/johnmay2

%%DATADIR%%/ftests/johnmay2.F

%%DATADIR%%/ftests/nineth.F

%%DATADIR%%/ftests/second

%%DATADIR%%/ftests/second.F

%%DATADIR%%/ftests/strtest

%%DATADIR%%/ftests/strtest.F

%%DATADIR%%/ftests/tenth

%%DATADIR%%/ftests/tenth.F

%%DATADIR%%/ftests/zero

%%DATADIR%%/ftests/zero.F

%%DATADIR%%/ftests/zeronamed

%%DATADIR%%/ftests/zeronamed.F