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Lines 93-109
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| 93 |
#define DWC_OTG_PC2UDEV(pc) \ |
93 |
#define DWC_OTG_PC2UDEV(pc) \ |
| 94 |
(USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) |
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(USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) |
| 95 |
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| 96 |
#define DWC_OTG_MSK_GINT_ENABLED \ |
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(GINTMSK_ENUMDONEMSK | \ |
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GINTMSK_USBRSTMSK | \ |
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GINTMSK_USBSUSPMSK | \ |
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GINTMSK_IEPINTMSK | \ |
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GINTMSK_SESSREQINTMSK | \ |
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GINTMSK_RXFLVLMSK | \ |
| 103 |
GINTMSK_HCHINTMSK | \ |
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GINTMSK_OTGINTMSK | \ |
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GINTMSK_PRTINTMSK) |
| 106 |
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| 107 |
#define DWC_OTG_MSK_GINT_THREAD_IRQ \ |
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#define DWC_OTG_MSK_GINT_THREAD_IRQ \ |
| 108 |
(GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ |
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(GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ |
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GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ |
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GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ |
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Lines 376-381
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| 376 |
/* enable all host channel interrupts */ |
365 |
/* enable all host channel interrupts */ |
| 377 |
DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, |
366 |
DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, |
| 378 |
(1U << sc->sc_host_ch_max) - 1U); |
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(1U << sc->sc_host_ch_max) - 1U); |
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368 |
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| 369 |
/* enable proper host channel interrupts */ |
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sc->sc_irq_mask |= GINTMSK_HCHINTMSK; |
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sc->sc_irq_mask &= ~GINTMSK_IEPINTMSK; |
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DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); |
| 379 |
} |
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} |
| 380 |
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| 381 |
if (mode == DWC_MODE_DEVICE) { |
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if (mode == DWC_MODE_DEVICE) { |
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Lines 436-441
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| 436 |
pf->usb.max_in_frame_size, |
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pf->usb.max_in_frame_size, |
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pf->usb.max_out_frame_size); |
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pf->usb.max_out_frame_size); |
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} |
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} |
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433 |
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| 434 |
/* enable proper device channel interrupts */ |
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sc->sc_irq_mask &= ~GINTMSK_HCHINTMSK; |
| 436 |
sc->sc_irq_mask |= GINTMSK_IEPINTMSK; |
| 437 |
DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); |
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} |
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} |
| 440 |
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| 441 |
/* reset RX FIFO */ |
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/* reset RX FIFO */ |
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Lines 2870-2879
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| 2870 |
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2869 |
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| 2871 |
for (x = 0; x != sc->sc_dev_in_ep_max; x++) { |
2870 |
for (x = 0; x != sc->sc_dev_in_ep_max; x++) { |
| 2872 |
temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); |
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temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); |
| 2873 |
if (temp & DIEPMSK_XFERCOMPLMSK) { |
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/* |
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DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), |
2873 |
* NOTE: Need to clear all interrupt bits, |
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DIEPMSK_XFERCOMPLMSK); |
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* because some appears to be unmaskable and |
| 2876 |
} |
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* can cause an interrupt loop: |
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2876 |
*/ |
| 2877 |
if (temp != 0) |
| 2878 |
DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), temp); |
| 2877 |
} |
2879 |
} |
| 2878 |
} |
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} |
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Lines 3980-3986
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| 3980 |
} |
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} |
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3983 |
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| 3982 |
/* enable interrupts */ |
3984 |
/* enable interrupts */ |
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sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; |
3985 |
sc->sc_irq_mask |= DWC_OTG_MSK_GINT_THREAD_IRQ; |
| 3984 |
DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); |
3986 |
DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); |
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3987 |
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| 3986 |
if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { |
3988 |
if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { |