Attachment #17378 for bug #31559

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 	case 0x71a18086:
 		return ("Intel 82443GX host to AGP bridge");

	case 0x1a218086:
 		return ("Intel 82840 host to AGP bridge");

	case 0x1a308086:
 		return ("Intel 82845 host to AGP bridge");

	case 0x25308086:
 		return ("Intel 82850 host to AGP bridge");

	case 0x25318086:
 		return ("Intel 82860 host to AGP bridge");
	};

	if (pci_get_vendor(dev) == 0x8086)

{
	struct agp_intel_softc *sc = device_get_softc(dev);
	struct agp_gatt *gatt;
	u_int32_t type = pci_get_devid(dev);
	int error;

	error = agp_generic_attach(dev);

	pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
	
	/* Enable things, clear errors etc. */
	switch (type) {
	case 0x1a218086: /* i840 */
	case 0x25308086: /* i850 */
	case 0x25318086: /* i860 */
		pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
		pci_write_config(dev, AGP_INTEL_MCHCFG,
				 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
				  | (1 << 9)), 2);
		break;

	case 0x1a308086: /* i845 */
		pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
		pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
				 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
				  | (1 << 1)), 1);
		break;

	default: /* Intel Generic (maybe) */
		pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
		pci_write_config(dev, AGP_INTEL_NBXCFG,
				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
				  & ~(1 << 10)) | (1 << 9), 4);
	}

	switch (type) {
	case 0x1a218086: /* i840 */
		pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
		break;

	case 0x1a308086: /* i845 */
	case 0x25308086: /* i850 */
	case 0x25318086: /* i860 */
		pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x001c, 2);
		break;

	default: /* Intel Generic (maybe) */
		pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
	}

	return 0;
}

agp_intel_detach(device_t dev)
{
	struct agp_intel_softc *sc = device_get_softc(dev);
	u_int32_t type = pci_get_devid(dev);
	int error;

	error = agp_generic_detach(dev);
	if (error)
		return error;

	switch (type) {
	case 0x1a218086: /* i840 */
	case 0x25308086: /* i850 */
	case 0x25318086: /* i860 */
		printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
				(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
				& ~(1 << 9)));
		pci_write_config(dev, AGP_INTEL_MCHCFG,
				(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
				& ~(1 << 9)), 2);

	case 0x1a308086: /* i845 */
		printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
				(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
				& ~(1 << 1)));
		pci_write_config(dev, AGP_INTEL_MCHCFG,
				(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
				& ~(1 << 1)), 1);

	default: /* Intel Generic (maybe) */
		printf("%s: set NBXCFG to %x\n", __FUNCTION__,
				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
				  & ~(1 << 9)));
		pci_write_config(dev, AGP_INTEL_NBXCFG,
				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
				  & ~(1 << 9)), 4);
	}
	pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
	AGP_SET_APERTURE(dev, sc->initial_aperture);
	agp_free_gatt(sc->gatt);

Lines 57-62 Link Here

(-)sys/pci/agpreg.h (+7 lines)
57	#define AGP_INTEL_ATTBASE 0xb8	57	#define AGP_INTEL_ATTBASE 0xb8
58		58
59	/*	59	/*
		60	* Config offsets for Intel i840/i845/i850/i860 AGP chipsets.
		61	*/
		62	#define AGP_INTEL_MCHCFG 0x50
		63	#define AGP_INTEL_I845_MCHCFG 0x51
		64	#define AGP_INTEL_I8XX_ERRSTS 0xc8
		65
		66	/*
60	* Config offsets for VIA AGP chipsets.	67	* Config offsets for VIA AGP chipsets.
61	*/	68	*/
62	#define AGP_VIA_GARTCTRL 0x80	69	#define AGP_VIA_GARTCTRL 0x80

Return to bug 31559

Lines 74-79 Link Here

(-)sys/pci/agp_intel.c (-11 / +79 lines)
74		74
75	case 0x71a18086:	75	case 0x71a18086:
76	return ("Intel 82443GX host to AGP bridge");	76	return ("Intel 82443GX host to AGP bridge");
		77
		78	case 0x1a218086:
		79	return ("Intel 82840 host to AGP bridge");
		80
		81	case 0x1a308086:
		82	return ("Intel 82845 host to AGP bridge");
		83
		84	case 0x25308086:
		85	return ("Intel 82850 host to AGP bridge");
		86
		87	case 0x25318086:
		88	return ("Intel 82860 host to AGP bridge");
77	};	89	};
78		90
79	if (pci_get_vendor(dev) == 0x8086)	91	if (pci_get_vendor(dev) == 0x8086)
Lines 102-107 Link Here
102	{	114	{
103	struct agp_intel_softc *sc = device_get_softc(dev);	115	struct agp_intel_softc *sc = device_get_softc(dev);
104	struct agp_gatt *gatt;	116	struct agp_gatt *gatt;
		117	u_int32_t type = pci_get_devid(dev);
105	int error;	118	int error;
106		119
107	error = agp_generic_attach(dev);	120	error = agp_generic_attach(dev);
Lines 130-140 Link Here
130	pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);	143	pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
131		144
132	/* Enable things, clear errors etc. */	145	/* Enable things, clear errors etc. */
133	pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);	146	switch (type) {
134	pci_write_config(dev, AGP_INTEL_NBXCFG,	147	case 0x1a218086: /* i840 */
135	(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)	148	case 0x25308086: /* i850 */
136	& ~(1 << 10)) \| (1 << 9), 4);	149	case 0x25318086: /* i860 */
137	pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);	150	pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
		151	pci_write_config(dev, AGP_INTEL_MCHCFG,
		152	(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
		153	\| (1 << 9)), 2);
		154	break;
		155
		156	case 0x1a308086: /* i845 */
		157	pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
		158	pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
		159	(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
		160	\| (1 << 1)), 1);
		161	break;
		162
		163	default: /* Intel Generic (maybe) */
		164	pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
		165	pci_write_config(dev, AGP_INTEL_NBXCFG,
		166	(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
		167	& ~(1 << 10)) \| (1 << 9), 4);
		168	}
		169
		170	switch (type) {
		171	case 0x1a218086: /* i840 */
		172	pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
		173	break;
		174
		175	case 0x1a308086: /* i845 */
		176	case 0x25308086: /* i850 */
		177	case 0x25318086: /* i860 */
		178	pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x001c, 2);
		179	break;
		180
		181	default: /* Intel Generic (maybe) */
		182	pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
		183	}
138		184
139	return 0;	185	return 0;
140	}	186	}
Lines 143-160 Link Here
143	agp_intel_detach(device_t dev)	189	agp_intel_detach(device_t dev)
144	{	190	{
145	struct agp_intel_softc *sc = device_get_softc(dev);	191	struct agp_intel_softc *sc = device_get_softc(dev);
		192	u_int32_t type = pci_get_devid(dev);
146	int error;	193	int error;
147		194
148	error = agp_generic_detach(dev);	195	error = agp_generic_detach(dev);
149	if (error)	196	if (error)
150	return error;	197	return error;
151		198
152	printf("%s: set NBXCFG to %x\n", __FUNCTION__,	199	switch (type) {
153	(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)	200	case 0x1a218086: /* i840 */
154	& ~(1 << 9)));	201	case 0x25308086: /* i850 */
155	pci_write_config(dev, AGP_INTEL_NBXCFG,	202	case 0x25318086: /* i860 */
156	(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)	203	printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
157	& ~(1 << 9)), 4);	204	(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
		205	& ~(1 << 9)));
		206	pci_write_config(dev, AGP_INTEL_MCHCFG,
		207	(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
		208	& ~(1 << 9)), 2);
		209
		210	case 0x1a308086: /* i845 */
		211	printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
		212	(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
		213	& ~(1 << 1)));
		214	pci_write_config(dev, AGP_INTEL_MCHCFG,
		215	(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
		216	& ~(1 << 1)), 1);
		217
		218	default: /* Intel Generic (maybe) */
		219	printf("%s: set NBXCFG to %x\n", __FUNCTION__,
		220	(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
		221	& ~(1 << 9)));
		222	pci_write_config(dev, AGP_INTEL_NBXCFG,
		223	(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
		224	& ~(1 << 9)), 4);
		225	}
158	pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);	226	pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
159	AGP_SET_APERTURE(dev, sc->initial_aperture);	227	AGP_SET_APERTURE(dev, sc->initial_aperture);
160	agp_free_gatt(sc->gatt);	228	agp_free_gatt(sc->gatt);