Attachment #17538 for bug #31825

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 	case 0x71a18086:
 		return ("Intel 82443GX host to AGP bridge");

	case 0x25008086:
 		return ("Intel 82820 host to AGP bridge");

	case 0x1a218086:
 		return ("Intel 82840 host to AGP bridge");

	case 0x1a308086:
 		return ("Intel 82845 host to AGP bridge");

	case 0x25308086:
 		return ("Intel 82850 host to AGP bridge");

	case 0x25318086:
 		return ("Intel 82860 host to AGP bridge");
	};

	if (pci_get_vendor(dev) == 0x8086)

{
	struct agp_intel_softc *sc = device_get_softc(dev);
	struct agp_gatt *gatt;
	u_int32_t type = pci_get_devid(dev);
	int error;

	error = agp_generic_attach(dev);

	pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
	
	/* Enable things, clear errors etc. */
	switch (type) {
	case 0x1a218086: /* i840 */
	case 0x25308086: /* i850 */
	case 0x25318086: /* i860 */
		pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
		pci_write_config(dev, AGP_INTEL_MCHCFG,
				 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
				  | (1 << 9)), 2);
		break;

	case 0x25008086: /* i820 */
		pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
		pci_write_config(dev, AGP_INTEL_I820_RDCR,
				 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
				  | (1 << 1)), 1);
		break;

	case 0x1a308086: /* i845 */
		pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
		pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
				 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
				  | (1 << 1)), 1);
		break;

	default: /* Intel Generic (maybe) */
		pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
		pci_write_config(dev, AGP_INTEL_NBXCFG,
				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
				  & ~(1 << 10)) | (1 << 9), 4);
	}

	switch (type) {
	case 0x1a218086: /* i840 */
		pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
		break;

	case 0x25008086: /* i820 */
	case 0x1a308086: /* i845 */
	case 0x25308086: /* i850 */
	case 0x25318086: /* i860 */
		pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x001c, 2);
		break;

	default: /* Intel Generic (maybe) */
		pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
	}

	return 0;
}

agp_intel_detach(device_t dev)
{
	struct agp_intel_softc *sc = device_get_softc(dev);
	u_int32_t type = pci_get_devid(dev);
	int error;

	error = agp_generic_detach(dev);
	if (error)
		return error;

	switch (type) {
	case 0x1a218086: /* i840 */
	case 0x25308086: /* i850 */
	case 0x25318086: /* i860 */
		printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
				(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
				& ~(1 << 9)));
		pci_write_config(dev, AGP_INTEL_MCHCFG,
				(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
				& ~(1 << 9)), 2);

	case 0x25008086: /* i820 */
		printf("%s: set RDCR to %x\n", __FUNCTION__, (unsigned)
				(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
				& ~(1 << 1)));
		pci_write_config(dev, AGP_INTEL_I820_RDCR,
				(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
				& ~(1 << 1)), 1);

	case 0x1a308086: /* i845 */
		printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
				(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
				& ~(1 << 1)));
		pci_write_config(dev, AGP_INTEL_MCHCFG,
				(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
				& ~(1 << 1)), 1);

	default: /* Intel Generic (maybe) */
		printf("%s: set NBXCFG to %x\n", __FUNCTION__,
				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
				  & ~(1 << 9)));
		pci_write_config(dev, AGP_INTEL_NBXCFG,
				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
				  & ~(1 << 9)), 4);
	}
	pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
	AGP_SET_APERTURE(dev, sc->initial_aperture);
	agp_free_gatt(sc->gatt);

Lines 57-62 Link Here

(-)sys/pci/agpreg.h (+8 lines)
57	#define AGP_INTEL_ATTBASE 0xb8	57	#define AGP_INTEL_ATTBASE 0xb8
58		58
59	/*	59	/*
		60	* Config offsets for Intel i820/i840/i845/i850/i860 AGP chipsets.
		61	*/
		62	#define AGP_INTEL_MCHCFG 0x50
		63	#define AGP_INTEL_I820_RDCR 0x51
		64	#define AGP_INTEL_I845_MCHCFG 0x51
		65	#define AGP_INTEL_I8XX_ERRSTS 0xc8
		66
		67	/*
60	* Config offsets for VIA AGP chipsets.	68	* Config offsets for VIA AGP chipsets.
61	*/	69	*/
62	#define AGP_VIA_GARTCTRL 0x80	70	#define AGP_VIA_GARTCTRL 0x80

Return to bug 31825

Lines 74-79 Link Here

(-)sys/pci/agp_intel.c (-11 / +98 lines)
74		74
75	case 0x71a18086:	75	case 0x71a18086:
76	return ("Intel 82443GX host to AGP bridge");	76	return ("Intel 82443GX host to AGP bridge");
		77
		78	case 0x25008086:
		79	return ("Intel 82820 host to AGP bridge");
		80
		81	case 0x1a218086:
		82	return ("Intel 82840 host to AGP bridge");
		83
		84	case 0x1a308086:
		85	return ("Intel 82845 host to AGP bridge");
		86
		87	case 0x25308086:
		88	return ("Intel 82850 host to AGP bridge");
		89
		90	case 0x25318086:
		91	return ("Intel 82860 host to AGP bridge");
77	};	92	};
78		93
79	if (pci_get_vendor(dev) == 0x8086)	94	if (pci_get_vendor(dev) == 0x8086)
Lines 102-107 Link Here
102	{	117	{
103	struct agp_intel_softc *sc = device_get_softc(dev);	118	struct agp_intel_softc *sc = device_get_softc(dev);
104	struct agp_gatt *gatt;	119	struct agp_gatt *gatt;
		120	u_int32_t type = pci_get_devid(dev);
105	int error;	121	int error;
106		122
107	error = agp_generic_attach(dev);	123	error = agp_generic_attach(dev);
Lines 130-140 Link Here
130	pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);	146	pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
131		147
132	/* Enable things, clear errors etc. */	148	/* Enable things, clear errors etc. */
133	pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);	149	switch (type) {
134	pci_write_config(dev, AGP_INTEL_NBXCFG,	150	case 0x1a218086: /* i840 */
135	(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)	151	case 0x25308086: /* i850 */
136	& ~(1 << 10)) \| (1 << 9), 4);	152	case 0x25318086: /* i860 */
137	pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);	153	pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
		154	pci_write_config(dev, AGP_INTEL_MCHCFG,
		155	(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
		156	\| (1 << 9)), 2);
		157	break;
		158
		159	case 0x25008086: /* i820 */
		160	pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
		161	pci_write_config(dev, AGP_INTEL_I820_RDCR,
		162	(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
		163	\| (1 << 1)), 1);
		164	break;
		165
		166	case 0x1a308086: /* i845 */
		167	pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
		168	pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
		169	(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
		170	\| (1 << 1)), 1);
		171	break;
		172
		173	default: /* Intel Generic (maybe) */
		174	pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
		175	pci_write_config(dev, AGP_INTEL_NBXCFG,
		176	(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
		177	& ~(1 << 10)) \| (1 << 9), 4);
		178	}
		179
		180	switch (type) {
		181	case 0x1a218086: /* i840 */
		182	pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
		183	break;
		184
		185	case 0x25008086: /* i820 */
		186	case 0x1a308086: /* i845 */
		187	case 0x25308086: /* i850 */
		188	case 0x25318086: /* i860 */
		189	pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x001c, 2);
		190	break;
		191
		192	default: /* Intel Generic (maybe) */
		193	pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
		194	}
138		195
139	return 0;	196	return 0;
140	}	197	}
Lines 143-160 Link Here
143	agp_intel_detach(device_t dev)	200	agp_intel_detach(device_t dev)
144	{	201	{
145	struct agp_intel_softc *sc = device_get_softc(dev);	202	struct agp_intel_softc *sc = device_get_softc(dev);
		203	u_int32_t type = pci_get_devid(dev);
146	int error;	204	int error;
147		205
148	error = agp_generic_detach(dev);	206	error = agp_generic_detach(dev);
149	if (error)	207	if (error)
150	return error;	208	return error;
151		209
152	printf("%s: set NBXCFG to %x\n", __FUNCTION__,	210	switch (type) {
153	(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)	211	case 0x1a218086: /* i840 */
154	& ~(1 << 9)));	212	case 0x25308086: /* i850 */
155	pci_write_config(dev, AGP_INTEL_NBXCFG,	213	case 0x25318086: /* i860 */
156	(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)	214	printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
157	& ~(1 << 9)), 4);	215	(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
		216	& ~(1 << 9)));
		217	pci_write_config(dev, AGP_INTEL_MCHCFG,
		218	(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
		219	& ~(1 << 9)), 2);
		220
		221	case 0x25008086: /* i820 */
		222	printf("%s: set RDCR to %x\n", __FUNCTION__, (unsigned)
		223	(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
		224	& ~(1 << 1)));
		225	pci_write_config(dev, AGP_INTEL_I820_RDCR,
		226	(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
		227	& ~(1 << 1)), 1);
		228
		229	case 0x1a308086: /* i845 */
		230	printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
		231	(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
		232	& ~(1 << 1)));
		233	pci_write_config(dev, AGP_INTEL_MCHCFG,
		234	(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
		235	& ~(1 << 1)), 1);
		236
		237	default: /* Intel Generic (maybe) */
		238	printf("%s: set NBXCFG to %x\n", __FUNCTION__,
		239	(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
		240	& ~(1 << 9)));
		241	pci_write_config(dev, AGP_INTEL_NBXCFG,
		242	(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
		243	& ~(1 << 9)), 4);
		244	}
158	pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);	245	pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
159	AGP_SET_APERTURE(dev, sc->initial_aperture);	246	AGP_SET_APERTURE(dev, sc->initial_aperture);
160	agp_free_gatt(sc->gatt);	247	agp_free_gatt(sc->gatt);