Attachment #176126 for bug #139743




static void		pci_unmask_msix(device_t dev, u_int index);
static int		pci_msi_blacklisted(void);
static int		pci_msix_blacklisted(void);
static void		pci_fix_asus_smbus(device_t dev);
static void		pci_resume_msi(device_t dev);
static void		pci_resume_msix(device_t dev);
static int		pci_remap_intr_method(device_t bus, device_t dev,

#define	PCI_QUIRK_UNMAP_REG	4 /* Ignore PCI map register */
#define	PCI_QUIRK_DISABLE_MSIX	5 /* MSI-X doesn't work */
#define	PCI_QUIRK_MSI_INTX_BUG	6 /* PCIM_CMD_INTxDIS disables MSI */
#define	PCI_QUIRK_FIXUP_ROUTINE	7 /* PCI needs a fix to continue */
	int	arg1;
	int	arg2;
	void (*fixup_func)(device_t dev);
};

static const struct pci_quirk pci_quirks[] = {
	/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
	{ 0x71138086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
	{ 0x719b8086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
	/* As does the Serverworks OSB4 (the SMBus mapping register) */
	{ 0x02001166, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },

	/*
	 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
	 * or the CMIC-SL (AKA ServerWorks GC_LE).
	 */
	{ 0x00141166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x00171166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

	/*
	 * MSI doesn't work on earlier Intel chipsets including
	 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
	 */
	{ 0x25408086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25508086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25608086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25708086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25788086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x35808086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

	/*
	 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
	 * bridge.
	 */
	{ 0x74501022, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

	/*
	 * MSI-X allocation doesn't work properly for devices passed through
	 * by VMware up to at least ESXi 5.1.
	 */
	{ 0x079015ad, PCI_QUIRK_DISABLE_MSIX,	0,	0, NULL }, /* PCI/PCI-X */
	{ 0x07a015ad, PCI_QUIRK_DISABLE_MSIX,	0,	0, NULL }, /* PCIe */

	/*
	 * Some virtualization environments emulate an older chipset
	 * but support MSI just fine.  QEMU uses the Intel 82440.
	 */
	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM,	0,	0, NULL },

	/*
	 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus

	 * For SB600 A21 and later, firmware must set the bit to hide it.
	 * For SB700 and later, it is unused and hardcoded to zero.
	 */
	{ 0x43851002, PCI_QUIRK_UNMAP_REG,	0x14,	0, NULL },

	/*
	 * Atheros AR8161/AR8162/E2200 Ethernet controllers have a bug that
	 * MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of the
	 * command register is set.
	 */
	{ 0x10911969, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL },
	{ 0xE0911969, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL },
	{ 0x10901969, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL },

	/*
	 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't
	 * issue MSI interrupts with PCIM_CMD_INTxDIS set either.
	 */
	{ 0x166814e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5714 */
	{ 0x166914e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5714S */
	{ 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5780 */
	{ 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5780S */
	{ 0x167814e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5715 */
	{ 0x167914e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5715S */

	/*
	 * The ASUS P4B-motherboards needs a hack to enable the Intel 801SMBus
	*/
	{ 0x24408086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },
	{ 0x24C08086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },

	{ 0 }
};

		cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
}

/* asus p4b/p4pe hack */

static void
pci_fix_asus_smbus(device_t dev)
{
	int	pmccfg;

	/* read subsystem vendor-id */
	pmccfg = pci_read_config(dev, 0xF2, 2);
	printf(" [-] pmccfg: %.4x\n",pmccfg);
	if( pmccfg & 0x8 ){
		pmccfg &= ~0x8;
		pci_write_config(dev, 0xF2, pmccfg, 2);
		pmccfg = pci_read_config(dev, 0xF2, 2);
		if( pmccfg & 0x8 )
			printf("Could not enable Intel 801SMBus!\n");
		else
			printf("Enabled Intel 801SMBus\n");
	}
}

/* extract header type specific config data */

static void

			 * Skip quirked resources.
			 */
			for (q = &pci_quirks[0]; q->devid != 0; q++)
				if (q->devid == ((cfg->device << 16) | cfg->vendor)){
					if (q->type == PCI_QUIRK_MAP_REG)
						pci_add_map(bus, dev, q->arg1, rl, force, 0);
					else if (q->type == PCI_QUIRK_FIXUP_ROUTINE)
						q->fixup_func(dev);
				}
				if (q->devid == devid &&
				    q->type == PCI_QUIRK_UNMAP_REG &&
				    q->arg1 == PCIR_BAR(i))

Return to bug 139743

Lines 117-122 static void pci_mask_msix(device_t dev, Link Here

(-)sys/dev/pci/pci.c (-26 / +62 lines)
117	static void pci_unmask_msix(device_t dev, u_int index);	117	static void pci_unmask_msix(device_t dev, u_int index);
118	static int pci_msi_blacklisted(void);	118	static int pci_msi_blacklisted(void);
119	static int pci_msix_blacklisted(void);	119	static int pci_msix_blacklisted(void);
		120	static void pci_fix_asus_smbus(device_t dev);
120	static void pci_resume_msi(device_t dev);	121	static void pci_resume_msi(device_t dev);
121	static void pci_resume_msix(device_t dev);	122	static void pci_resume_msix(device_t dev);
122	static int pci_remap_intr_method(device_t bus, device_t dev,	123	static int pci_remap_intr_method(device_t bus, device_t dev,
Lines 221-274 struct pci_quirk { Link Here
221	#define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */	222	#define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */
222	#define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */	223	#define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
223	#define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */	224	#define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */
		225	#define PCI_QUIRK_FIXUP_ROUTINE 7 /* PCI needs a fix to continue */
224	int arg1;	226	int arg1;
225	int arg2;	227	int arg2;
		228	void (*fixup_func)(device_t dev);
226	};	229	};
227		230
228	static const struct pci_quirk pci_quirks[] = {	231	static const struct pci_quirk pci_quirks[] = {
229	/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */	232	/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
230	{ 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },	233	{ 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0, NULL },
231	{ 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },	234	{ 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0, NULL },
232	/* As does the Serverworks OSB4 (the SMBus mapping register) */	235	/* As does the Serverworks OSB4 (the SMBus mapping register) */
233	{ 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },	236	{ 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0, NULL },
234		237
235	/*	238	/*
236	* MSI doesn't work with the ServerWorks CNB20-HE Host Bridge	239	* MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
237	* or the CMIC-SL (AKA ServerWorks GC_LE).	240	* or the CMIC-SL (AKA ServerWorks GC_LE).
238	*/	241	*/
239	{ 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },	242	{ 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
240	{ 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },	243	{ 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
241		244
242	/*	245	/*
243	* MSI doesn't work on earlier Intel chipsets including	246	* MSI doesn't work on earlier Intel chipsets including
244	* E7500, E7501, E7505, 845, 865, 875/E7210, and 855.	247	* E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
245	*/	248	*/
246	{ 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	249	{ 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
247	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	250	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
248	{ 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	251	{ 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
249	{ 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	252	{ 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
250	{ 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	253	{ 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
251	{ 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	254	{ 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
252	{ 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	255	{ 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
253		256
254	/*	257	/*
255	* MSI doesn't work with devices behind the AMD 8131 HT-PCIX	258	* MSI doesn't work with devices behind the AMD 8131 HT-PCIX
256	* bridge.	259	* bridge.
257	*/	260	*/
258	{ 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },	261	{ 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
259		262
260	/*	263	/*
261	* MSI-X allocation doesn't work properly for devices passed through	264	* MSI-X allocation doesn't work properly for devices passed through
262	* by VMware up to at least ESXi 5.1.	265	* by VMware up to at least ESXi 5.1.
263	*/	266	*/
264	{ 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCI/PCI-X */	267	{ 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0, NULL }, /* PCI/PCI-X */
265	{ 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCIe */	268	{ 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0, NULL }, /* PCIe */
266		269
267	/*	270	/*
268	* Some virtualization environments emulate an older chipset	271	* Some virtualization environments emulate an older chipset
269	* but support MSI just fine. QEMU uses the Intel 82440.	272	* but support MSI just fine. QEMU uses the Intel 82440.
270	*/	273	*/
271	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },	274	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0, NULL },
272		275
273	/*	276	/*
274	* HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus	277	* HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus
Lines 278-304 static const struct pci_quirk pci_quirks Link Here
278	* For SB600 A21 and later, firmware must set the bit to hide it.	281	* For SB600 A21 and later, firmware must set the bit to hide it.
279	* For SB700 and later, it is unused and hardcoded to zero.	282	* For SB700 and later, it is unused and hardcoded to zero.
280	*/	283	*/
281	{ 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },	284	{ 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0, NULL },
282		285
283	/*	286	/*
284	* Atheros AR8161/AR8162/E2200 Ethernet controllers have a bug that	287	* Atheros AR8161/AR8162/E2200 Ethernet controllers have a bug that
285	* MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of the	288	* MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of the
286	* command register is set.	289	* command register is set.
287	*/	290	*/
288	{ 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	291	{ 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
289	{ 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	292	{ 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
290	{ 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	293	{ 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
291		294
292	/*	295	/*
293	* Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't	296	* Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't
294	* issue MSI interrupts with PCIM_CMD_INTxDIS set either.	297	* issue MSI interrupts with PCIM_CMD_INTxDIS set either.
295	*/	298	*/
296	{ 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */	299	{ 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5714 */
297	{ 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */	300	{ 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5714S */
298	{ 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */	301	{ 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5780 */
299	{ 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */	302	{ 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5780S */
300	{ 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */	303	{ 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5715 */
301	{ 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */	304	{ 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5715S */
		305
		306	/*
		307	* The ASUS P4B-motherboards needs a hack to enable the Intel 801SMBus
		308	*/
		309	{ 0x24408086, PCI_QUIRK_FIXUP_ROUTINE, 0, 0, &pci_fix_asus_smbus },
		310	{ 0x24C08086, PCI_QUIRK_FIXUP_ROUTINE, 0, 0, &pci_fix_asus_smbus },
302		311
303	{ 0 }	312	{ 0 }
304	};	313	};
Lines 578-583 pci_fixancient(pcicfgregs *cfg) Link Here
578	cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;	587	cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
579	}	588	}
580		589
		590	/* asus p4b/p4pe hack */
		591
		592	static void
		593	pci_fix_asus_smbus(device_t dev)
		594	{
		595	int pmccfg;
		596
		597	/* read subsystem vendor-id */
		598	pmccfg = pci_read_config(dev, 0xF2, 2);
		599	printf(" [-] pmccfg: %.4x\n",pmccfg);
		600	if( pmccfg & 0x8 ){
		601	pmccfg &= ~0x8;
		602	pci_write_config(dev, 0xF2, pmccfg, 2);
		603	pmccfg = pci_read_config(dev, 0xF2, 2);
		604	if( pmccfg & 0x8 )
		605	printf("Could not enable Intel 801SMBus!\n");
		606	else
		607	printf("Enabled Intel 801SMBus\n");
		608	}
		609	}
		610
581	/* extract header type specific config data */	611	/* extract header type specific config data */
582		612
583	static void	613	static void
Lines 3819-3824 pci_add_resources(device_t bus, device_t Link Here
3819	* Skip quirked resources.	3849	* Skip quirked resources.
3820	*/	3850	*/
3821	for (q = &pci_quirks[0]; q->devid != 0; q++)	3851	for (q = &pci_quirks[0]; q->devid != 0; q++)
		3852	if (q->devid == ((cfg->device << 16) \| cfg->vendor)){
		3853	if (q->type == PCI_QUIRK_MAP_REG)
		3854	pci_add_map(bus, dev, q->arg1, rl, force, 0);
		3855	else if (q->type == PCI_QUIRK_FIXUP_ROUTINE)
		3856	q->fixup_func(dev);
		3857	}
3822	if (q->devid == devid &&	3858	if (q->devid == devid &&
3823	q->type == PCI_QUIRK_UNMAP_REG &&	3859	q->type == PCI_QUIRK_UNMAP_REG &&
3824	q->arg1 == PCIR_BAR(i))	3860	q->arg1 == PCIR_BAR(i))