Attachment 17882 Details for Bug 32338 – diff_sis.txt

diff_sis.txt

diff_sis.txt (text/plain), 3.26 KB, created by David S Madole on 2002-01-08 01:13:19 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: David S Madole

Created: 2002-01-08 01:13:19 UTC

Size: 3.26 KB

patch

obsolete

>*** if_sisreg.h.orig	Wed Feb 21 22:17:51 2001
>--- if_sisreg.h	Thu Nov 29 19:28:35 2001
>***************
>*** 76,81 ****
>--- 76,82 ----
>  
>  /* NS DP83815 registers */
>  #define NS_CLKRUN		0x3C
>+ #define NS_SRR			0x58
>  #define NS_BMCR			0x80
>  #define NS_BMSR			0x84
>  #define NS_PHYIDR1		0x88
>***************
>*** 401,406 ****
>--- 402,408 ----
>  	struct sis_list_data	*sis_ldata;
>  	struct sis_ring_data	sis_cdata;
>  	struct callout_handle	sis_stat_ch;
>+ 	device_t		sis_dev;
>  };
>  
>  /*
>*** if_sis.c.orig	Wed Feb 21 22:17:51 2001
>--- if_sis.c	Thu Nov 29 19:41:31 2001
>***************
>*** 723,728 ****
>--- 723,730 ----
>  	unit = device_get_unit(dev);
>  	bzero(sc, sizeof(struct sis_softc));
>  
>+ 	sc->sis_dev = dev;
>+ 
>  	if (pci_get_device(dev) == SIS_DEVICEID_900)
>  		sc->sis_type = SIS_TYPE_900;
>  	if (pci_get_device(dev) == SIS_DEVICEID_7016)
>***************
>*** 1159,1166 ****
>  void sis_rxeoc(sc)
>  	struct sis_softc	*sc;
>  {
>  	sis_rxeof(sc);
>- 	sis_init(sc);
>  	return;
>  }
>  
>--- 1161,1183 ----
>  void sis_rxeoc(sc)
>  	struct sis_softc	*sc;
>  {
>+ 	int latency;
>+ 
>+ 	/*
>+ 	 * The BIOS may have initialized the maximum latency timer
>+ 	 * too low to be able to keep up with a 100Mbs stream when
>+ 	 * heavy disk or other DMA is taking place. Try to correct
>+ 	 * for this adaptively by bumping it up a little each time
>+ 	 * the receive FIFO overflows.
>+ 	 */
>+ 
>+ 	latency = pci_read_config(sc->sis_dev, PCIR_LATTIMER, 1);
>+ 	if (latency < 255) {
>+ 		if ((latency += 32) > 255) latency = 255;
>+ 		pci_write_config(sc->sis_dev, PCIR_LATTIMER, latency, 1);
>+ 	}
>+ 
>  	sis_rxeof(sc);
>  	return;
>  }
>  
>***************
>*** 1293,1305 ****
>  			sis_txeof(sc);
>  
>  		if ((status & SIS_ISR_RX_DESC_OK) ||
>! 		    (status & SIS_ISR_RX_OK))
>  			sis_rxeof(sc);
>  
>! 		if ((status & SIS_ISR_RX_ERR) ||
>! 		    (status & SIS_ISR_RX_OFLOW)) {
>  			sis_rxeoc(sc);
>- 		}
>  
>  		if (status & SIS_ISR_SYSERR) {
>  			sis_reset(sc);
>--- 1310,1321 ----
>  			sis_txeof(sc);
>  
>  		if ((status & SIS_ISR_RX_DESC_OK) ||
>! 		    (status & SIS_ISR_RX_OK) ||
>! 		    (status & SIS_ISR_RX_ERR))
>  			sis_rxeof(sc);
>  
>! 		if (status & SIS_ISR_RX_OFLOW)
>  			sis_rxeoc(sc);
>  
>  		if (status & SIS_ISR_SYSERR) {
>  			sis_reset(sc);
>***************
>*** 1562,1569 ****
>  	 * performance." Note however that at least three
>  	 * of the registers are listed as "reserved" in
>  	 * the register map, so who knows what they do.
>  	 */
>! 	if (sc->sis_type == SIS_TYPE_83815) {
>  		CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
>  		CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
>  		CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
>--- 1578,1593 ----
>  	 * performance." Note however that at least three
>  	 * of the registers are listed as "reserved" in
>  	 * the register map, so who knows what they do.
>+ 	 *
>+ 	 * An appararently later version (December 2000)
>+ 	 * has this data on page 78 and qualifies it as
>+ 	 * applying only to silicon version 203h, which
>+ 	 * is aparently a typo'd reference to version 302h
>+ 	 * as referred to on page 64.
>  	 */
>! 	if (sc->sis_type == SIS_TYPE_83815 &&
>! 	    CSR_READ_4(sc, NS_SRR) == 0x0302) {
>! 
>  		CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
>  		CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
>  		CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
>=

Actions: View

Attachments on bug 32338: 17882