Attachment #180878 for bug #217845

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Lines 1-9 Link Here

(-)lib/libc/mips/Makefile.inc (-4 lines)
1	# $NetBSD: Makefile.inc,v 1.7 2005/09/17 11:49:39 tsutsui Exp $	1	# $NetBSD: Makefile.inc,v 1.7 2005/09/17 11:49:39 tsutsui Exp $
2	# $FreeBSD$	2	# $FreeBSD$
3		3
4	.if ${MACHINE_ARCH:Mmips*hf} == ""
5	CFLAGS+=-DSOFTFLOAT
6	.endif
7
8	SRCS+= machdep_ldisd.c	4	SRCS+= machdep_ldisd.c
9	SYM_MAPS+= ${LIBC_SRCTOP}/mips/Symbol.map	5	SYM_MAPS+= ${LIBC_SRCTOP}/mips/Symbol.map




	 * In N64, FP registers F24 .. F31 are callee-saved.
	 * In O32, FP registers F20 .. F23 are callee-saved.
	 */
#ifndef __mips_soft_float
	cfc1	v0, $31				# too bad can't check if FP used
#if defined(__mips_n64) || defined(__mips_n32)
	FP_S	$f30, (_JB_FPREG_F30 * SZREG)(a0)

	FP_S	$f31, (_JB_FPREG_F31 * SZREG)(a0)
#endif
	INT_S	v0, (_JB_FPREG_FCSR * SZREG)(a0)
#endif /* ! __mips_soft_float */
	REG_EPILOGUE

	j	ra

#if defined(__mips_n32) || defined(__mips_n64)
	REG_L		gp, (_JB_REG_GP * SZREG)(a0)
#endif
#ifndef __mips_soft_float
	# get fpu status
	INT_L		v0, (_JB_FPREG_FCSR * SZREG)(a0)
	ctc1		v0, $31

	FP_L	$f29, (_JB_FPREG_F29 * SZREG)(a0)
	FP_L	$f31, (_JB_FPREG_F31 * SZREG)(a0)
#endif
#endif	/* ! __mips_soft_float */

	REG_EPILOGUE
	move	v0, a1			# get return value in 1st arg

Lines 14-20 Link Here

(-)lib/libc/mips/gen/flt_rounds.c (-2 / +2 lines)
14	#include <fenv.h>	14	#include <fenv.h>
15	#include <float.h>	15	#include <float.h>
16		16
17	#ifdef SOFTFLOAT	17	#ifdef __mips_soft_float
18	#include "softfloat-for-gcc.h"	18	#include "softfloat-for-gcc.h"
19	#include "milieu.h"	19	#include "milieu.h"
20	#include "softfloat.h"	20	#include "softfloat.h"
Lines 32-38 Link Here
32	{	32	{
33	int mode;	33	int mode;
34		34
35	#ifdef SOFTFLOAT	35	#ifdef __mips_soft_float
36	mode = __softfloat_float_rounding_mode;	36	mode = __softfloat_float_rounding_mode;
37	#else	37	#else
38	__asm __volatile("cfc1 %0,$31" : "=r" (mode));	38	__asm __volatile("cfc1 %0,$31" : "=r" (mode));




#if defined(__mips_n32) || defined(__mips_n64)
	REG_S	gp, (_JB_REG_GP * SZREG)(a0)
#endif
#ifndef __mips_soft_float
	/*
	 * From "MIPSpro N32 ABI Handbook", Table 2-1:
	 * In N32, FP registers F20, F22, F24, F26, F28, F30 are callee-saved.

	FP_S	$f29, (_JB_FPREG_F29 * SZREG)(a0)
	FP_S	$f31, (_JB_FPREG_F31 * SZREG)(a0)
#endif
#endif	/* ! __mips_soft_float */

	move	v0, zero
	jr	ra

#if defined(__mips_n32) || defined(__mips_n64)
	REG_L	gp, (_JB_REG_GP * SZREG)(a0)
#endif
#ifndef __mips_soft_float
	/*
	 * From "MIPSpro N32 ABI Handbook", Table 2-1:
	 * In N32, FP registers F20, F22, F24, F26, F28, F30 are callee-saved.

	FP_L	$f29, (_JB_FPREG_F29 * SZREG)(a0)
	FP_L	$f31, (_JB_FPREG_F31 * SZREG)(a0)
#endif
#endif	/* ! __mips_soft_float */

	move	v0, a1
	j	ra

Lines 1-8 Link Here

(-)lib/msun/mips/Makefile.inc (-4 lines)
1	# $FreeBSD$	1	# $FreeBSD$
2		2
3	.if ${MACHINE_ARCH:Mmips*hf} == ""
4	CFLAGS+=-DSOFTFLOAT
5	.endif
6
7	LDBL_PREC = 53	3	LDBL_PREC = 53
8	SYM_MAPS += ${.CURDIR}/mips/Symbol.map	4	SYM_MAPS += ${.CURDIR}/mips/Symbol.map

Lines 39-45 Link Here

(-)lib/msun/mips/fenv.c (-1 / +1 lines)
39	*/	39	*/
40	const fenv_t __fe_dfl_env = 0;	40	const fenv_t __fe_dfl_env = 0;
41		41
42	#ifdef SOFTFLOAT	42	#ifdef __mips_soft_float
43	#define __set_env(env, flags, mask, rnd) env = ((flags) \	43	#define __set_env(env, flags, mask, rnd) env = ((flags) \
44	\| (mask)<<_FPUSW_SHIFT \	44	\| (mask)<<_FPUSW_SHIFT \
45	\| (rnd) << 24)	45	\| (rnd) << 24)

Lines 39-45 Link Here

(-)lib/msun/mips/fenv.h (-6 / +10 lines)
39	typedef __uint32_t fexcept_t;	39	typedef __uint32_t fexcept_t;
40		40
41	/* Exception flags */	41	/* Exception flags */
42	#ifdef SOFTFLOAT	42	#ifdef __mips_soft_float
43	#define _FPUSW_SHIFT 16	43	#define _FPUSW_SHIFT 16
44	#define FE_INVALID 0x0001	44	#define FE_INVALID 0x0001
45	#define FE_DIVBYZERO 0x0002	45	#define FE_DIVBYZERO 0x0002
Lines 74-85 Link Here
74	#define _ENABLE_SHIFT 5	74	#define _ENABLE_SHIFT 5
75	#define _ENABLE_MASK (FE_ALL_EXCEPT << _ENABLE_SHIFT)	75	#define _ENABLE_MASK (FE_ALL_EXCEPT << _ENABLE_SHIFT)
76		76
77	#ifndef SOFTFLOAT	77	#if !defined(__mips_soft_float) && !defined(__mips_hard_float)
		78	#error compiler didnt set soft/hard float macros
		79	#endif
		80
		81	#ifndef __mips_soft_float
78	#define __cfc1(__fcsr) __asm __volatile("cfc1 %0, $31" : "=r" (__fcsr))	82	#define __cfc1(__fcsr) __asm __volatile("cfc1 %0, $31" : "=r" (__fcsr))
79	#define __ctc1(__fcsr) __asm __volatile("ctc1 %0, $31" :: "r" (__fcsr))	83	#define __ctc1(__fcsr) __asm __volatile("ctc1 %0, $31" :: "r" (__fcsr))
80	#endif	84	#endif
81		85
82	#ifdef SOFTFLOAT	86	#ifdef __mips_soft_float
83	int feclearexcept(int __excepts);	87	int feclearexcept(int __excepts);
84	int fegetexceptflag(fexcept_t *__flagp, int __excepts);	88	int fegetexceptflag(fexcept_t *__flagp, int __excepts);
85	int fesetexceptflag(const fexcept_t *__flagp, int __excepts);	89	int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
Lines 223-235 Link Here
223		227
224	return (0);	228	return (0);
225	}	229	}
226	#endif /* !SOFTFLOAT */	230	#endif /* !__mips_soft_float */
227		231
228	#if __BSD_VISIBLE	232	#if __BSD_VISIBLE
229		233
230	/* We currently provide no external definitions of the functions below. */	234	/* We currently provide no external definitions of the functions below. */
231		235
232	#ifdef SOFTFLOAT	236	#ifdef __mips_soft_float
233	int feenableexcept(int __mask);	237	int feenableexcept(int __mask);
234	int fedisableexcept(int __mask);	238	int fedisableexcept(int __mask);
235	int fegetexcept(void);	239	int fegetexcept(void);
Lines 268-274 Link Here
268	return ((fcsr & _ENABLE_MASK) >> _ENABLE_SHIFT);	272	return ((fcsr & _ENABLE_MASK) >> _ENABLE_SHIFT);
269	}	273	}
270		274
271	#endif /* !SOFTFLOAT */	275	#endif /* !__mips_soft_float */
272		276
273	#endif /* __BSD_VISIBLE */	277	#endif /* __BSD_VISIBLE */
274		278

Return to bug 217845

Lines 90-96 Link Here

(-)lib/libc/mips/gen/_setjmp.S (-4 / +4 lines)
90	* In N64, FP registers F24 .. F31 are callee-saved.	90	* In N64, FP registers F24 .. F31 are callee-saved.
91	* In O32, FP registers F20 .. F23 are callee-saved.	91	* In O32, FP registers F20 .. F23 are callee-saved.
92	*/	92	*/
93	#ifndef SOFTFLOAT	93	#ifndef __mips_soft_float
94	cfc1 v0, $31 # too bad can't check if FP used	94	cfc1 v0, $31 # too bad can't check if FP used
95	#if defined(__mips_n64) \|\| defined(__mips_n32)	95	#if defined(__mips_n64) \|\| defined(__mips_n32)
96	FP_S $f30, (_JB_FPREG_F30 * SZREG)(a0)	96	FP_S $f30, (_JB_FPREG_F30 * SZREG)(a0)
Lines 113-119 Link Here
113	FP_S $f31, (_JB_FPREG_F31 * SZREG)(a0)	113	FP_S $f31, (_JB_FPREG_F31 * SZREG)(a0)
114	#endif	114	#endif
115	INT_S v0, (_JB_FPREG_FCSR * SZREG)(a0)	115	INT_S v0, (_JB_FPREG_FCSR * SZREG)(a0)
116	#endif /* ! SOFTFLOAT */	116	#endif /* ! __mips_soft_float */
117	REG_EPILOGUE	117	REG_EPILOGUE
118		118
119	j ra	119	j ra
Lines 151-157 Link Here
151	#if defined(__mips_n32) \|\| defined(__mips_n64)	151	#if defined(__mips_n32) \|\| defined(__mips_n64)
152	REG_L gp, (_JB_REG_GP * SZREG)(a0)	152	REG_L gp, (_JB_REG_GP * SZREG)(a0)
153	#endif	153	#endif
154	#ifndef SOFTFLOAT	154	#ifndef __mips_soft_float
155	# get fpu status	155	# get fpu status
156	INT_L v0, (_JB_FPREG_FCSR * SZREG)(a0)	156	INT_L v0, (_JB_FPREG_FCSR * SZREG)(a0)
157	ctc1 v0, $31	157	ctc1 v0, $31
Lines 181-187 Link Here
181	FP_L $f29, (_JB_FPREG_F29 * SZREG)(a0)	181	FP_L $f29, (_JB_FPREG_F29 * SZREG)(a0)
182	FP_L $f31, (_JB_FPREG_F31 * SZREG)(a0)	182	FP_L $f31, (_JB_FPREG_F31 * SZREG)(a0)
183	#endif	183	#endif
184	#endif /* ! SOFTFLOAT */	184	#endif /* ! __mips_soft_float */
185		185
186	REG_EPILOGUE	186	REG_EPILOGUE
187	move v0, a1 # get return value in 1st arg	187	move v0, a1 # get return value in 1st arg

Lines 106-112 Link Here

(-)lib/libc/mips/gen/setjmp.S (-4 / +4 lines)
106	#if defined(__mips_n32) \|\| defined(__mips_n64)	106	#if defined(__mips_n32) \|\| defined(__mips_n64)
107	REG_S gp, (_JB_REG_GP * SZREG)(a0)	107	REG_S gp, (_JB_REG_GP * SZREG)(a0)
108	#endif	108	#endif
109	#ifndef SOFTFLOAT	109	#ifndef __mips_soft_float
110	/*	110	/*
111	* From "MIPSpro N32 ABI Handbook", Table 2-1:	111	* From "MIPSpro N32 ABI Handbook", Table 2-1:
112	* In N32, FP registers F20, F22, F24, F26, F28, F30 are callee-saved.	112	* In N32, FP registers F20, F22, F24, F26, F28, F30 are callee-saved.
Lines 135-141 Link Here
135	FP_S $f29, (_JB_FPREG_F29 * SZREG)(a0)	135	FP_S $f29, (_JB_FPREG_F29 * SZREG)(a0)
136	FP_S $f31, (_JB_FPREG_F31 * SZREG)(a0)	136	FP_S $f31, (_JB_FPREG_F31 * SZREG)(a0)
137	#endif	137	#endif
138	#endif /* ! SOFTFLOAT */	138	#endif /* ! __mips_soft_float */
139		139
140	move v0, zero	140	move v0, zero
141	jr ra	141	jr ra
Lines 190-196 Link Here
190	#if defined(__mips_n32) \|\| defined(__mips_n64)	190	#if defined(__mips_n32) \|\| defined(__mips_n64)
191	REG_L gp, (_JB_REG_GP * SZREG)(a0)	191	REG_L gp, (_JB_REG_GP * SZREG)(a0)
192	#endif	192	#endif
193	#ifndef SOFTFLOAT	193	#ifndef __mips_soft_float
194	/*	194	/*
195	* From "MIPSpro N32 ABI Handbook", Table 2-1:	195	* From "MIPSpro N32 ABI Handbook", Table 2-1:
196	* In N32, FP registers F20, F22, F24, F26, F28, F30 are callee-saved.	196	* In N32, FP registers F20, F22, F24, F26, F28, F30 are callee-saved.
Lines 219-225 Link Here
219	FP_L $f29, (_JB_FPREG_F29 * SZREG)(a0)	219	FP_L $f29, (_JB_FPREG_F29 * SZREG)(a0)
220	FP_L $f31, (_JB_FPREG_F31 * SZREG)(a0)	220	FP_L $f31, (_JB_FPREG_F31 * SZREG)(a0)
221	#endif	221	#endif
222	#endif /* ! SOFTFLOAT */	222	#endif /* ! __mips_soft_float */
223		223
224	move v0, a1	224	move v0, a1
225	j ra	225	j ra