Attachment 180878 Details for Bug 217845 – Replace SOFTFLOAT tests with __mips_soft_float, which gcc/clang define for us.

[patch] Replace SOFTFLOAT tests with __mips_soft_float, which gcc/clang define for us.

float3.diff (text/plain), 6.26 KB, created by Dan Nelson on 2017-03-16 15:08:06 UTC

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Creator: Dan Nelson

Created: 2017-03-16 15:08:06 UTC

Size: 6.26 KB

patch

obsolete

># HG changeset patch
># User Dan Nelson <dnelson_1901@yahoo.com>
># Date 1489675279 18000
>#      Thu Mar 16 09:41:19 2017 -0500
># Branch current-dan
># Node ID 87b4007304f4ee88c9d48f384e7a66e8de75e431
># Parent  b313de44ecf22db1d14b47346aba070b05f22f07
>Replace SOFTFLOAT with __mips_soft_float, which gcc/clang define for us.
>
>D8376 extended softfloat/hardfloat support, but used a macro that never
>actually gets set except in libc and msun's Makefile.inc.  So libc and libm
>got built correctly, but any program including fenv.h itself assumed it was
>on a hardfloat systen and emitted inline fpu instructions for
>fedisableexcept() and friends.
>
>Using __mips_soft_float makes everything work in all cases, since it's a
>compiler-internal macro that is always set correctly for the target.
>
>diff -r b313de44ecf2 -r 87b4007304f4 lib/libc/mips/Makefile.inc
>--- lib/libc/mips/Makefile.inc	Thu Mar 16 09:55:26 2017 -0500
>+++ lib/libc/mips/Makefile.inc	Thu Mar 16 09:41:19 2017 -0500
>@@ -1,9 +1,5 @@
> #	$NetBSD: Makefile.inc,v 1.7 2005/09/17 11:49:39 tsutsui Exp $
> # $FreeBSD$
> 
>-.if ${MACHINE_ARCH:Mmips*hf} == ""
>-CFLAGS+=-DSOFTFLOAT
>-.endif
>-
> SRCS+= machdep_ldisd.c
> SYM_MAPS+= ${LIBC_SRCTOP}/mips/Symbol.map
>diff -r b313de44ecf2 -r 87b4007304f4 lib/libc/mips/gen/_setjmp.S
>--- lib/libc/mips/gen/_setjmp.S	Thu Mar 16 09:55:26 2017 -0500
>+++ lib/libc/mips/gen/_setjmp.S	Thu Mar 16 09:41:19 2017 -0500
>@@ -90,7 +90,7 @@
> 	 * In N64, FP registers F24 .. F31 are callee-saved.
> 	 * In O32, FP registers F20 .. F23 are callee-saved.
> 	 */
>-#ifndef SOFTFLOAT
>+#ifndef __mips_soft_float
> 	cfc1	v0, $31				# too bad can't check if FP used
> #if defined(__mips_n64) || defined(__mips_n32)
> 	FP_S	$f30, (_JB_FPREG_F30 * SZREG)(a0)
>@@ -113,7 +113,7 @@
> 	FP_S	$f31, (_JB_FPREG_F31 * SZREG)(a0)
> #endif
> 	INT_S	v0, (_JB_FPREG_FCSR * SZREG)(a0)
>-#endif /* ! SOFTFLOAT */
>+#endif /* ! __mips_soft_float */
> 	REG_EPILOGUE
> 
> 	j	ra
>@@ -151,7 +151,7 @@
> #if defined(__mips_n32) || defined(__mips_n64)
> 	REG_L		gp, (_JB_REG_GP * SZREG)(a0)
> #endif
>-#ifndef SOFTFLOAT
>+#ifndef __mips_soft_float
> 	# get fpu status
> 	INT_L		v0, (_JB_FPREG_FCSR * SZREG)(a0)
> 	ctc1		v0, $31
>@@ -181,7 +181,7 @@
> 	FP_L	$f29, (_JB_FPREG_F29 * SZREG)(a0)
> 	FP_L	$f31, (_JB_FPREG_F31 * SZREG)(a0)
> #endif
>-#endif	/* ! SOFTFLOAT */
>+#endif	/* ! __mips_soft_float */
> 
> 	REG_EPILOGUE
> 	move	v0, a1			# get return value in 1st arg
>diff -r b313de44ecf2 -r 87b4007304f4 lib/libc/mips/gen/flt_rounds.c
>--- lib/libc/mips/gen/flt_rounds.c	Thu Mar 16 09:55:26 2017 -0500
>+++ lib/libc/mips/gen/flt_rounds.c	Thu Mar 16 09:41:19 2017 -0500
>@@ -14,7 +14,7 @@
> #include <fenv.h>
> #include <float.h>
> 
>-#ifdef	SOFTFLOAT
>+#ifdef	__mips_soft_float
> #include "softfloat-for-gcc.h"
> #include "milieu.h"
> #include "softfloat.h"
>@@ -32,7 +32,7 @@
> {
> 	int mode;
> 
>-#ifdef SOFTFLOAT
>+#ifdef __mips_soft_float
> 	mode = __softfloat_float_rounding_mode;
> #else
> 	__asm __volatile("cfc1 %0,$31" : "=r" (mode));
>diff -r b313de44ecf2 -r 87b4007304f4 lib/libc/mips/gen/setjmp.S
>--- lib/libc/mips/gen/setjmp.S	Thu Mar 16 09:55:26 2017 -0500
>+++ lib/libc/mips/gen/setjmp.S	Thu Mar 16 09:41:19 2017 -0500
>@@ -106,7 +106,7 @@
> #if defined(__mips_n32) || defined(__mips_n64)
> 	REG_S	gp, (_JB_REG_GP * SZREG)(a0)
> #endif
>-#ifndef SOFTFLOAT
>+#ifndef __mips_soft_float
> 	/*
> 	 * From "MIPSpro N32 ABI Handbook", Table 2-1:
> 	 * In N32, FP registers F20, F22, F24, F26, F28, F30 are callee-saved.
>@@ -135,7 +135,7 @@
> 	FP_S	$f29, (_JB_FPREG_F29 * SZREG)(a0)
> 	FP_S	$f31, (_JB_FPREG_F31 * SZREG)(a0)
> #endif
>-#endif	/* ! SOFTFLOAT */
>+#endif	/* ! __mips_soft_float */
> 
> 	move	v0, zero
> 	jr	ra
>@@ -190,7 +190,7 @@
> #if defined(__mips_n32) || defined(__mips_n64)
> 	REG_L	gp, (_JB_REG_GP * SZREG)(a0)
> #endif
>-#ifndef SOFTFLOAT
>+#ifndef __mips_soft_float
> 	/*
> 	 * From "MIPSpro N32 ABI Handbook", Table 2-1:
> 	 * In N32, FP registers F20, F22, F24, F26, F28, F30 are callee-saved.
>@@ -219,7 +219,7 @@
> 	FP_L	$f29, (_JB_FPREG_F29 * SZREG)(a0)
> 	FP_L	$f31, (_JB_FPREG_F31 * SZREG)(a0)
> #endif
>-#endif	/* ! SOFTFLOAT */
>+#endif	/* ! __mips_soft_float */
> 
> 	move	v0, a1
> 	j	ra
>diff -r b313de44ecf2 -r 87b4007304f4 lib/msun/mips/Makefile.inc
>--- lib/msun/mips/Makefile.inc	Thu Mar 16 09:55:26 2017 -0500
>+++ lib/msun/mips/Makefile.inc	Thu Mar 16 09:41:19 2017 -0500
>@@ -1,8 +1,4 @@
> # $FreeBSD$
> 
>-.if ${MACHINE_ARCH:Mmips*hf} == ""
>-CFLAGS+=-DSOFTFLOAT
>-.endif
>-
> LDBL_PREC = 53
> SYM_MAPS += ${.CURDIR}/mips/Symbol.map
>diff -r b313de44ecf2 -r 87b4007304f4 lib/msun/mips/fenv.c
>--- lib/msun/mips/fenv.c	Thu Mar 16 09:55:26 2017 -0500
>+++ lib/msun/mips/fenv.c	Thu Mar 16 09:41:19 2017 -0500
>@@ -39,7 +39,7 @@
>  */
> const fenv_t __fe_dfl_env = 0;
> 
>-#ifdef	SOFTFLOAT
>+#ifdef	__mips_soft_float
> #define __set_env(env, flags, mask, rnd) env = ((flags)                 \
>                                                 | (mask)<<_FPUSW_SHIFT  \
>                                                 | (rnd) << 24)
>diff -r b313de44ecf2 -r 87b4007304f4 lib/msun/mips/fenv.h
>--- lib/msun/mips/fenv.h	Thu Mar 16 09:55:26 2017 -0500
>+++ lib/msun/mips/fenv.h	Thu Mar 16 09:41:19 2017 -0500
>@@ -39,7 +39,7 @@
> typedef	__uint32_t	fexcept_t;
> 
> /* Exception flags */
>-#ifdef SOFTFLOAT
>+#ifdef __mips_soft_float
> #define	_FPUSW_SHIFT	16
> #define	FE_INVALID	0x0001
> #define	FE_DIVBYZERO	0x0002
>@@ -74,12 +74,16 @@
> #define	_ENABLE_SHIFT	5
> #define	_ENABLE_MASK	(FE_ALL_EXCEPT << _ENABLE_SHIFT)
> 
>-#ifndef	SOFTFLOAT
>+#if !defined(__mips_soft_float) && !defined(__mips_hard_float)
>+#error compiler didnt set soft/hard float macros
>+#endif
>+
>+#ifndef	__mips_soft_float
> #define	__cfc1(__fcsr)	__asm __volatile("cfc1 %0, $31" : "=r" (__fcsr))
> #define	__ctc1(__fcsr)	__asm __volatile("ctc1 %0, $31" :: "r" (__fcsr))
> #endif
> 
>-#ifdef SOFTFLOAT
>+#ifdef __mips_soft_float
> int feclearexcept(int __excepts);
> int fegetexceptflag(fexcept_t *__flagp, int __excepts);
> int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
>@@ -223,13 +227,13 @@
> 
> 	return (0);
> }
>-#endif /* !SOFTFLOAT */
>+#endif /* !__mips_soft_float */
> 
> #if __BSD_VISIBLE
> 
> /* We currently provide no external definitions of the functions below. */
> 
>-#ifdef SOFTFLOAT
>+#ifdef __mips_soft_float
> int feenableexcept(int __mask);
> int fedisableexcept(int __mask);
> int fegetexcept(void);
>@@ -268,7 +272,7 @@
> 	return ((fcsr & _ENABLE_MASK) >> _ENABLE_SHIFT);
> }
> 
>-#endif /* !SOFTFLOAT */
>+#endif /* !__mips_soft_float */
> 
> #endif /* __BSD_VISIBLE */
>

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Attachments on bug 217845: 180878