Attachment #183084 for bug #218894

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Lines 1239-1245 Link Here

(-)sys/dev/e1000/e1000_82571.c (-1 / +2 lines)
1239	case e1000_82574:	1239	case e1000_82574:
1240	case e1000_82583:	1240	case e1000_82583:
1241	reg_data = E1000_READ_REG(hw, E1000_GCR);	1241	reg_data = E1000_READ_REG(hw, E1000_GCR);
1242	reg_data \|= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;	1242	reg_data \|= (E1000_GCR_L1_ACT_WITHOUT_L0S_RX \|
		1243	E1000_GCR_DISABLE_TIMEOUT_MECHANISM);
1243	E1000_WRITE_REG(hw, E1000_GCR, reg_data);	1244	E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1244	break;	1245	break;
1245	default:	1246	default:

Lines 42-47 Link Here

(-)sys/dev/e1000/e1000_82571.h (+1 lines)
42	(ID_LED_DEF1_DEF2))	42	(ID_LED_DEF1_DEF2))
43		43
44	#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000	44	#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
		45	#define E1000_GCR_DISABLE_TIMEOUT_MECHANISM 0x80000000
45	#define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */	46	#define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */
46		47
47	/* Intr Throttling - RW */	48	/* Intr Throttling - RW */

Lines 1259-1265 Link Here

(-)sys/dev/e1000/e1000_mac.c (-1 / +2 lines)
1259	* ability to transmit pause frames is not enabled, then these	1259	* ability to transmit pause frames is not enabled, then these
1260	* registers will be set to 0.	1260	* registers will be set to 0.
1261	*/	1261	*/
1262	if (hw->fc.current_mode & e1000_fc_tx_pause) {	1262	if (hw->fc.current_mode == e1000_fc_tx_pause \|\|
		1263	hw->fc.current_mode == e1000_fc_full) {
1263	/* We need to set up the Receive Threshold high and low water	1264	/* We need to set up the Receive Threshold high and low water
1264	* marks as well as (optionally) enabling the transmission of	1265	* marks as well as (optionally) enabling the transmission of
1265	* XON frames.	1266	* XON frames.




	** Figure out the desired mbuf
	** pool for doing jumbos
	*/
	if (adapter->hw.mac.max_frame_size <= MCLBYTES)
		adapter->rx_mbuf_sz = MCLBYTES;
	else if (adapter->hw.mac.max_frame_size <= MJUMPAGESIZE)
		adapter->rx_mbuf_sz = MJUMPAGESIZE;
	else if (adapter->hw.mac.max_frame_size <= MJUM9BYTES)
		adapter->rx_mbuf_sz = MJUM9BYTES;
	else 
		adapter->rx_mbuf_sz = MJUM16BYTES;

	/* Prepare receive descriptors and buffers */
	if (em_setup_receive_structures(adapter)) {

	case e1000_80003es2lan:
			pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
		break;
	case e1000_82573: /* 82573: Total Packet Buffer is 32K */
			pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
		break;
	case e1000_82574:
	case e1000_82583:
			pba = E1000_PBA_26K; /* 26K for Rx, 14K for Tx */
		break;
	case e1000_ich8lan:
		pba = E1000_PBA_8K;

		else
			pba = E1000_PBA_10K;
		break;
	case e1000_82573: /* Total Packet Buffer is 32K */
	case e1000_pchlan:
	case e1000_pch2lan:
	case e1000_pch_lpt:
	case e1000_pch_spt:
		/*
		 * Total size (PBS) is 32K.
		 * Small Rx buffer size causes Receiver Overrun Error.
		 * For good Tx performance, Tx buffer should be more than 
		 * double size of a frame.
		 * 26K for Rx, 6K for Tx at ETHERMTU frame size.
		 * 18K for Rx, 14K for Tx at 9K Jumbo frame size.
		 */
		{
	  		u32 pbs=32, min_tx, good_tx;
			min_tx  = if_getmtu(ifp)+ sizeof(struct e1000_tx_desc);
			good_tx = max(roundup2((min_tx<<1), 2048)>>10, 6);
			min_tx  = max(roundup2(min_tx, 2048)>>10, 6);
			pba = pbs - good_tx;
			if(pba < good_tx) {
				pba = good_tx;
			}
			if( (pbs-pba) < min_tx) {
				pba = pbs - min_tx;
			}
		}
		break;
	default:
		if (adapter->hw.mac.max_frame_size > 8192)

	 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
	 */
	rx_buffer_size = ((E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10 );
	/* remain 20% or 2 full sized frames. */
	hw->fc.high_water =
		max(((rx_buffer_size * 8) / 10),
		    (rx_buffer_size - 2 * adapter->hw.mac.max_frame_size))
		& 0xFFF0;
	hw->fc.low_water = hw->fc.high_water - 1024; /* 1k */

	if (adapter->fc) /* locally set flow control value? */
		hw->fc.requested_mode = adapter->fc;

	case e1000_pch2lan:
	case e1000_pch_lpt:
	case e1000_pch_spt:
		hw->fc.high_water = 0x5C20;
		hw->fc.low_water = 0x5048;
		hw->fc.pause_time = 0x0650;
		hw->fc.refresh_time = 0x0400;
		/* Jumbos need adjusted PBA */
		if (if_getmtu(ifp) > ETHERMTU)
			E1000_WRITE_REG(hw, E1000_PBA, 12);
		else
			E1000_WRITE_REG(hw, E1000_PBA, 26);
		break;
        case e1000_ich9lan:
        case e1000_ich10lan:
		if (if_getmtu(ifp) > ETHERMTU) {
			hw->fc.high_water = 0x2800;
			hw->fc.low_water = hw->fc.high_water - 8;
			break;
		} 
		/* else fall thru */
	default:
		if (hw->mac.type == e1000_80003es2lan)

		txr->busy = EM_TX_IDLE;
		txdctl = 0; /* clear txdctl */
                txdctl |= 0x1f; /* PTHRESH */
		if (adapter->hw.mac.type == e1000_82574) {
			txdctl |= 4 << 8; /* HTHRESH */
                	txdctl |= 4 << 16;/* WTHRESH */
		} else {
			txdctl |= 1 << 8; /* HTHRESH */
			txdctl |= 1 << 16;/* WTHRESH */
		}
		txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
		txdctl |= E1000_TXDCTL_GRAN;
                txdctl |= 1 << 25; /* LWTHRESH */

		u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
		E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
	} else if (adapter->hw.mac.type == e1000_82574) {
			u32 rxdctl = 0;
			u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));

			rxdctl |= 0x20; /* PTHRESH */
			rxdctl |= 1 << 8; /* HTHRESH */
			rxdctl |= 1 << 16;/* WTHRESH */
			rxdctl |= 1 << 24; /* Switch to granularity */
			E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl);
		}
	}
		
	if (adapter->hw.mac.type >= e1000_pch2lan) {

        /* Make sure VLAN Filters are off */
        rctl &= ~E1000_RCTL_VFE;

	/* Clear BSIZE bits 17:16, BSEX bit 25 and FLXBUF bits 30:27 */
	rctl &= ~0x7A030000;
	if (adapter->hw.mac.max_frame_size <= 2048)
		rctl |= E1000_RCTL_SZ_2048;
	else if (adapter->hw.mac.max_frame_size <= 4096)
		rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
	else if (adapter->hw.mac.max_frame_size <= 8192)
		rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
	else
		rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX;

	/* Use FLXBUF instead of BSIZE */
	if (adapter->hw.mac.max_frame_size > 2048)
		rctl |= roundup2(adapter->hw.mac.max_frame_size, 1024)<<(27-10);

	/* ensure we clear use DTYPE of 00 here */
	rctl &= ~0x00000C00;
	/* Write out the settings */

	*/
	for (int i = 0; i < EM_VFTA_SIZE; i++)
                if (adapter->shadow_vfta[i] != 0)
			e1000_write_vfta(hw,
                            i, adapter->shadow_vfta[i]);

	reg = E1000_READ_REG(hw, E1000_CTRL);

Return to bug 218894

Lines 1421-1432 Link Here

(-)sys/dev/e1000/if_em.c (-33 / +57 lines)
1421	** Figure out the desired mbuf	1421	** Figure out the desired mbuf
1422	** pool for doing jumbos	1422	** pool for doing jumbos
1423	*/	1423	*/
1424	if (adapter->hw.mac.max_frame_size <= 2048)	1424	if (adapter->hw.mac.max_frame_size <= MCLBYTES)
1425	adapter->rx_mbuf_sz = MCLBYTES;	1425	adapter->rx_mbuf_sz = MCLBYTES;
1426	else if (adapter->hw.mac.max_frame_size <= 4096)	1426	else if (adapter->hw.mac.max_frame_size <= MJUMPAGESIZE)
1427	adapter->rx_mbuf_sz = MJUMPAGESIZE;	1427	adapter->rx_mbuf_sz = MJUMPAGESIZE;
1428	else	1428	else if (adapter->hw.mac.max_frame_size <= MJUM9BYTES)
1429	adapter->rx_mbuf_sz = MJUM9BYTES;	1429	adapter->rx_mbuf_sz = MJUM9BYTES;
		1430	else
		1431	adapter->rx_mbuf_sz = MJUM16BYTES;
1430		1432
1431	/* Prepare receive descriptors and buffers */	1433	/* Prepare receive descriptors and buffers */
1432	if (em_setup_receive_structures(adapter)) {	1434	if (em_setup_receive_structures(adapter)) {
Lines 3051-3062 Link Here
3051	case e1000_80003es2lan:	3053	case e1000_80003es2lan:
3052	pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */	3054	pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
3053	break;	3055	break;
3054	case e1000_82573: /* 82573: Total Packet Buffer is 32K */
3055	pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
3056	break;
3057	case e1000_82574:	3056	case e1000_82574:
3058	case e1000_82583:	3057	case e1000_82583:
3059	pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */	3058	pba = E1000_PBA_26K; /* 26K for Rx, 14K for Tx */
3060	break;	3059	break;
3061	case e1000_ich8lan:	3060	case e1000_ich8lan:
3062	pba = E1000_PBA_8K;	3061	pba = E1000_PBA_8K;
Lines 3069-3079 Link Here
3069	else	3068	else
3070	pba = E1000_PBA_10K;	3069	pba = E1000_PBA_10K;
3071	break;	3070	break;
		3071	case e1000_82573: /* Total Packet Buffer is 32K */
3072	case e1000_pchlan:	3072	case e1000_pchlan:
3073	case e1000_pch2lan:	3073	case e1000_pch2lan:
3074	case e1000_pch_lpt:	3074	case e1000_pch_lpt:
3075	case e1000_pch_spt:	3075	case e1000_pch_spt:
3076	pba = E1000_PBA_26K;	3076	/*
		3077	* Total size (PBS) is 32K.
		3078	* Small Rx buffer size causes Receiver Overrun Error.
		3079	* For good Tx performance, Tx buffer should be more than
		3080	* double size of a frame.
		3081	* 26K for Rx, 6K for Tx at ETHERMTU frame size.
		3082	* 18K for Rx, 14K for Tx at 9K Jumbo frame size.
		3083	*/
		3084	{
		3085	u32 pbs=32, min_tx, good_tx;
		3086	min_tx = if_getmtu(ifp)+ sizeof(struct e1000_tx_desc);
		3087	good_tx = max(roundup2((min_tx<<1), 2048)>>10, 6);
		3088	min_tx = max(roundup2(min_tx, 2048)>>10, 6);
		3089	pba = pbs - good_tx;
		3090	if(pba < good_tx) {
		3091	pba = good_tx;
		3092	}
		3093	if( (pbs-pba) < min_tx) {
		3094	pba = pbs - min_tx;
		3095	}
		3096	}
3077	break;	3097	break;
3078	default:	3098	default:
3079	if (adapter->hw.mac.max_frame_size > 8192)	3099	if (adapter->hw.mac.max_frame_size > 8192)
Lines 3098-3106 Link Here
3098	* - The pause time is fairly large at 1000 x 512ns = 512 usec.	3118	* - The pause time is fairly large at 1000 x 512ns = 512 usec.
3099	*/	3119	*/
3100	rx_buffer_size = ((E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10 );	3120	rx_buffer_size = ((E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10 );
3101	hw->fc.high_water = rx_buffer_size -	3121	/* remain 20% or 2 full sized frames. */
3102	roundup2(adapter->hw.mac.max_frame_size, 1024);	3122	hw->fc.high_water =
3103	hw->fc.low_water = hw->fc.high_water - 1500;	3123	max(((rx_buffer_size * 8) / 10),
		3124	(rx_buffer_size - 2 * adapter->hw.mac.max_frame_size))
		3125	& 0xFFF0;
		3126	hw->fc.low_water = hw->fc.high_water - 1024; /* 1k */
3104		3127
3105	if (adapter->fc) /* locally set flow control value? */	3128	if (adapter->fc) /* locally set flow control value? */
3106	hw->fc.requested_mode = adapter->fc;	3129	hw->fc.requested_mode = adapter->fc;
Lines 3132-3154 Link Here
3132	case e1000_pch2lan:	3155	case e1000_pch2lan:
3133	case e1000_pch_lpt:	3156	case e1000_pch_lpt:
3134	case e1000_pch_spt:	3157	case e1000_pch_spt:
3135	hw->fc.high_water = 0x5C20;
3136	hw->fc.low_water = 0x5048;
3137	hw->fc.pause_time = 0x0650;	3158	hw->fc.pause_time = 0x0650;
3138	hw->fc.refresh_time = 0x0400;	3159	hw->fc.refresh_time = 0x0400;
3139	/* Jumbos need adjusted PBA */
3140	if (if_getmtu(ifp) > ETHERMTU)
3141	E1000_WRITE_REG(hw, E1000_PBA, 12);
3142	else
3143	E1000_WRITE_REG(hw, E1000_PBA, 26);
3144	break;	3160	break;
3145	case e1000_ich9lan:	3161	case e1000_ich9lan:
3146	case e1000_ich10lan:	3162	case e1000_ich10lan:
3147	if (if_getmtu(ifp) > ETHERMTU) {
3148	hw->fc.high_water = 0x2800;
3149	hw->fc.low_water = hw->fc.high_water - 8;	3163	hw->fc.low_water = hw->fc.high_water - 8;
3150	break;	3164	break;
3151	}
3152	/* else fall thru */	3165	/* else fall thru */
3153	default:	3166	default:
3154	if (hw->mac.type == e1000_80003es2lan)	3167	if (hw->mac.type == e1000_80003es2lan)
Lines 3684-3691 Link Here
3684	txr->busy = EM_TX_IDLE;	3697	txr->busy = EM_TX_IDLE;
3685	txdctl = 0; /* clear txdctl */	3698	txdctl = 0; /* clear txdctl */
3686	txdctl \|= 0x1f; /* PTHRESH */	3699	txdctl \|= 0x1f; /* PTHRESH */
3687	txdctl \|= 1 << 8; /* HTHRESH */	3700	if (adapter->hw.mac.type == e1000_82574) {
3688	txdctl \|= 1 << 16;/* WTHRESH */	3701	txdctl \|= 4 << 8; /* HTHRESH */
		3702	txdctl \|= 4 << 16;/* WTHRESH */
		3703	} else {
		3704	txdctl \|= 1 << 8; /* HTHRESH */
		3705	txdctl \|= 1 << 16;/* WTHRESH */
		3706	}
3689	txdctl \|= 1 << 22; /* Reserved bit 22 must always be 1 */	3707	txdctl \|= 1 << 22; /* Reserved bit 22 must always be 1 */
3690	txdctl \|= E1000_TXDCTL_GRAN;	3708	txdctl \|= E1000_TXDCTL_GRAN;
3691	txdctl \|= 1 << 25; /* LWTHRESH */	3709	txdctl \|= 1 << 25; /* LWTHRESH */
Lines 4717-4731 Link Here
4717	u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));	4735	u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
4718	E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl \| 3);	4736	E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl \| 3);
4719	} else if (adapter->hw.mac.type == e1000_82574) {	4737	} else if (adapter->hw.mac.type == e1000_82574) {
4720	for (int i = 0; i < adapter->num_queues; i++) {	4738	u32 rxdctl = 0;
4721	u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
4722		4739
4723	rxdctl \|= 0x20; /* PTHRESH */	4740	rxdctl \|= 0x20; /* PTHRESH */
4724	rxdctl \|= 4 << 8; /* HTHRESH */	4741	rxdctl \|= 1 << 8; /* HTHRESH */
4725	rxdctl \|= 4 << 16;/* WTHRESH */	4742	rxdctl \|= 1 << 16;/* WTHRESH */
4726	rxdctl \|= 1 << 24; /* Switch to granularity */	4743	rxdctl \|= 1 << 24; /* Switch to granularity */
4727	E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);	4744	E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl);
4728	}
4729	}	4745	}
4730		4746
4731	if (adapter->hw.mac.type >= e1000_pch2lan) {	4747	if (adapter->hw.mac.type >= e1000_pch2lan) {
Lines 4738-4750 Link Here
4738	/* Make sure VLAN Filters are off */	4754	/* Make sure VLAN Filters are off */
4739	rctl &= ~E1000_RCTL_VFE;	4755	rctl &= ~E1000_RCTL_VFE;
4740		4756
4741	if (adapter->rx_mbuf_sz == MCLBYTES)	4757	/* Clear BSIZE bits 17:16, BSEX bit 25 and FLXBUF bits 30:27 */
		4758	rctl &= ~0x7A030000;
		4759	if (adapter->hw.mac.max_frame_size <= 2048)
4742	rctl \|= E1000_RCTL_SZ_2048;	4760	rctl \|= E1000_RCTL_SZ_2048;
4743	else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)	4761	else if (adapter->hw.mac.max_frame_size <= 4096)
4744	rctl \|= E1000_RCTL_SZ_4096 \| E1000_RCTL_BSEX;	4762	rctl \|= E1000_RCTL_SZ_4096 \| E1000_RCTL_BSEX;
4745	else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)	4763	else if (adapter->hw.mac.max_frame_size <= 8192)
4746	rctl \|= E1000_RCTL_SZ_8192 \| E1000_RCTL_BSEX;	4764	rctl \|= E1000_RCTL_SZ_8192 \| E1000_RCTL_BSEX;
		4765	else
		4766	rctl \|= E1000_RCTL_SZ_16384 \| E1000_RCTL_BSEX;
4747		4767
		4768	/* Use FLXBUF instead of BSIZE */
		4769	if (adapter->hw.mac.max_frame_size > 2048)
		4770	rctl \|= roundup2(adapter->hw.mac.max_frame_size, 1024)<<(27-10);
		4771
4748	/* ensure we clear use DTYPE of 00 here */	4772	/* ensure we clear use DTYPE of 00 here */
4749	rctl &= ~0x00000C00;	4773	rctl &= ~0x00000C00;
4750	/* Write out the settings */	4774	/* Write out the settings */
Lines 5093-5099 Link Here
5093	*/	5117	*/
5094	for (int i = 0; i < EM_VFTA_SIZE; i++)	5118	for (int i = 0; i < EM_VFTA_SIZE; i++)
5095	if (adapter->shadow_vfta[i] != 0)	5119	if (adapter->shadow_vfta[i] != 0)
5096	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,	5120	e1000_write_vfta(hw,
5097	i, adapter->shadow_vfta[i]);	5121	i, adapter->shadow_vfta[i]);
5098		5122
5099	reg = E1000_READ_REG(hw, E1000_CTRL);	5123	reg = E1000_READ_REG(hw, E1000_CTRL);