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Lines 125-132
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| 125 |
uhci_pci_resume(device_t self) |
125 |
uhci_pci_resume(device_t self) |
| 126 |
{ |
126 |
{ |
| 127 |
uhci_softc_t *sc = device_get_softc(self); |
127 |
uhci_softc_t *sc = device_get_softc(self); |
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128 |
u_int32_t csr; |
| 128 |
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129 |
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| 129 |
uhci_power(PWR_RESUME, sc); |
130 |
uhci_power(PWR_RESUME, sc); |
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131 |
/* Enable the device. */ |
| 132 |
csr = pci_read_config(self, PCI_COMMAND_STATUS_REG, 4); |
| 133 |
pci_write_config(self, PCI_COMMAND_STATUS_REG, |
| 134 |
csr | PCIM_CMD_BUSMASTEREN, 4); |
| 130 |
bus_generic_resume(self); |
135 |
bus_generic_resume(self); |
| 131 |
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136 |
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| 132 |
return 0; |
137 |
return 0; |
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Lines 182-187
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| 182 |
uhci_softc_t *sc = device_get_softc(self); |
187 |
uhci_softc_t *sc = device_get_softc(self); |
| 183 |
int rid; |
188 |
int rid; |
| 184 |
int err; |
189 |
int err; |
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190 |
u_int32_t csr; |
| 185 |
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191 |
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| 186 |
rid = PCI_UHCI_BASE_REG; |
192 |
rid = PCI_UHCI_BASE_REG; |
| 187 |
sc->io_res = bus_alloc_resource(self, SYS_RES_IOPORT, &rid, |
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sc->io_res = bus_alloc_resource(self, SYS_RES_IOPORT, &rid, |
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Lines 275-280
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| 275 |
uhci_pci_detach(self); |
281 |
uhci_pci_detach(self); |
| 276 |
return ENXIO; |
282 |
return ENXIO; |
| 277 |
} |
283 |
} |
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284 |
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| 285 |
/* Enable the device. */ |
| 286 |
csr = pci_read_config(self, PCI_COMMAND_STATUS_REG, 4); |
| 287 |
pci_write_config(self, PCI_COMMAND_STATUS_REG, |
| 288 |
csr | PCIM_CMD_BUSMASTEREN, 4); |
| 278 |
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289 |
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| 279 |
/* Set the PIRQD enable bit and switch off all the others. We don't |
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/* Set the PIRQD enable bit and switch off all the others. We don't |
| 280 |
* want legacy support to interfere with us |
291 |
* want legacy support to interfere with us |