Attachment #188407 for bug #223971




      page size extension                    = true
      processor serial number                = false
      CLFLUSH instruction                    = true
      debug store                            = false
      thermal monitor and clock ctrl         = false
      MMX Technology                         = true
      FXSAVE/FXRSTOR                         = true
      SSE extensions                         = true
      SSE2 extensions                        = true
      self snoop                             = false
      hyper-threading / multi-core supported = true
      therm. monitor                         = false
      IA64                                   = false
      pending break event                    = false
   feature information (1/ecx):
      PNI/SSE3: Prescott New Instructions     = true
      PCLMULDQ instruction                    = false
      64-bit debug store                      = false
      MONITOR/MWAIT                           = false
      CPL-qualified debug store               = false
      VMX: virtual machine extensions         = false
      SMX: safer mode extensions              = false
      Enhanced Intel SpeedStep Technology     = false
      thermal monitor 2                       = false
      SSSE3 extensions                        = true
      context ID: adaptive or shared L1 data  = false
      FMA instruction                         = false
      CMPXCHG16B instruction                  = false
      xTPR disable                            = false
      perfmon and debug                       = false
      process context identifiers             = false
      direct cache access                     = false
      SSE4.1 extensions                       = false

      cache level                          = 0x2 (2)
      self-initializing cache level        = true
      fully associative cache              = false
      extra threads sharing this cache     = 0x0 (0)
      extra processor cores on this die    = 0x3 (3)
      system coherency line size           = 0x3f (63)
      physical line partitions             = 0x0 (0)

      complex cache indexing               = false
      number of sets - 1 (s)               = 4095
   MONITOR/MWAIT (5):
      smallest monitor-line size (bytes)       = 0x0 (0)
      largest monitor-line size (bytes)        = 0x0 (0)
      enum of Monitor-MWAIT exts supported     = false
      supports intrs as break-event for MWAIT  = false
      number of C0 sub C-states using MWAIT    = 0x0 (0)
      number of C1 sub C-states using MWAIT    = 0x0 (0)
      number of C2 sub C-states using MWAIT    = 0x0 (0)
      number of C3 sub C-states using MWAIT    = 0x0 (0)
      number of C4 sub C-states using MWAIT    = 0x0 (0)

      number of C6 sub C-states using MWAIT    = 0x0 (0)
      number of C7 sub C-states using MWAIT    = 0x0 (0)
   Thermal and Power Management Features (6):
      digital thermometer                     = false
      Intel Turbo Boost Technology            = false
      ARAT always running APIC timer          = false
      PLN power limit notification            = false

      HWP energy performance preference       = false
      HWP package level request               = false
      HDC base registers                      = false
      digital thermometer thresholds          = 0x0 (0)
      ACNT/MCNT supported performance measure = false
      ACNT2 available                         = false
      performance-energy bias capability      = false
   extended feature flags (7):

   Direct Cache Access Parameters (9):
      PLATFORM_DCA_CAP MSR bits = 0
   Architecture Performance Monitoring Features (0xa/eax):
      version ID                               = 0x0 (0)
      number of counters per logical processor = 0x0 (0)
      bit width of counter                     = 0x0 (0)
      length of EBX bit vector                 = 0x0 (0)
   Architecture Performance Monitoring Features (0xa/ebx):
      core cycle event not available           = false
      instruction retired event not available  = false

      branch inst retired event not available  = false
      branch mispred retired event not avail   = false
   Architecture Performance Monitoring Features (0xa/edx):
      number of fixed counters    = 0x0 (0)
      bit width of fixed counters = 0x0 (0)
   extended feature flags (0x80000001/edx):
      SYSCALL and SYSRET instructions        = true
      execution disable                      = true

Return to bug 223971

Lines 34-66 Link Here

(-)cpuid-etallen.guest (-29 / +29 lines)
34	page size extension = true	34	page size extension = true
35	processor serial number = false	35	processor serial number = false
36	CLFLUSH instruction = true	36	CLFLUSH instruction = true
37	debug store = true	37	debug store = false
38	thermal monitor and clock ctrl = true	38	thermal monitor and clock ctrl = false
39	MMX Technology = true	39	MMX Technology = true
40	FXSAVE/FXRSTOR = true	40	FXSAVE/FXRSTOR = true
41	SSE extensions = true	41	SSE extensions = true
42	SSE2 extensions = true	42	SSE2 extensions = true
43	self snoop = true	43	self snoop = false
44	hyper-threading / multi-core supported = true	44	hyper-threading / multi-core supported = true
45	therm. monitor = true	45	therm. monitor = false
46	IA64 = false	46	IA64 = false
47	pending break event = true	47	pending break event = false
48	feature information (1/ecx):	48	feature information (1/ecx):
49	PNI/SSE3: Prescott New Instructions = true	49	PNI/SSE3: Prescott New Instructions = true
50	PCLMULDQ instruction = false	50	PCLMULDQ instruction = false
51	64-bit debug store = true	51	64-bit debug store = false
52	MONITOR/MWAIT = true	52	MONITOR/MWAIT = false
53	CPL-qualified debug store = true	53	CPL-qualified debug store = false
54	VMX: virtual machine extensions = true	54	VMX: virtual machine extensions = false
55	SMX: safer mode extensions = false	55	SMX: safer mode extensions = false
56	Enhanced Intel SpeedStep Technology = true	56	Enhanced Intel SpeedStep Technology = false
57	thermal monitor 2 = true	57	thermal monitor 2 = false
58	SSSE3 extensions = true	58	SSSE3 extensions = true
59	context ID: adaptive or shared L1 data = false	59	context ID: adaptive or shared L1 data = false
60	FMA instruction = false	60	FMA instruction = false
61	CMPXCHG16B instruction = true	61	CMPXCHG16B instruction = false
62	xTPR disable = true	62	xTPR disable = false
63	perfmon and debug = true	63	perfmon and debug = false
64	process context identifiers = false	64	process context identifiers = false
65	direct cache access = false	65	direct cache access = false
66	SSE4.1 extensions = false	66	SSE4.1 extensions = false
Lines 124-130 Link Here
124	cache level = 0x2 (2)	124	cache level = 0x2 (2)
125	self-initializing cache level = true	125	self-initializing cache level = true
126	fully associative cache = false	126	fully associative cache = false
127	extra threads sharing this cache = 0x1 (1)	127	extra threads sharing this cache = 0x0 (0)
128	extra processor cores on this die = 0x3 (3)	128	extra processor cores on this die = 0x3 (3)
129	system coherency line size = 0x3f (63)	129	system coherency line size = 0x3f (63)
130	physical line partitions = 0x0 (0)	130	physical line partitions = 0x0 (0)
Lines 135-146 Link Here
135	complex cache indexing = false	135	complex cache indexing = false
136	number of sets - 1 (s) = 4095	136	number of sets - 1 (s) = 4095
137	MONITOR/MWAIT (5):	137	MONITOR/MWAIT (5):
138	smallest monitor-line size (bytes) = 0x40 (64)	138	smallest monitor-line size (bytes) = 0x0 (0)
139	largest monitor-line size (bytes) = 0x40 (64)	139	largest monitor-line size (bytes) = 0x0 (0)
140	enum of Monitor-MWAIT exts supported = true	140	enum of Monitor-MWAIT exts supported = false
141	supports intrs as break-event for MWAIT = true	141	supports intrs as break-event for MWAIT = false
142	number of C0 sub C-states using MWAIT = 0x0 (0)	142	number of C0 sub C-states using MWAIT = 0x0 (0)
143	number of C1 sub C-states using MWAIT = 0x2 (2)	143	number of C1 sub C-states using MWAIT = 0x0 (0)
144	number of C2 sub C-states using MWAIT = 0x0 (0)	144	number of C2 sub C-states using MWAIT = 0x0 (0)
145	number of C3 sub C-states using MWAIT = 0x0 (0)	145	number of C3 sub C-states using MWAIT = 0x0 (0)
146	number of C4 sub C-states using MWAIT = 0x0 (0)	146	number of C4 sub C-states using MWAIT = 0x0 (0)
Lines 148-154 Link Here
148	number of C6 sub C-states using MWAIT = 0x0 (0)	148	number of C6 sub C-states using MWAIT = 0x0 (0)
149	number of C7 sub C-states using MWAIT = 0x0 (0)	149	number of C7 sub C-states using MWAIT = 0x0 (0)
150	Thermal and Power Management Features (6):	150	Thermal and Power Management Features (6):
151	digital thermometer = true	151	digital thermometer = false
152	Intel Turbo Boost Technology = false	152	Intel Turbo Boost Technology = false
153	ARAT always running APIC timer = false	153	ARAT always running APIC timer = false
154	PLN power limit notification = false	154	PLN power limit notification = false
Lines 160-167 Link Here
160	HWP energy performance preference = false	160	HWP energy performance preference = false
161	HWP package level request = false	161	HWP package level request = false
162	HDC base registers = false	162	HDC base registers = false
163	digital thermometer thresholds = 0x2 (2)	163	digital thermometer thresholds = 0x0 (0)
164	ACNT/MCNT supported performance measure = true	164	ACNT/MCNT supported performance measure = false
165	ACNT2 available = false	165	ACNT2 available = false
166	performance-energy bias capability = false	166	performance-energy bias capability = false
167	extended feature flags (7):	167	extended feature flags (7):
Lines 209-218 Link Here
209	Direct Cache Access Parameters (9):	209	Direct Cache Access Parameters (9):
210	PLATFORM_DCA_CAP MSR bits = 0	210	PLATFORM_DCA_CAP MSR bits = 0
211	Architecture Performance Monitoring Features (0xa/eax):	211	Architecture Performance Monitoring Features (0xa/eax):
212	version ID = 0x2 (2)	212	version ID = 0x0 (0)
213	number of counters per logical processor = 0x2 (2)	213	number of counters per logical processor = 0x0 (0)
214	bit width of counter = 0x28 (40)	214	bit width of counter = 0x0 (0)
215	length of EBX bit vector = 0x7 (7)	215	length of EBX bit vector = 0x0 (0)
216	Architecture Performance Monitoring Features (0xa/ebx):	216	Architecture Performance Monitoring Features (0xa/ebx):
217	core cycle event not available = false	217	core cycle event not available = false
218	instruction retired event not available = false	218	instruction retired event not available = false
Lines 222-229 Link Here
222	branch inst retired event not available = false	222	branch inst retired event not available = false
223	branch mispred retired event not avail = false	223	branch mispred retired event not avail = false
224	Architecture Performance Monitoring Features (0xa/edx):	224	Architecture Performance Monitoring Features (0xa/edx):
225	number of fixed counters = 0x3 (3)	225	number of fixed counters = 0x0 (0)
226	bit width of fixed counters = 0x28 (40)	226	bit width of fixed counters = 0x0 (0)
227	extended feature flags (0x80000001/edx):	227	extended feature flags (0x80000001/edx):
228	SYSCALL and SYSRET instructions = true	228	SYSCALL and SYSRET instructions = true
229	execution disable = true	229	execution disable = true