Attachment 189922 Details for Bug 225330 – Patch to make clang do a slightly better job at restoring the EFLAGS register

[patch] Patch to make clang do a slightly better job at restoring the EFLAGS register

clang-eflags.patch (text/plain), 2.97 KB, created by Jonathan T. Looney on 2018-01-20 01:03:28 UTC

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Creator: Jonathan T. Looney

Created: 2018-01-20 01:03:28 UTC

Size: 2.97 KB

patch

obsolete

>Index: contrib/llvm/lib/Target/X86/X86InstrInfo.cpp
>===================================================================
>--- contrib/llvm/lib/Target/X86/X86InstrInfo.cpp	(revision 328051)
>+++ contrib/llvm/lib/Target/X86/X86InstrInfo.cpp	(working copy)
>@@ -6717,12 +6717,18 @@
>   bool is64 = X86::GR64RegClass.contains(Reg);
> 
>   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
>-    int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
>+    int MovRR = is64 ? X86::MOV64rr : X86::MOV32rr;
>+    int MovRM = is64 ? X86::MOV64rm : X86::MOV32rm;
>+    int MovMR = is64 ? X86::MOV64mr : X86::MOV32mr;
>     int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
>     int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
>     int Pop = is64 ? X86::POP64r : X86::POP32r;
>     int PopF = is64 ? X86::POPF64 : X86::POPF32;
>     int AX = is64 ? X86::RAX : X86::EAX;
>+    int ANDri = is64 ? X86::AND64ri32 : X86::AND32ri;
>+    int ORrr = is64 ? X86::OR64rr : X86::OR32rr;
>+    int SP = is64 ? X86::RSP : X86::ESP;
>+    int32_t EflagsMask = 0x8d5; // OF, SF, ZF, AF, PF, CF
> 
>     if (!Subtarget.hasLAHFSAHF()) {
>       assert(Subtarget.is64Bit() &&
>@@ -6733,13 +6739,13 @@
>       if (FromEFLAGS) {
>         BuildMI(MBB, MI, DL, get(PushF));
>         BuildMI(MBB, MI, DL, get(Pop), DestReg);
>+        BuildMI(MBB, MI, DL, get(ANDri), DestReg)
>+            .addReg(DestReg)
>+            .addImm(EflagsMask);
>+        return;
>       }
>-      if (ToEFLAGS) {
>-        BuildMI(MBB, MI, DL, get(Push))
>-            .addReg(SrcReg, getKillRegState(KillSrc));
>-        BuildMI(MBB, MI, DL, get(PopF));
>-      }
>-      return;
>+      // The ToEFLAGS case uses RAX/EAX, so it is handled later with the
>+      // LAHF/SAHF case which also requires that register.
>     }
> 
>     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
>@@ -6794,14 +6800,26 @@
>     if (FromEFLAGS) {
>       BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
>       BuildMI(MBB, MI, DL, get(X86::LAHF));
>-      BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
>+      BuildMI(MBB, MI, DL, get(MovRR), Reg).addReg(AX);
>     }
>-    if (ToEFLAGS) {
>-      BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
>+    if (ToEFLAGS && Subtarget.hasLAHFSAHF()) {
>+      BuildMI(MBB, MI, DL, get(MovRR), AX).addReg(Reg, getKillRegState(KillSrc));
>       BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
>           .addReg(X86::AL)
>           .addImm(INT8_MAX);
>       BuildMI(MBB, MI, DL, get(X86::SAHF));
>+    } else if (ToEFLAGS) {
>+        BuildMI(MBB, MI, DL, get(PushF));
>+        addRegOffset(BuildMI(MBB, MI, DL, get(MovRM), AX), SP, false, 0);
>+        BuildMI(MBB, MI, DL, get(ANDri), AX)
>+            .addReg(AX)
>+            .addImm(~(EflagsMask));
>+        BuildMI(MBB, MI, DL, get(ORrr), AX)
>+            .addReg(AX)
>+            .addReg(SrcReg, getKillRegState(KillSrc));
>+        addRegOffset(BuildMI(MBB, MI, DL, get(MovMR)), SP, false, 0)
>+            .addReg(AX);
>+        BuildMI(MBB, MI, DL, get(PopF));
>     }
>     if (!AXDead)
>       BuildMI(MBB, MI, DL, get(Pop), AX);

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Attachments on bug 225330: 189922