Attachment #194974 for bug #139743




static void		pci_unmask_msix(device_t dev, u_int index);
static int		pci_msi_blacklisted(void);
static int		pci_msix_blacklisted(void);
static void		pci_fix_asus_smbus(device_t dev);
static void		pci_resume_msi(device_t dev);
static void		pci_resume_msix(device_t dev);
static int		pci_remap_intr_method(device_t bus, device_t dev,

#define	PCI_QUIRK_UNMAP_REG	4 /* Ignore PCI map register */
#define	PCI_QUIRK_DISABLE_MSIX	5 /* MSI-X doesn't work */
#define	PCI_QUIRK_MSI_INTX_BUG	6 /* PCIM_CMD_INTxDIS disables MSI */
#define	PCI_QUIRK_FIXUP_ROUTINE	7 /* PCI needs a fix to continue */
	int	arg1;
	int	arg2;
	void (*fixup_func)(device_t dev);
};

static const struct pci_quirk pci_quirks[] = {
	/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
	{ 0x71138086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
	{ 0x719b8086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
	/* As does the Serverworks OSB4 (the SMBus mapping register) */
	{ 0x02001166, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },

	/*
	 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
	 * or the CMIC-SL (AKA ServerWorks GC_LE).
	 */
	{ 0x00141166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x00171166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

	/*
	 * MSI doesn't work on earlier Intel chipsets including
	 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
	 */
	{ 0x25408086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25508086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25608086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25708086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25788086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x35808086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

	/*
	 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
	 * bridge.
	 */
	{ 0x74501022, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

	/*
	 * MSI-X allocation doesn't work properly for devices passed through
	 * by VMware up to at least ESXi 5.1.
	 */
	{ 0x079015ad, PCI_QUIRK_DISABLE_MSIX,	0,	0, NULL }, /* PCI/PCI-X */
	{ 0x07a015ad, PCI_QUIRK_DISABLE_MSIX,	0,	0, NULL }, /* PCIe */

	/*
	 * Some virtualization environments emulate an older chipset
	 * but support MSI just fine.  QEMU uses the Intel 82440.
	 */
	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM,	0,	0, NULL },

	/*
	 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus

	 * For SB600 A21 and later, firmware must set the bit to hide it.
	 * For SB700 and later, it is unused and hardcoded to zero.
	 */
	{ 0x43851002, PCI_QUIRK_UNMAP_REG,	0x14,	0, NULL },

	/*
	 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have
	 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit
	 * of the command register is set.
	 */
	{ 0x10911969, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL },
	{ 0xE0911969, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL },
	{ 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL },
	{ 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL },
	{ 0x10901969, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL },

	/*
	 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't
	 * issue MSI interrupts with PCIM_CMD_INTxDIS set either.
	 */
	{ 0x166814e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5714 */
	{ 0x166914e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5714S */
	{ 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5780 */
	{ 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5780S */
	{ 0x167814e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5715 */
	{ 0x167914e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5715S */

	/*
	 * The ASUS P4B-motherboards needs a hack to enable the Intel 801SMBus
	 */
	{ 0x24408086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },
	{ 0x24C08086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },

	{ 0 }
};

		cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
}

/* asus p4b/p4pe hack */

static void
pci_fix_asus_smbus(device_t dev)
{
	int	pmccfg;

	/* read subsystem vendor-id */
	pmccfg = pci_read_config(dev, 0xF2, 2);
	printf(" [-] pmccfg: %.4x\n",pmccfg);
	if( pmccfg & 0x8 ){
		pmccfg &= ~0x8;
		pci_write_config(dev, 0xF2, pmccfg, 2);
		pmccfg = pci_read_config(dev, 0xF2, 2);
		if( pmccfg & 0x8 )
			printf("Could not enable Intel 801SMBus!\n");
		else
			printf("Enabled Intel 801SMBus\n");
	}
}

/* extract header type specific config data */

static void

			 * Skip quirked resources.
			 */
			for (q = &pci_quirks[0]; q->devid != 0; q++)
				if (q->devid == ((cfg->device << 16) | cfg->vendor)){
					if (q->type == PCI_QUIRK_MAP_REG)
						pci_add_map(bus, dev, q->arg1, rl, force, 0);
					else if (q->type == PCI_QUIRK_FIXUP_ROUTINE)
						q->fixup_func(dev);
				}
				if (q->devid == devid &&
				    q->type == PCI_QUIRK_UNMAP_REG &&
				    q->arg1 == PCIR_BAR(i))

Return to bug 139743

Lines 117-122 static void pci_mask_msix(device_t dev, Link Here

(-)sys/dev/pci/pci.c (-28 / +64 lines)
117	static void pci_unmask_msix(device_t dev, u_int index);	117	static void pci_unmask_msix(device_t dev, u_int index);
118	static int pci_msi_blacklisted(void);	118	static int pci_msi_blacklisted(void);
119	static int pci_msix_blacklisted(void);	119	static int pci_msix_blacklisted(void);
		120	static void pci_fix_asus_smbus(device_t dev);
120	static void pci_resume_msi(device_t dev);	121	static void pci_resume_msi(device_t dev);
121	static void pci_resume_msix(device_t dev);	122	static void pci_resume_msix(device_t dev);
122	static int pci_remap_intr_method(device_t bus, device_t dev,	123	static int pci_remap_intr_method(device_t bus, device_t dev,
Lines 224-277 struct pci_quirk { Link Here
224	#define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */	225	#define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */
225	#define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */	226	#define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
226	#define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */	227	#define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */
		228	#define PCI_QUIRK_FIXUP_ROUTINE 7 /* PCI needs a fix to continue */
227	int arg1;	229	int arg1;
228	int arg2;	230	int arg2;
		231	void (*fixup_func)(device_t dev);
229	};	232	};
230		233
231	static const struct pci_quirk pci_quirks[] = {	234	static const struct pci_quirk pci_quirks[] = {
232	/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */	235	/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
233	{ 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },	236	{ 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0, NULL },
234	{ 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },	237	{ 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0, NULL },
235	/* As does the Serverworks OSB4 (the SMBus mapping register) */	238	/* As does the Serverworks OSB4 (the SMBus mapping register) */
236	{ 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },	239	{ 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0, NULL },
237		240
238	/*	241	/*
239	* MSI doesn't work with the ServerWorks CNB20-HE Host Bridge	242	* MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
240	* or the CMIC-SL (AKA ServerWorks GC_LE).	243	* or the CMIC-SL (AKA ServerWorks GC_LE).
241	*/	244	*/
242	{ 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },	245	{ 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
243	{ 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },	246	{ 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
244		247
245	/*	248	/*
246	* MSI doesn't work on earlier Intel chipsets including	249	* MSI doesn't work on earlier Intel chipsets including
247	* E7500, E7501, E7505, 845, 865, 875/E7210, and 855.	250	* E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
248	*/	251	*/
249	{ 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	252	{ 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
250	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	253	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
251	{ 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	254	{ 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
252	{ 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	255	{ 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
253	{ 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	256	{ 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
254	{ 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	257	{ 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
255	{ 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	258	{ 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
256		259
257	/*	260	/*
258	* MSI doesn't work with devices behind the AMD 8131 HT-PCIX	261	* MSI doesn't work with devices behind the AMD 8131 HT-PCIX
259	* bridge.	262	* bridge.
260	*/	263	*/
261	{ 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },	264	{ 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
262		265
263	/*	266	/*
264	* MSI-X allocation doesn't work properly for devices passed through	267	* MSI-X allocation doesn't work properly for devices passed through
265	* by VMware up to at least ESXi 5.1.	268	* by VMware up to at least ESXi 5.1.
266	*/	269	*/
267	{ 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCI/PCI-X */	270	{ 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0, NULL }, /* PCI/PCI-X */
268	{ 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCIe */	271	{ 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0, NULL }, /* PCIe */
269		272
270	/*	273	/*
271	* Some virtualization environments emulate an older chipset	274	* Some virtualization environments emulate an older chipset
272	* but support MSI just fine. QEMU uses the Intel 82440.	275	* but support MSI just fine. QEMU uses the Intel 82440.
273	*/	276	*/
274	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },	277	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0, NULL },
275		278
276	/*	279	/*
277	* HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus	280	* HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus
Lines 281-309 static const struct pci_quirk pci_quirks Link Here
281	* For SB600 A21 and later, firmware must set the bit to hide it.	284	* For SB600 A21 and later, firmware must set the bit to hide it.
282	* For SB700 and later, it is unused and hardcoded to zero.	285	* For SB700 and later, it is unused and hardcoded to zero.
283	*/	286	*/
284	{ 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },	287	{ 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0, NULL },
285		288
286	/*	289	/*
287	* Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have	290	* Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have
288	* a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit	291	* a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit
289	* of the command register is set.	292	* of the command register is set.
290	*/	293	*/
291	{ 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	294	{ 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
292	{ 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	295	{ 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
293	{ 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	296	{ 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
294	{ 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	297	{ 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
295	{ 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	298	{ 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
296		299
297	/*	300	/*
298	* Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't	301	* Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't
299	* issue MSI interrupts with PCIM_CMD_INTxDIS set either.	302	* issue MSI interrupts with PCIM_CMD_INTxDIS set either.
300	*/	303	*/
301	{ 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */	304	{ 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5714 */
302	{ 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */	305	{ 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5714S */
303	{ 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */	306	{ 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5780 */
304	{ 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */	307	{ 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5780S */
305	{ 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */	308	{ 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5715 */
306	{ 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */	309	{ 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5715S */
		310
		311	/*
		312	* The ASUS P4B-motherboards needs a hack to enable the Intel 801SMBus
		313	*/
		314	{ 0x24408086, PCI_QUIRK_FIXUP_ROUTINE, 0, 0, &pci_fix_asus_smbus },
		315	{ 0x24C08086, PCI_QUIRK_FIXUP_ROUTINE, 0, 0, &pci_fix_asus_smbus },
307		316
308	{ 0 }	317	{ 0 }
309	};	318	};
Lines 589-594 pci_fixancient(pcicfgregs *cfg) Link Here
589	cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;	598	cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
590	}	599	}
591		600
		601	/* asus p4b/p4pe hack */
		602
		603	static void
		604	pci_fix_asus_smbus(device_t dev)
		605	{
		606	int pmccfg;
		607
		608	/* read subsystem vendor-id */
		609	pmccfg = pci_read_config(dev, 0xF2, 2);
		610	printf(" [-] pmccfg: %.4x\n",pmccfg);
		611	if( pmccfg & 0x8 ){
		612	pmccfg &= ~0x8;
		613	pci_write_config(dev, 0xF2, pmccfg, 2);
		614	pmccfg = pci_read_config(dev, 0xF2, 2);
		615	if( pmccfg & 0x8 )
		616	printf("Could not enable Intel 801SMBus!\n");
		617	else
		618	printf("Enabled Intel 801SMBus\n");
		619	}
		620	}
		621
592	/* extract header type specific config data */	622	/* extract header type specific config data */
593		623
594	static void	624	static void
Lines 3955-3960 pci_add_resources(device_t bus, device_t Link Here
3955	* Skip quirked resources.	3985	* Skip quirked resources.
3956	*/	3986	*/
3957	for (q = &pci_quirks[0]; q->devid != 0; q++)	3987	for (q = &pci_quirks[0]; q->devid != 0; q++)
		3988	if (q->devid == ((cfg->device << 16) \| cfg->vendor)){
		3989	if (q->type == PCI_QUIRK_MAP_REG)
		3990	pci_add_map(bus, dev, q->arg1, rl, force, 0);
		3991	else if (q->type == PCI_QUIRK_FIXUP_ROUTINE)
		3992	q->fixup_func(dev);
		3993	}
3958	if (q->devid == devid &&	3994	if (q->devid == devid &&
3959	q->type == PCI_QUIRK_UNMAP_REG &&	3995	q->type == PCI_QUIRK_UNMAP_REG &&
3960	q->arg1 == PCIR_BAR(i))	3996	q->arg1 == PCIR_BAR(i))