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(-)doc/en_US.ISO8859-1/books/developers-handbook/dma/chapter.sgml (-4 / +4 lines)
Lines 137-143 Link Here
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	which indicates that the counter has reached zero and no more data
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	which indicates that the counter has reached zero and no more data
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	will be transferred until the DMA controller is reprogrammed by the
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	will be transferred until the DMA controller is reprogrammed by the
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	CPU.  This event is also called the Terminal Count (TC). There is only
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	CPU.  This event is also called the Terminal Count (TC). There is only
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	one EOP signal, and since only DMA channel can be active at any
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	one EOP signal, and since only one DMA channel can be active at any
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	instant, the DMA channel that is currently active must be the DMA
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	instant, the DMA channel that is currently active must be the DMA
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	channel that just completed its task.</para>
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	channel that just completed its task.</para>
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Lines 155-161 Link Here
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      <para>It is important to understand that although the CPU always
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      <para>It is important to understand that although the CPU always
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	releases the bus to the DMA when the DMA makes the request, this
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	releases the bus to the DMA when the DMA makes the request, this
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	action is invisible to both applications and the operating systems,
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	action is invisible to both applications and the operating system,
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	except for slight changes in the amount of time the processor takes to
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	except for slight changes in the amount of time the processor takes to
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	execute instructions when the DMA is active. Subsequently, the
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	execute instructions when the DMA is active. Subsequently, the
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	processor must poll the peripheral, poll the registers in the DMA
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	processor must poll the peripheral, poll the registers in the DMA
Lines 226-232 Link Here
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      <note>
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      <note>
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	<para>A new implementation of the 8237, called the 82374, allows 16
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	<para>A new implementation of the 8237, called the 82374, allows 16
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	  bits of page register to be specified, allows access to the entire
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	  bits of page register to be specified and allows access to the entire
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	  32 bit address space, without the use of bounce buffers.</para>
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	  32 bit address space, without the use of bounce buffers.</para>
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      </note>
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      </note>
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    </sect2>
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    </sect2>
Lines 372-378 Link Here
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	      the peripheral requests transfers, they will be granted.  It is
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	      the peripheral requests transfers, they will be granted.  It is
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	      up to the CPU to move new data into the fixed buffer ahead of
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	      up to the CPU to move new data into the fixed buffer ahead of
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	      where the DMA is about to transfer it when doing output
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	      where the DMA is about to transfer it when doing output
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	      operations, and read new data out of the buffer behind where the
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	      operations, and to read new data out of the buffer behind where the
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	      DMA is writing when doing input operations.</para>
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	      DMA is writing when doing input operations.</para>
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	    <para>This technique is frequently used on audio devices that have
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	    <para>This technique is frequently used on audio devices that have

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