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Lines 161-167
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| 161 |
Static LIST_HEAD(, uhci_intr_info) uhci_ii_free; |
161 |
Static LIST_HEAD(, uhci_intr_info) uhci_ii_free; |
| 162 |
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| 163 |
Static void uhci_busreset(uhci_softc_t *); |
163 |
Static void uhci_busreset(uhci_softc_t *); |
| 164 |
Static void uhci_reset(uhci_softc_t *); |
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| 165 |
Static usbd_status uhci_run(uhci_softc_t *, int run); |
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Static usbd_status uhci_run(uhci_softc_t *, int run); |
| 166 |
Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); |
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Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); |
| 167 |
Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); |
166 |
Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); |
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Lines 280-287
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| 280 |
#define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) |
279 |
#define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) |
| 281 |
#define UHCISTS(sc) UREAD2(sc, UHCI_STS) |
280 |
#define UHCISTS(sc) UREAD2(sc, UHCI_STS) |
| 282 |
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281 |
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| 283 |
#define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ |
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| 284 |
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| 285 |
#define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) |
282 |
#define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) |
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283 |
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| 287 |
#define UHCI_INTR_ENDPT 1 |
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#define UHCI_INTR_ENDPT 1 |
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Lines 1473-1493
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| 1473 |
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1470 |
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| 1474 |
if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) |
1471 |
if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) |
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uhci_intr(sc); |
1472 |
uhci_intr(sc); |
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} |
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| 1477 |
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| 1478 |
void |
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uhci_reset(uhci_softc_t *sc) |
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{ |
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int n; |
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| 1483 |
UHCICMD(sc, UHCI_CMD_HCRESET); |
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/* The reset bit goes low when the controller is done. */ |
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for (n = 0; n < UHCI_RESET_TIMEOUT && |
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(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) |
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usb_delay_ms(&sc->sc_bus, 1); |
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if (n >= UHCI_RESET_TIMEOUT) |
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printf("%s: controller did not reset\n", |
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USBDEVNAME(sc->sc_bus.bdev)); |
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} |
1473 |
} |
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1474 |
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| 1493 |
usbd_status |
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usbd_status |