Attachment #201473 for bug #139743




static void		pci_unmask_msix(device_t dev, u_int index);
static int		pci_msi_blacklisted(void);
static int		pci_msix_blacklisted(void);
static void		pci_fix_asus_smbus(device_t dev);
static void		pci_resume_msi(device_t dev);
static void		pci_resume_msix(device_t dev);
static int		pci_remap_intr_method(device_t bus, device_t dev,

#define	PCI_QUIRK_UNMAP_REG	4 /* Ignore PCI map register */
#define	PCI_QUIRK_DISABLE_MSIX	5 /* MSI-X doesn't work */
#define	PCI_QUIRK_MSI_INTX_BUG	6 /* PCIM_CMD_INTxDIS disables MSI */
#define	PCI_QUIRK_FIXUP_ROUTINE	7 /* PCI needs a fix to continue */
	int	arg1;
	int	arg2;
	void (*fixup_func)(device_t dev);
};

static const struct pci_quirk pci_quirks[] = {
	/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
	{ 0x71138086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
	{ 0x719b8086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
	/* As does the Serverworks OSB4 (the SMBus mapping register) */
	{ 0x02001166, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },

	/*
	 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
	 * or the CMIC-SL (AKA ServerWorks GC_LE).
	 */
	{ 0x00141166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x00171166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

	/*
	 * MSI doesn't work on earlier Intel chipsets including
	 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
	 */
	{ 0x25408086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25508086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25608086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25708086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25788086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x35808086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

	/*
	 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
	 * bridge.
	 */
	{ 0x74501022, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

	/*
	 * MSI-X allocation doesn't work properly for devices passed through
	 * by VMware up to at least ESXi 5.1.
	 */
	{ 0x079015ad, PCI_QUIRK_DISABLE_MSIX,	0,	0, NULL }, /* PCI/PCI-X */
	{ 0x07a015ad, PCI_QUIRK_DISABLE_MSIX,	0,	0, NULL }, /* PCIe */

	/*
	 * Some virtualization environments emulate an older chipset
	 * but support MSI just fine.  QEMU uses the Intel 82440.
	 */
	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM,	0,	0, NULL },

	/*
	 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus

	 * For SB600 A21 and later, firmware must set the bit to hide it.
	 * For SB700 and later, it is unused and hardcoded to zero.
	 */
	{ 0x43851002, PCI_QUIRK_UNMAP_REG,	0x14,	0, NULL },

	/*
	 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have
	 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit
	 * of the command register is set.
	 */
	{ 0x10911969, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL },
	{ 0xE0911969, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL },
	{ 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL },
	{ 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL },
	{ 0x10901969, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL },

	/*
	 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't
	 * issue MSI interrupts with PCIM_CMD_INTxDIS set either.
	 */
	{ 0x166814e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5714 */
	{ 0x166914e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5714S */
	{ 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5780 */
	{ 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5780S */
	{ 0x167814e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5715 */
	{ 0x167914e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0, NULL }, /* BCM5715S */

	/*
	 * The ASUS P4B-motherboards needs a hack to enable the Intel 801SMBus
	 */
	{ 0x24408086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },
	{ 0x24C08086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },

	{ 0 }
};


		cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
}

/* asus p4b/p4pe hack */

static void
pci_fix_asus_smbus(device_t dev)
{
	int	pmccfg;

	/* read subsystem vendor-id */
	pmccfg = pci_read_config(dev, 0xF2, 2);
	printf(" [-] pmccfg: %.4x\n",pmccfg);
	if( pmccfg & 0x8 ){
		pmccfg &= ~0x8;
		pci_write_config(dev, 0xF2, pmccfg, 2);
		pmccfg = pci_read_config(dev, 0xF2, 2);
		if( pmccfg & 0x8 )
			printf("Could not enable Intel 801SMBus!\n");
		else
			printf("Enabled Intel 801SMBus\n");
	}
}

/* extract header type specific config data */

static void

			 * Skip quirked resources.
			 */
			for (q = &pci_quirks[0]; q->devid != 0; q++)
				if (q->devid == ((cfg->device << 16) | cfg->vendor)){
					if (q->type == PCI_QUIRK_MAP_REG)
						pci_add_map(bus, dev, q->arg1, rl, force, 0);
					else if (q->type == PCI_QUIRK_FIXUP_ROUTINE)
						q->fixup_func(dev);
				}
				if (q->devid == devid &&
				    q->type == PCI_QUIRK_UNMAP_REG &&
				    q->arg1 == PCIR_BAR(i))

Return to bug 139743

Lines 119-124 static void pci_mask_msix(device_t dev, u_int index); Link Here

(-)sys/dev/pci/pci.c (-28 / +64 lines)
119	static void pci_unmask_msix(device_t dev, u_int index);	119	static void pci_unmask_msix(device_t dev, u_int index);
120	static int pci_msi_blacklisted(void);	120	static int pci_msi_blacklisted(void);
121	static int pci_msix_blacklisted(void);	121	static int pci_msix_blacklisted(void);
		122	static void pci_fix_asus_smbus(device_t dev);
122	static void pci_resume_msi(device_t dev);	123	static void pci_resume_msi(device_t dev);
123	static void pci_resume_msix(device_t dev);	124	static void pci_resume_msix(device_t dev);
124	static int pci_remap_intr_method(device_t bus, device_t dev,	125	static int pci_remap_intr_method(device_t bus, device_t dev,
Lines 229-282 struct pci_quirk { Link Here
229	#define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */	230	#define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */
230	#define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */	231	#define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
231	#define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */	232	#define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */
		233	#define PCI_QUIRK_FIXUP_ROUTINE 7 /* PCI needs a fix to continue */
232	int arg1;	234	int arg1;
233	int arg2;	235	int arg2;
		236	void (*fixup_func)(device_t dev);
234	};	237	};
235		238
236	static const struct pci_quirk pci_quirks[] = {	239	static const struct pci_quirk pci_quirks[] = {
237	/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */	240	/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
238	{ 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },	241	{ 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0, NULL },
239	{ 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },	242	{ 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0, NULL },
240	/* As does the Serverworks OSB4 (the SMBus mapping register) */	243	/* As does the Serverworks OSB4 (the SMBus mapping register) */
241	{ 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },	244	{ 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0, NULL },
242		245
243	/*	246	/*
244	* MSI doesn't work with the ServerWorks CNB20-HE Host Bridge	247	* MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
245	* or the CMIC-SL (AKA ServerWorks GC_LE).	248	* or the CMIC-SL (AKA ServerWorks GC_LE).
246	*/	249	*/
247	{ 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },	250	{ 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
248	{ 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },	251	{ 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
249		252
250	/*	253	/*
251	* MSI doesn't work on earlier Intel chipsets including	254	* MSI doesn't work on earlier Intel chipsets including
252	* E7500, E7501, E7505, 845, 865, 875/E7210, and 855.	255	* E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
253	*/	256	*/
254	{ 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	257	{ 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
255	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	258	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
256	{ 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	259	{ 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
257	{ 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	260	{ 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
258	{ 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	261	{ 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
259	{ 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	262	{ 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
260	{ 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	263	{ 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
261		264
262	/*	265	/*
263	* MSI doesn't work with devices behind the AMD 8131 HT-PCIX	266	* MSI doesn't work with devices behind the AMD 8131 HT-PCIX
264	* bridge.	267	* bridge.
265	*/	268	*/
266	{ 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },	269	{ 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
267		270
268	/*	271	/*
269	* MSI-X allocation doesn't work properly for devices passed through	272	* MSI-X allocation doesn't work properly for devices passed through
270	* by VMware up to at least ESXi 5.1.	273	* by VMware up to at least ESXi 5.1.
271	*/	274	*/
272	{ 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCI/PCI-X */	275	{ 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0, NULL }, /* PCI/PCI-X */
273	{ 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCIe */	276	{ 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0, NULL }, /* PCIe */
274		277
275	/*	278	/*
276	* Some virtualization environments emulate an older chipset	279	* Some virtualization environments emulate an older chipset
277	* but support MSI just fine. QEMU uses the Intel 82440.	280	* but support MSI just fine. QEMU uses the Intel 82440.
278	*/	281	*/
279	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },	282	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0, NULL },
280		283
281	/*	284	/*
282	* HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus	285	* HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus
Lines 286-315 static const struct pci_quirk pci_quirks[] = { Link Here
286	* For SB600 A21 and later, firmware must set the bit to hide it.	289	* For SB600 A21 and later, firmware must set the bit to hide it.
287	* For SB700 and later, it is unused and hardcoded to zero.	290	* For SB700 and later, it is unused and hardcoded to zero.
288	*/	291	*/
289	{ 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },	292	{ 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0, NULL },
290		293
291	/*	294	/*
292	* Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have	295	* Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have
293	* a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit	296	* a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit
294	* of the command register is set.	297	* of the command register is set.
295	*/	298	*/
296	{ 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	299	{ 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
297	{ 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	300	{ 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
298	{ 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	301	{ 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
299	{ 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	302	{ 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
300	{ 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	303	{ 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
301		304
302	/*	305	/*
303	* Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't	306	* Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't
304	* issue MSI interrupts with PCIM_CMD_INTxDIS set either.	307	* issue MSI interrupts with PCIM_CMD_INTxDIS set either.
305	*/	308	*/
306	{ 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */	309	{ 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5714 */
307	{ 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */	310	{ 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5714S */
308	{ 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */	311	{ 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5780 */
309	{ 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */	312	{ 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5780S */
310	{ 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */	313	{ 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5715 */
311	{ 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */	314	{ 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5715S */
312		315
		316	/*
		317	* The ASUS P4B-motherboards needs a hack to enable the Intel 801SMBus
		318	*/
		319	{ 0x24408086, PCI_QUIRK_FIXUP_ROUTINE, 0, 0, &pci_fix_asus_smbus },
		320	{ 0x24C08086, PCI_QUIRK_FIXUP_ROUTINE, 0, 0, &pci_fix_asus_smbus },
		321
313	{ 0 }	322	{ 0 }
314	};	323	};
315		324
Lines 599-604 pci_fixancient(pcicfgregs *cfg) Link Here
599	cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;	608	cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
600	}	609	}
601		610
		611	/* asus p4b/p4pe hack */
		612
		613	static void
		614	pci_fix_asus_smbus(device_t dev)
		615	{
		616	int pmccfg;
		617
		618	/* read subsystem vendor-id */
		619	pmccfg = pci_read_config(dev, 0xF2, 2);
		620	printf(" [-] pmccfg: %.4x\n",pmccfg);
		621	if( pmccfg & 0x8 ){
		622	pmccfg &= ~0x8;
		623	pci_write_config(dev, 0xF2, pmccfg, 2);
		624	pmccfg = pci_read_config(dev, 0xF2, 2);
		625	if( pmccfg & 0x8 )
		626	printf("Could not enable Intel 801SMBus!\n");
		627	else
		628	printf("Enabled Intel 801SMBus\n");
		629	}
		630	}
		631
602	/* extract header type specific config data */	632	/* extract header type specific config data */
603		633
604	static void	634	static void
Lines 3973-3978 pci_add_resources(device_t bus, device_t dev, int forc Link Here
3973	* Skip quirked resources.	4003	* Skip quirked resources.
3974	*/	4004	*/
3975	for (q = &pci_quirks[0]; q->devid != 0; q++)	4005	for (q = &pci_quirks[0]; q->devid != 0; q++)
		4006	if (q->devid == ((cfg->device << 16) \| cfg->vendor)){
		4007	if (q->type == PCI_QUIRK_MAP_REG)
		4008	pci_add_map(bus, dev, q->arg1, rl, force, 0);
		4009	else if (q->type == PCI_QUIRK_FIXUP_ROUTINE)
		4010	q->fixup_func(dev);
		4011	}
3976	if (q->devid == devid &&	4012	if (q->devid == devid &&
3977	q->type == PCI_QUIRK_UNMAP_REG &&	4013	q->type == PCI_QUIRK_UNMAP_REG &&
3978	q->arg1 == PCIR_BAR(i))	4014	q->arg1 == PCIR_BAR(i))