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Lines 1414-1420
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| 1414 |
struct rl_softc *sc = xsc; |
1414 |
struct rl_softc *sc = xsc; |
| 1415 |
struct ifnet *ifp = &sc->arpcom.ac_if; |
1415 |
struct ifnet *ifp = &sc->arpcom.ac_if; |
| 1416 |
struct mii_data *mii; |
1416 |
struct mii_data *mii; |
| 1417 |
int s, i; |
1417 |
int s; |
| 1418 |
u_int32_t rxcfg = 0; |
1418 |
u_int32_t rxcfg = 0; |
| 1419 |
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1419 |
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| 1420 |
s = splimp(); |
1420 |
s = splimp(); |
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Lines 1426-1435
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| 1426 |
*/ |
1426 |
*/ |
| 1427 |
rl_stop(sc); |
1427 |
rl_stop(sc); |
| 1428 |
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1428 |
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| 1429 |
/* Init our MAC address */ |
1429 |
/* |
| 1430 |
for (i = 0; i < ETHER_ADDR_LEN; i++) { |
1430 |
* Init our MAC address. Even though the chipset |
| 1431 |
CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); |
1431 |
* documentation doesn't mention it, we need to enter "Config |
| 1432 |
} |
1432 |
* register write enable" mode to modify the ID registers. |
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1433 |
*/ |
| 1434 |
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); |
| 1435 |
CSR_WRITE_4(sc, RL_IDR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); |
| 1436 |
CSR_WRITE_4(sc, RL_IDR4, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); |
| 1437 |
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); |
| 1433 |
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1438 |
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| 1434 |
/* Init the RX buffer pointer register. */ |
1439 |
/* Init the RX buffer pointer register. */ |
| 1435 |
CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); |
1440 |
CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); |