|
Lines 270-276
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| 270 |
0x02, |
270 |
0x02, |
| 271 |
ResourceTemplate () |
271 |
ResourceTemplate () |
| 272 |
{ |
272 |
{ |
| 273 |
Register (PCC, |
273 |
Register (PlatformCommChannel, |
| 274 |
0x20, // Bit Width |
274 |
0x20, // Bit Width |
| 275 |
0x00, // Bit Offset |
275 |
0x00, // Bit Offset |
| 276 |
0x0000000000000000, // Address |
276 |
0x0000000000000000, // Address |
|
Lines 280-286
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| 280 |
|
280 |
|
| 281 |
ResourceTemplate () |
281 |
ResourceTemplate () |
| 282 |
{ |
282 |
{ |
| 283 |
Register (PCC, |
283 |
Register (PlatformCommChannel, |
| 284 |
0x20, // Bit Width |
284 |
0x20, // Bit Width |
| 285 |
0x00, // Bit Offset |
285 |
0x00, // Bit Offset |
| 286 |
0x0000000000000004, // Address |
286 |
0x0000000000000004, // Address |
|
Lines 290-296
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| 290 |
|
290 |
|
| 291 |
ResourceTemplate () |
291 |
ResourceTemplate () |
| 292 |
{ |
292 |
{ |
| 293 |
Register (PCC, |
293 |
Register (PlatformCommChannel, |
| 294 |
0x20, // Bit Width |
294 |
0x20, // Bit Width |
| 295 |
0x00, // Bit Offset |
295 |
0x00, // Bit Offset |
| 296 |
0x0000000000000008, // Address |
296 |
0x0000000000000008, // Address |
|
Lines 300-306
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|
| 300 |
|
300 |
|
| 301 |
ResourceTemplate () |
301 |
ResourceTemplate () |
| 302 |
{ |
302 |
{ |
| 303 |
Register (PCC, |
303 |
Register (PlatformCommChannel, |
| 304 |
0x20, // Bit Width |
304 |
0x20, // Bit Width |
| 305 |
0x00, // Bit Offset |
305 |
0x00, // Bit Offset |
| 306 |
0x000000000000000C, // Address |
306 |
0x000000000000000C, // Address |
|
Lines 310-316
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|
| 310 |
|
310 |
|
| 311 |
ResourceTemplate () |
311 |
ResourceTemplate () |
| 312 |
{ |
312 |
{ |
| 313 |
Register (PCC, |
313 |
Register (PlatformCommChannel, |
| 314 |
0x20, // Bit Width |
314 |
0x20, // Bit Width |
| 315 |
0x00, // Bit Offset |
315 |
0x00, // Bit Offset |
| 316 |
0x0000000000000010, // Address |
316 |
0x0000000000000010, // Address |
|
Lines 320-326
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|
| 320 |
|
320 |
|
| 321 |
ResourceTemplate () |
321 |
ResourceTemplate () |
| 322 |
{ |
322 |
{ |
| 323 |
Register (PCC, |
323 |
Register (PlatformCommChannel, |
| 324 |
0x20, // Bit Width |
324 |
0x20, // Bit Width |
| 325 |
0x00, // Bit Offset |
325 |
0x00, // Bit Offset |
| 326 |
0x0000000000000014, // Address |
326 |
0x0000000000000014, // Address |
|
Lines 375-381
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|
| 375 |
|
375 |
|
| 376 |
ResourceTemplate () |
376 |
ResourceTemplate () |
| 377 |
{ |
377 |
{ |
| 378 |
Register (PCC, |
378 |
Register (PlatformCommChannel, |
| 379 |
0x40, // Bit Width |
379 |
0x40, // Bit Width |
| 380 |
0x00, // Bit Offset |
380 |
0x00, // Bit Offset |
| 381 |
0x000000000000002C, // Address |
381 |
0x000000000000002C, // Address |
|
Lines 385-391
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|
| 385 |
|
385 |
|
| 386 |
ResourceTemplate () |
386 |
ResourceTemplate () |
| 387 |
{ |
387 |
{ |
| 388 |
Register (PCC, |
388 |
Register (PlatformCommChannel, |
| 389 |
0x40, // Bit Width |
389 |
0x40, // Bit Width |
| 390 |
0x00, // Bit Offset |
390 |
0x00, // Bit Offset |
| 391 |
0x0000000000000034, // Address |
391 |
0x0000000000000034, // Address |
|
Lines 440-446
Link Here
|
| 440 |
|
440 |
|
| 441 |
ResourceTemplate () |
441 |
ResourceTemplate () |
| 442 |
{ |
442 |
{ |
| 443 |
Register (PCC, |
443 |
Register (PlatformCommChannel, |
| 444 |
0x20, // Bit Width |
444 |
0x20, // Bit Width |
| 445 |
0x00, // Bit Offset |
445 |
0x00, // Bit Offset |
| 446 |
0x0000000000000050, // Address |
446 |
0x0000000000000050, // Address |
|
Lines 706-712
Link Here
|
| 706 |
0x02, |
706 |
0x02, |
| 707 |
ResourceTemplate () |
707 |
ResourceTemplate () |
| 708 |
{ |
708 |
{ |
| 709 |
Register (PCC, |
709 |
Register (PlatformCommChannel, |
| 710 |
0x20, // Bit Width |
710 |
0x20, // Bit Width |
| 711 |
0x00, // Bit Offset |
711 |
0x00, // Bit Offset |
| 712 |
0x0000000000000100, // Address |
712 |
0x0000000000000100, // Address |
|
Lines 716-722
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|
| 716 |
|
716 |
|
| 717 |
ResourceTemplate () |
717 |
ResourceTemplate () |
| 718 |
{ |
718 |
{ |
| 719 |
Register (PCC, |
719 |
Register (PlatformCommChannel, |
| 720 |
0x20, // Bit Width |
720 |
0x20, // Bit Width |
| 721 |
0x00, // Bit Offset |
721 |
0x00, // Bit Offset |
| 722 |
0x0000000000000104, // Address |
722 |
0x0000000000000104, // Address |
|
Lines 726-732
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|
| 726 |
|
726 |
|
| 727 |
ResourceTemplate () |
727 |
ResourceTemplate () |
| 728 |
{ |
728 |
{ |
| 729 |
Register (PCC, |
729 |
Register (PlatformCommChannel, |
| 730 |
0x20, // Bit Width |
730 |
0x20, // Bit Width |
| 731 |
0x00, // Bit Offset |
731 |
0x00, // Bit Offset |
| 732 |
0x0000000000000108, // Address |
732 |
0x0000000000000108, // Address |
|
Lines 736-742
Link Here
|
| 736 |
|
736 |
|
| 737 |
ResourceTemplate () |
737 |
ResourceTemplate () |
| 738 |
{ |
738 |
{ |
| 739 |
Register (PCC, |
739 |
Register (PlatformCommChannel, |
| 740 |
0x20, // Bit Width |
740 |
0x20, // Bit Width |
| 741 |
0x00, // Bit Offset |
741 |
0x00, // Bit Offset |
| 742 |
0x000000000000010C, // Address |
742 |
0x000000000000010C, // Address |
|
Lines 746-752
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|
| 746 |
|
746 |
|
| 747 |
ResourceTemplate () |
747 |
ResourceTemplate () |
| 748 |
{ |
748 |
{ |
| 749 |
Register (PCC, |
749 |
Register (PlatformCommChannel, |
| 750 |
0x20, // Bit Width |
750 |
0x20, // Bit Width |
| 751 |
0x00, // Bit Offset |
751 |
0x00, // Bit Offset |
| 752 |
0x0000000000000110, // Address |
752 |
0x0000000000000110, // Address |
|
Lines 756-762
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|
| 756 |
|
756 |
|
| 757 |
ResourceTemplate () |
757 |
ResourceTemplate () |
| 758 |
{ |
758 |
{ |
| 759 |
Register (PCC, |
759 |
Register (PlatformCommChannel, |
| 760 |
0x20, // Bit Width |
760 |
0x20, // Bit Width |
| 761 |
0x00, // Bit Offset |
761 |
0x00, // Bit Offset |
| 762 |
0x0000000000000114, // Address |
762 |
0x0000000000000114, // Address |
|
Lines 811-817
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|
| 811 |
|
811 |
|
| 812 |
ResourceTemplate () |
812 |
ResourceTemplate () |
| 813 |
{ |
813 |
{ |
| 814 |
Register (PCC, |
814 |
Register (PlatformCommChannel, |
| 815 |
0x40, // Bit Width |
815 |
0x40, // Bit Width |
| 816 |
0x00, // Bit Offset |
816 |
0x00, // Bit Offset |
| 817 |
0x000000000000012C, // Address |
817 |
0x000000000000012C, // Address |
|
Lines 821-827
Link Here
|
| 821 |
|
821 |
|
| 822 |
ResourceTemplate () |
822 |
ResourceTemplate () |
| 823 |
{ |
823 |
{ |
| 824 |
Register (PCC, |
824 |
Register (PlatformCommChannel, |
| 825 |
0x40, // Bit Width |
825 |
0x40, // Bit Width |
| 826 |
0x00, // Bit Offset |
826 |
0x00, // Bit Offset |
| 827 |
0x0000000000000134, // Address |
827 |
0x0000000000000134, // Address |
|
Lines 876-882
Link Here
|
| 876 |
|
876 |
|
| 877 |
ResourceTemplate () |
877 |
ResourceTemplate () |
| 878 |
{ |
878 |
{ |
| 879 |
Register (PCC, |
879 |
Register (PlatformCommChannel, |
| 880 |
0x20, // Bit Width |
880 |
0x20, // Bit Width |
| 881 |
0x00, // Bit Offset |
881 |
0x00, // Bit Offset |
| 882 |
0x0000000000000150, // Address |
882 |
0x0000000000000150, // Address |
|
Lines 1142-1148
Link Here
|
| 1142 |
0x02, |
1142 |
0x02, |
| 1143 |
ResourceTemplate () |
1143 |
ResourceTemplate () |
| 1144 |
{ |
1144 |
{ |
| 1145 |
Register (PCC, |
1145 |
Register (PlatformCommChannel, |
| 1146 |
0x20, // Bit Width |
1146 |
0x20, // Bit Width |
| 1147 |
0x00, // Bit Offset |
1147 |
0x00, // Bit Offset |
| 1148 |
0x0000000000000200, // Address |
1148 |
0x0000000000000200, // Address |
|
Lines 1152-1158
Link Here
|
| 1152 |
|
1152 |
|
| 1153 |
ResourceTemplate () |
1153 |
ResourceTemplate () |
| 1154 |
{ |
1154 |
{ |
| 1155 |
Register (PCC, |
1155 |
Register (PlatformCommChannel, |
| 1156 |
0x20, // Bit Width |
1156 |
0x20, // Bit Width |
| 1157 |
0x00, // Bit Offset |
1157 |
0x00, // Bit Offset |
| 1158 |
0x0000000000000204, // Address |
1158 |
0x0000000000000204, // Address |
|
Lines 1162-1168
Link Here
|
| 1162 |
|
1162 |
|
| 1163 |
ResourceTemplate () |
1163 |
ResourceTemplate () |
| 1164 |
{ |
1164 |
{ |
| 1165 |
Register (PCC, |
1165 |
Register (PlatformCommChannel, |
| 1166 |
0x20, // Bit Width |
1166 |
0x20, // Bit Width |
| 1167 |
0x00, // Bit Offset |
1167 |
0x00, // Bit Offset |
| 1168 |
0x0000000000000208, // Address |
1168 |
0x0000000000000208, // Address |
|
Lines 1172-1178
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|
| 1172 |
|
1172 |
|
| 1173 |
ResourceTemplate () |
1173 |
ResourceTemplate () |
| 1174 |
{ |
1174 |
{ |
| 1175 |
Register (PCC, |
1175 |
Register (PlatformCommChannel, |
| 1176 |
0x20, // Bit Width |
1176 |
0x20, // Bit Width |
| 1177 |
0x00, // Bit Offset |
1177 |
0x00, // Bit Offset |
| 1178 |
0x000000000000020C, // Address |
1178 |
0x000000000000020C, // Address |
|
Lines 1182-1188
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|
| 1182 |
|
1182 |
|
| 1183 |
ResourceTemplate () |
1183 |
ResourceTemplate () |
| 1184 |
{ |
1184 |
{ |
| 1185 |
Register (PCC, |
1185 |
Register (PlatformCommChannel, |
| 1186 |
0x20, // Bit Width |
1186 |
0x20, // Bit Width |
| 1187 |
0x00, // Bit Offset |
1187 |
0x00, // Bit Offset |
| 1188 |
0x0000000000000210, // Address |
1188 |
0x0000000000000210, // Address |
|
Lines 1192-1198
Link Here
|
| 1192 |
|
1192 |
|
| 1193 |
ResourceTemplate () |
1193 |
ResourceTemplate () |
| 1194 |
{ |
1194 |
{ |
| 1195 |
Register (PCC, |
1195 |
Register (PlatformCommChannel, |
| 1196 |
0x20, // Bit Width |
1196 |
0x20, // Bit Width |
| 1197 |
0x00, // Bit Offset |
1197 |
0x00, // Bit Offset |
| 1198 |
0x0000000000000214, // Address |
1198 |
0x0000000000000214, // Address |
|
Lines 1247-1253
Link Here
|
| 1247 |
|
1247 |
|
| 1248 |
ResourceTemplate () |
1248 |
ResourceTemplate () |
| 1249 |
{ |
1249 |
{ |
| 1250 |
Register (PCC, |
1250 |
Register (PlatformCommChannel, |
| 1251 |
0x40, // Bit Width |
1251 |
0x40, // Bit Width |
| 1252 |
0x00, // Bit Offset |
1252 |
0x00, // Bit Offset |
| 1253 |
0x000000000000022C, // Address |
1253 |
0x000000000000022C, // Address |
|
Lines 1257-1263
Link Here
|
| 1257 |
|
1257 |
|
| 1258 |
ResourceTemplate () |
1258 |
ResourceTemplate () |
| 1259 |
{ |
1259 |
{ |
| 1260 |
Register (PCC, |
1260 |
Register (PlatformCommChannel, |
| 1261 |
0x40, // Bit Width |
1261 |
0x40, // Bit Width |
| 1262 |
0x00, // Bit Offset |
1262 |
0x00, // Bit Offset |
| 1263 |
0x0000000000000234, // Address |
1263 |
0x0000000000000234, // Address |
|
Lines 1312-1318
Link Here
|
| 1312 |
|
1312 |
|
| 1313 |
ResourceTemplate () |
1313 |
ResourceTemplate () |
| 1314 |
{ |
1314 |
{ |
| 1315 |
Register (PCC, |
1315 |
Register (PlatformCommChannel, |
| 1316 |
0x20, // Bit Width |
1316 |
0x20, // Bit Width |
| 1317 |
0x00, // Bit Offset |
1317 |
0x00, // Bit Offset |
| 1318 |
0x0000000000000250, // Address |
1318 |
0x0000000000000250, // Address |
|
Lines 1578-1584
Link Here
|
| 1578 |
0x02, |
1578 |
0x02, |
| 1579 |
ResourceTemplate () |
1579 |
ResourceTemplate () |
| 1580 |
{ |
1580 |
{ |
| 1581 |
Register (PCC, |
1581 |
Register (PlatformCommChannel, |
| 1582 |
0x20, // Bit Width |
1582 |
0x20, // Bit Width |
| 1583 |
0x00, // Bit Offset |
1583 |
0x00, // Bit Offset |
| 1584 |
0x0000000000000300, // Address |
1584 |
0x0000000000000300, // Address |
|
Lines 1588-1594
Link Here
|
| 1588 |
|
1588 |
|
| 1589 |
ResourceTemplate () |
1589 |
ResourceTemplate () |
| 1590 |
{ |
1590 |
{ |
| 1591 |
Register (PCC, |
1591 |
Register (PlatformCommChannel, |
| 1592 |
0x20, // Bit Width |
1592 |
0x20, // Bit Width |
| 1593 |
0x00, // Bit Offset |
1593 |
0x00, // Bit Offset |
| 1594 |
0x0000000000000304, // Address |
1594 |
0x0000000000000304, // Address |
|
Lines 1598-1604
Link Here
|
| 1598 |
|
1598 |
|
| 1599 |
ResourceTemplate () |
1599 |
ResourceTemplate () |
| 1600 |
{ |
1600 |
{ |
| 1601 |
Register (PCC, |
1601 |
Register (PlatformCommChannel, |
| 1602 |
0x20, // Bit Width |
1602 |
0x20, // Bit Width |
| 1603 |
0x00, // Bit Offset |
1603 |
0x00, // Bit Offset |
| 1604 |
0x0000000000000308, // Address |
1604 |
0x0000000000000308, // Address |
|
Lines 1608-1614
Link Here
|
| 1608 |
|
1608 |
|
| 1609 |
ResourceTemplate () |
1609 |
ResourceTemplate () |
| 1610 |
{ |
1610 |
{ |
| 1611 |
Register (PCC, |
1611 |
Register (PlatformCommChannel, |
| 1612 |
0x20, // Bit Width |
1612 |
0x20, // Bit Width |
| 1613 |
0x00, // Bit Offset |
1613 |
0x00, // Bit Offset |
| 1614 |
0x000000000000030C, // Address |
1614 |
0x000000000000030C, // Address |
|
Lines 1618-1624
Link Here
|
| 1618 |
|
1618 |
|
| 1619 |
ResourceTemplate () |
1619 |
ResourceTemplate () |
| 1620 |
{ |
1620 |
{ |
| 1621 |
Register (PCC, |
1621 |
Register (PlatformCommChannel, |
| 1622 |
0x20, // Bit Width |
1622 |
0x20, // Bit Width |
| 1623 |
0x00, // Bit Offset |
1623 |
0x00, // Bit Offset |
| 1624 |
0x0000000000000310, // Address |
1624 |
0x0000000000000310, // Address |
|
Lines 1628-1634
Link Here
|
| 1628 |
|
1628 |
|
| 1629 |
ResourceTemplate () |
1629 |
ResourceTemplate () |
| 1630 |
{ |
1630 |
{ |
| 1631 |
Register (PCC, |
1631 |
Register (PlatformCommChannel, |
| 1632 |
0x20, // Bit Width |
1632 |
0x20, // Bit Width |
| 1633 |
0x00, // Bit Offset |
1633 |
0x00, // Bit Offset |
| 1634 |
0x0000000000000314, // Address |
1634 |
0x0000000000000314, // Address |
|
Lines 1683-1689
Link Here
|
| 1683 |
|
1683 |
|
| 1684 |
ResourceTemplate () |
1684 |
ResourceTemplate () |
| 1685 |
{ |
1685 |
{ |
| 1686 |
Register (PCC, |
1686 |
Register (PlatformCommChannel, |
| 1687 |
0x40, // Bit Width |
1687 |
0x40, // Bit Width |
| 1688 |
0x00, // Bit Offset |
1688 |
0x00, // Bit Offset |
| 1689 |
0x000000000000032C, // Address |
1689 |
0x000000000000032C, // Address |
|
Lines 1693-1699
Link Here
|
| 1693 |
|
1693 |
|
| 1694 |
ResourceTemplate () |
1694 |
ResourceTemplate () |
| 1695 |
{ |
1695 |
{ |
| 1696 |
Register (PCC, |
1696 |
Register (PlatformCommChannel, |
| 1697 |
0x40, // Bit Width |
1697 |
0x40, // Bit Width |
| 1698 |
0x00, // Bit Offset |
1698 |
0x00, // Bit Offset |
| 1699 |
0x0000000000000334, // Address |
1699 |
0x0000000000000334, // Address |
|
Lines 1748-1754
Link Here
|
| 1748 |
|
1748 |
|
| 1749 |
ResourceTemplate () |
1749 |
ResourceTemplate () |
| 1750 |
{ |
1750 |
{ |
| 1751 |
Register (PCC, |
1751 |
Register (PlatformCommChannel, |
| 1752 |
0x20, // Bit Width |
1752 |
0x20, // Bit Width |
| 1753 |
0x00, // Bit Offset |
1753 |
0x00, // Bit Offset |
| 1754 |
0x0000000000000350, // Address |
1754 |
0x0000000000000350, // Address |
|
Lines 2014-2020
Link Here
|
| 2014 |
0x02, |
2014 |
0x02, |
| 2015 |
ResourceTemplate () |
2015 |
ResourceTemplate () |
| 2016 |
{ |
2016 |
{ |
| 2017 |
Register (PCC, |
2017 |
Register (PlatformCommChannel, |
| 2018 |
0x20, // Bit Width |
2018 |
0x20, // Bit Width |
| 2019 |
0x00, // Bit Offset |
2019 |
0x00, // Bit Offset |
| 2020 |
0x0000000000000400, // Address |
2020 |
0x0000000000000400, // Address |
|
Lines 2024-2030
Link Here
|
| 2024 |
|
2024 |
|
| 2025 |
ResourceTemplate () |
2025 |
ResourceTemplate () |
| 2026 |
{ |
2026 |
{ |
| 2027 |
Register (PCC, |
2027 |
Register (PlatformCommChannel, |
| 2028 |
0x20, // Bit Width |
2028 |
0x20, // Bit Width |
| 2029 |
0x00, // Bit Offset |
2029 |
0x00, // Bit Offset |
| 2030 |
0x0000000000000404, // Address |
2030 |
0x0000000000000404, // Address |
|
Lines 2034-2040
Link Here
|
| 2034 |
|
2034 |
|
| 2035 |
ResourceTemplate () |
2035 |
ResourceTemplate () |
| 2036 |
{ |
2036 |
{ |
| 2037 |
Register (PCC, |
2037 |
Register (PlatformCommChannel, |
| 2038 |
0x20, // Bit Width |
2038 |
0x20, // Bit Width |
| 2039 |
0x00, // Bit Offset |
2039 |
0x00, // Bit Offset |
| 2040 |
0x0000000000000408, // Address |
2040 |
0x0000000000000408, // Address |
|
Lines 2044-2050
Link Here
|
| 2044 |
|
2044 |
|
| 2045 |
ResourceTemplate () |
2045 |
ResourceTemplate () |
| 2046 |
{ |
2046 |
{ |
| 2047 |
Register (PCC, |
2047 |
Register (PlatformCommChannel, |
| 2048 |
0x20, // Bit Width |
2048 |
0x20, // Bit Width |
| 2049 |
0x00, // Bit Offset |
2049 |
0x00, // Bit Offset |
| 2050 |
0x000000000000040C, // Address |
2050 |
0x000000000000040C, // Address |
|
Lines 2054-2060
Link Here
|
| 2054 |
|
2054 |
|
| 2055 |
ResourceTemplate () |
2055 |
ResourceTemplate () |
| 2056 |
{ |
2056 |
{ |
| 2057 |
Register (PCC, |
2057 |
Register (PlatformCommChannel, |
| 2058 |
0x20, // Bit Width |
2058 |
0x20, // Bit Width |
| 2059 |
0x00, // Bit Offset |
2059 |
0x00, // Bit Offset |
| 2060 |
0x0000000000000410, // Address |
2060 |
0x0000000000000410, // Address |
|
Lines 2064-2070
Link Here
|
| 2064 |
|
2064 |
|
| 2065 |
ResourceTemplate () |
2065 |
ResourceTemplate () |
| 2066 |
{ |
2066 |
{ |
| 2067 |
Register (PCC, |
2067 |
Register (PlatformCommChannel, |
| 2068 |
0x20, // Bit Width |
2068 |
0x20, // Bit Width |
| 2069 |
0x00, // Bit Offset |
2069 |
0x00, // Bit Offset |
| 2070 |
0x0000000000000414, // Address |
2070 |
0x0000000000000414, // Address |
|
Lines 2119-2125
Link Here
|
| 2119 |
|
2119 |
|
| 2120 |
ResourceTemplate () |
2120 |
ResourceTemplate () |
| 2121 |
{ |
2121 |
{ |
| 2122 |
Register (PCC, |
2122 |
Register (PlatformCommChannel, |
| 2123 |
0x40, // Bit Width |
2123 |
0x40, // Bit Width |
| 2124 |
0x00, // Bit Offset |
2124 |
0x00, // Bit Offset |
| 2125 |
0x000000000000042C, // Address |
2125 |
0x000000000000042C, // Address |
|
Lines 2129-2135
Link Here
|
| 2129 |
|
2129 |
|
| 2130 |
ResourceTemplate () |
2130 |
ResourceTemplate () |
| 2131 |
{ |
2131 |
{ |
| 2132 |
Register (PCC, |
2132 |
Register (PlatformCommChannel, |
| 2133 |
0x40, // Bit Width |
2133 |
0x40, // Bit Width |
| 2134 |
0x00, // Bit Offset |
2134 |
0x00, // Bit Offset |
| 2135 |
0x0000000000000434, // Address |
2135 |
0x0000000000000434, // Address |
|
Lines 2184-2190
Link Here
|
| 2184 |
|
2184 |
|
| 2185 |
ResourceTemplate () |
2185 |
ResourceTemplate () |
| 2186 |
{ |
2186 |
{ |
| 2187 |
Register (PCC, |
2187 |
Register (PlatformCommChannel, |
| 2188 |
0x20, // Bit Width |
2188 |
0x20, // Bit Width |
| 2189 |
0x00, // Bit Offset |
2189 |
0x00, // Bit Offset |
| 2190 |
0x0000000000000450, // Address |
2190 |
0x0000000000000450, // Address |
|
Lines 2450-2456
Link Here
|
| 2450 |
0x02, |
2450 |
0x02, |
| 2451 |
ResourceTemplate () |
2451 |
ResourceTemplate () |
| 2452 |
{ |
2452 |
{ |
| 2453 |
Register (PCC, |
2453 |
Register (PlatformCommChannel, |
| 2454 |
0x20, // Bit Width |
2454 |
0x20, // Bit Width |
| 2455 |
0x00, // Bit Offset |
2455 |
0x00, // Bit Offset |
| 2456 |
0x0000000000000500, // Address |
2456 |
0x0000000000000500, // Address |
|
Lines 2460-2466
Link Here
|
| 2460 |
|
2460 |
|
| 2461 |
ResourceTemplate () |
2461 |
ResourceTemplate () |
| 2462 |
{ |
2462 |
{ |
| 2463 |
Register (PCC, |
2463 |
Register (PlatformCommChannel, |
| 2464 |
0x20, // Bit Width |
2464 |
0x20, // Bit Width |
| 2465 |
0x00, // Bit Offset |
2465 |
0x00, // Bit Offset |
| 2466 |
0x0000000000000504, // Address |
2466 |
0x0000000000000504, // Address |
|
Lines 2470-2476
Link Here
|
| 2470 |
|
2470 |
|
| 2471 |
ResourceTemplate () |
2471 |
ResourceTemplate () |
| 2472 |
{ |
2472 |
{ |
| 2473 |
Register (PCC, |
2473 |
Register (PlatformCommChannel, |
| 2474 |
0x20, // Bit Width |
2474 |
0x20, // Bit Width |
| 2475 |
0x00, // Bit Offset |
2475 |
0x00, // Bit Offset |
| 2476 |
0x0000000000000508, // Address |
2476 |
0x0000000000000508, // Address |
|
Lines 2480-2486
Link Here
|
| 2480 |
|
2480 |
|
| 2481 |
ResourceTemplate () |
2481 |
ResourceTemplate () |
| 2482 |
{ |
2482 |
{ |
| 2483 |
Register (PCC, |
2483 |
Register (PlatformCommChannel, |
| 2484 |
0x20, // Bit Width |
2484 |
0x20, // Bit Width |
| 2485 |
0x00, // Bit Offset |
2485 |
0x00, // Bit Offset |
| 2486 |
0x000000000000050C, // Address |
2486 |
0x000000000000050C, // Address |
|
Lines 2490-2496
Link Here
|
| 2490 |
|
2490 |
|
| 2491 |
ResourceTemplate () |
2491 |
ResourceTemplate () |
| 2492 |
{ |
2492 |
{ |
| 2493 |
Register (PCC, |
2493 |
Register (PlatformCommChannel, |
| 2494 |
0x20, // Bit Width |
2494 |
0x20, // Bit Width |
| 2495 |
0x00, // Bit Offset |
2495 |
0x00, // Bit Offset |
| 2496 |
0x0000000000000510, // Address |
2496 |
0x0000000000000510, // Address |
|
Lines 2500-2506
Link Here
|
| 2500 |
|
2500 |
|
| 2501 |
ResourceTemplate () |
2501 |
ResourceTemplate () |
| 2502 |
{ |
2502 |
{ |
| 2503 |
Register (PCC, |
2503 |
Register (PlatformCommChannel, |
| 2504 |
0x20, // Bit Width |
2504 |
0x20, // Bit Width |
| 2505 |
0x00, // Bit Offset |
2505 |
0x00, // Bit Offset |
| 2506 |
0x0000000000000514, // Address |
2506 |
0x0000000000000514, // Address |
|
Lines 2555-2561
Link Here
|
| 2555 |
|
2555 |
|
| 2556 |
ResourceTemplate () |
2556 |
ResourceTemplate () |
| 2557 |
{ |
2557 |
{ |
| 2558 |
Register (PCC, |
2558 |
Register (PlatformCommChannel, |
| 2559 |
0x40, // Bit Width |
2559 |
0x40, // Bit Width |
| 2560 |
0x00, // Bit Offset |
2560 |
0x00, // Bit Offset |
| 2561 |
0x000000000000052C, // Address |
2561 |
0x000000000000052C, // Address |
|
Lines 2565-2571
Link Here
|
| 2565 |
|
2565 |
|
| 2566 |
ResourceTemplate () |
2566 |
ResourceTemplate () |
| 2567 |
{ |
2567 |
{ |
| 2568 |
Register (PCC, |
2568 |
Register (PlatformCommChannel, |
| 2569 |
0x40, // Bit Width |
2569 |
0x40, // Bit Width |
| 2570 |
0x00, // Bit Offset |
2570 |
0x00, // Bit Offset |
| 2571 |
0x0000000000000534, // Address |
2571 |
0x0000000000000534, // Address |
|
Lines 2620-2626
Link Here
|
| 2620 |
|
2620 |
|
| 2621 |
ResourceTemplate () |
2621 |
ResourceTemplate () |
| 2622 |
{ |
2622 |
{ |
| 2623 |
Register (PCC, |
2623 |
Register (PlatformCommChannel, |
| 2624 |
0x20, // Bit Width |
2624 |
0x20, // Bit Width |
| 2625 |
0x00, // Bit Offset |
2625 |
0x00, // Bit Offset |
| 2626 |
0x0000000000000550, // Address |
2626 |
0x0000000000000550, // Address |
|
Lines 2886-2892
Link Here
|
| 2886 |
0x02, |
2886 |
0x02, |
| 2887 |
ResourceTemplate () |
2887 |
ResourceTemplate () |
| 2888 |
{ |
2888 |
{ |
| 2889 |
Register (PCC, |
2889 |
Register (PlatformCommChannel, |
| 2890 |
0x20, // Bit Width |
2890 |
0x20, // Bit Width |
| 2891 |
0x00, // Bit Offset |
2891 |
0x00, // Bit Offset |
| 2892 |
0x0000000000000600, // Address |
2892 |
0x0000000000000600, // Address |
|
Lines 2896-2902
Link Here
|
| 2896 |
|
2896 |
|
| 2897 |
ResourceTemplate () |
2897 |
ResourceTemplate () |
| 2898 |
{ |
2898 |
{ |
| 2899 |
Register (PCC, |
2899 |
Register (PlatformCommChannel, |
| 2900 |
0x20, // Bit Width |
2900 |
0x20, // Bit Width |
| 2901 |
0x00, // Bit Offset |
2901 |
0x00, // Bit Offset |
| 2902 |
0x0000000000000604, // Address |
2902 |
0x0000000000000604, // Address |
|
Lines 2906-2912
Link Here
|
| 2906 |
|
2906 |
|
| 2907 |
ResourceTemplate () |
2907 |
ResourceTemplate () |
| 2908 |
{ |
2908 |
{ |
| 2909 |
Register (PCC, |
2909 |
Register (PlatformCommChannel, |
| 2910 |
0x20, // Bit Width |
2910 |
0x20, // Bit Width |
| 2911 |
0x00, // Bit Offset |
2911 |
0x00, // Bit Offset |
| 2912 |
0x0000000000000608, // Address |
2912 |
0x0000000000000608, // Address |
|
Lines 2916-2922
Link Here
|
| 2916 |
|
2916 |
|
| 2917 |
ResourceTemplate () |
2917 |
ResourceTemplate () |
| 2918 |
{ |
2918 |
{ |
| 2919 |
Register (PCC, |
2919 |
Register (PlatformCommChannel, |
| 2920 |
0x20, // Bit Width |
2920 |
0x20, // Bit Width |
| 2921 |
0x00, // Bit Offset |
2921 |
0x00, // Bit Offset |
| 2922 |
0x000000000000060C, // Address |
2922 |
0x000000000000060C, // Address |
|
Lines 2926-2932
Link Here
|
| 2926 |
|
2926 |
|
| 2927 |
ResourceTemplate () |
2927 |
ResourceTemplate () |
| 2928 |
{ |
2928 |
{ |
| 2929 |
Register (PCC, |
2929 |
Register (PlatformCommChannel, |
| 2930 |
0x20, // Bit Width |
2930 |
0x20, // Bit Width |
| 2931 |
0x00, // Bit Offset |
2931 |
0x00, // Bit Offset |
| 2932 |
0x0000000000000610, // Address |
2932 |
0x0000000000000610, // Address |
|
Lines 2936-2942
Link Here
|
| 2936 |
|
2936 |
|
| 2937 |
ResourceTemplate () |
2937 |
ResourceTemplate () |
| 2938 |
{ |
2938 |
{ |
| 2939 |
Register (PCC, |
2939 |
Register (PlatformCommChannel, |
| 2940 |
0x20, // Bit Width |
2940 |
0x20, // Bit Width |
| 2941 |
0x00, // Bit Offset |
2941 |
0x00, // Bit Offset |
| 2942 |
0x0000000000000614, // Address |
2942 |
0x0000000000000614, // Address |
|
Lines 2991-2997
Link Here
|
| 2991 |
|
2991 |
|
| 2992 |
ResourceTemplate () |
2992 |
ResourceTemplate () |
| 2993 |
{ |
2993 |
{ |
| 2994 |
Register (PCC, |
2994 |
Register (PlatformCommChannel, |
| 2995 |
0x40, // Bit Width |
2995 |
0x40, // Bit Width |
| 2996 |
0x00, // Bit Offset |
2996 |
0x00, // Bit Offset |
| 2997 |
0x000000000000062C, // Address |
2997 |
0x000000000000062C, // Address |
|
Lines 3001-3007
Link Here
|
| 3001 |
|
3001 |
|
| 3002 |
ResourceTemplate () |
3002 |
ResourceTemplate () |
| 3003 |
{ |
3003 |
{ |
| 3004 |
Register (PCC, |
3004 |
Register (PlatformCommChannel, |
| 3005 |
0x40, // Bit Width |
3005 |
0x40, // Bit Width |
| 3006 |
0x00, // Bit Offset |
3006 |
0x00, // Bit Offset |
| 3007 |
0x0000000000000634, // Address |
3007 |
0x0000000000000634, // Address |
|
Lines 3056-3062
Link Here
|
| 3056 |
|
3056 |
|
| 3057 |
ResourceTemplate () |
3057 |
ResourceTemplate () |
| 3058 |
{ |
3058 |
{ |
| 3059 |
Register (PCC, |
3059 |
Register (PlatformCommChannel, |
| 3060 |
0x20, // Bit Width |
3060 |
0x20, // Bit Width |
| 3061 |
0x00, // Bit Offset |
3061 |
0x00, // Bit Offset |
| 3062 |
0x0000000000000650, // Address |
3062 |
0x0000000000000650, // Address |
|
Lines 3322-3328
Link Here
|
| 3322 |
0x02, |
3322 |
0x02, |
| 3323 |
ResourceTemplate () |
3323 |
ResourceTemplate () |
| 3324 |
{ |
3324 |
{ |
| 3325 |
Register (PCC, |
3325 |
Register (PlatformCommChannel, |
| 3326 |
0x20, // Bit Width |
3326 |
0x20, // Bit Width |
| 3327 |
0x00, // Bit Offset |
3327 |
0x00, // Bit Offset |
| 3328 |
0x0000000000000700, // Address |
3328 |
0x0000000000000700, // Address |
|
Lines 3332-3338
Link Here
|
| 3332 |
|
3332 |
|
| 3333 |
ResourceTemplate () |
3333 |
ResourceTemplate () |
| 3334 |
{ |
3334 |
{ |
| 3335 |
Register (PCC, |
3335 |
Register (PlatformCommChannel, |
| 3336 |
0x20, // Bit Width |
3336 |
0x20, // Bit Width |
| 3337 |
0x00, // Bit Offset |
3337 |
0x00, // Bit Offset |
| 3338 |
0x0000000000000704, // Address |
3338 |
0x0000000000000704, // Address |
|
Lines 3342-3348
Link Here
|
| 3342 |
|
3342 |
|
| 3343 |
ResourceTemplate () |
3343 |
ResourceTemplate () |
| 3344 |
{ |
3344 |
{ |
| 3345 |
Register (PCC, |
3345 |
Register (PlatformCommChannel, |
| 3346 |
0x20, // Bit Width |
3346 |
0x20, // Bit Width |
| 3347 |
0x00, // Bit Offset |
3347 |
0x00, // Bit Offset |
| 3348 |
0x0000000000000708, // Address |
3348 |
0x0000000000000708, // Address |
|
Lines 3352-3358
Link Here
|
| 3352 |
|
3352 |
|
| 3353 |
ResourceTemplate () |
3353 |
ResourceTemplate () |
| 3354 |
{ |
3354 |
{ |
| 3355 |
Register (PCC, |
3355 |
Register (PlatformCommChannel, |
| 3356 |
0x20, // Bit Width |
3356 |
0x20, // Bit Width |
| 3357 |
0x00, // Bit Offset |
3357 |
0x00, // Bit Offset |
| 3358 |
0x000000000000070C, // Address |
3358 |
0x000000000000070C, // Address |
|
Lines 3362-3368
Link Here
|
| 3362 |
|
3362 |
|
| 3363 |
ResourceTemplate () |
3363 |
ResourceTemplate () |
| 3364 |
{ |
3364 |
{ |
| 3365 |
Register (PCC, |
3365 |
Register (PlatformCommChannel, |
| 3366 |
0x20, // Bit Width |
3366 |
0x20, // Bit Width |
| 3367 |
0x00, // Bit Offset |
3367 |
0x00, // Bit Offset |
| 3368 |
0x0000000000000710, // Address |
3368 |
0x0000000000000710, // Address |
|
Lines 3372-3378
Link Here
|
| 3372 |
|
3372 |
|
| 3373 |
ResourceTemplate () |
3373 |
ResourceTemplate () |
| 3374 |
{ |
3374 |
{ |
| 3375 |
Register (PCC, |
3375 |
Register (PlatformCommChannel, |
| 3376 |
0x20, // Bit Width |
3376 |
0x20, // Bit Width |
| 3377 |
0x00, // Bit Offset |
3377 |
0x00, // Bit Offset |
| 3378 |
0x0000000000000714, // Address |
3378 |
0x0000000000000714, // Address |
|
Lines 3427-3433
Link Here
|
| 3427 |
|
3427 |
|
| 3428 |
ResourceTemplate () |
3428 |
ResourceTemplate () |
| 3429 |
{ |
3429 |
{ |
| 3430 |
Register (PCC, |
3430 |
Register (PlatformCommChannel, |
| 3431 |
0x40, // Bit Width |
3431 |
0x40, // Bit Width |
| 3432 |
0x00, // Bit Offset |
3432 |
0x00, // Bit Offset |
| 3433 |
0x000000000000072C, // Address |
3433 |
0x000000000000072C, // Address |
|
Lines 3437-3443
Link Here
|
| 3437 |
|
3437 |
|
| 3438 |
ResourceTemplate () |
3438 |
ResourceTemplate () |
| 3439 |
{ |
3439 |
{ |
| 3440 |
Register (PCC, |
3440 |
Register (PlatformCommChannel, |
| 3441 |
0x40, // Bit Width |
3441 |
0x40, // Bit Width |
| 3442 |
0x00, // Bit Offset |
3442 |
0x00, // Bit Offset |
| 3443 |
0x0000000000000734, // Address |
3443 |
0x0000000000000734, // Address |
|
Lines 3492-3498
Link Here
|
| 3492 |
|
3492 |
|
| 3493 |
ResourceTemplate () |
3493 |
ResourceTemplate () |
| 3494 |
{ |
3494 |
{ |
| 3495 |
Register (PCC, |
3495 |
Register (PlatformCommChannel, |
| 3496 |
0x20, // Bit Width |
3496 |
0x20, // Bit Width |
| 3497 |
0x00, // Bit Offset |
3497 |
0x00, // Bit Offset |
| 3498 |
0x0000000000000750, // Address |
3498 |
0x0000000000000750, // Address |
|
Lines 3758-3764
Link Here
|
| 3758 |
0x02, |
3758 |
0x02, |
| 3759 |
ResourceTemplate () |
3759 |
ResourceTemplate () |
| 3760 |
{ |
3760 |
{ |
| 3761 |
Register (PCC, |
3761 |
Register (PlatformCommChannel, |
| 3762 |
0x20, // Bit Width |
3762 |
0x20, // Bit Width |
| 3763 |
0x00, // Bit Offset |
3763 |
0x00, // Bit Offset |
| 3764 |
0x0000000000000800, // Address |
3764 |
0x0000000000000800, // Address |
|
Lines 3768-3774
Link Here
|
| 3768 |
|
3768 |
|
| 3769 |
ResourceTemplate () |
3769 |
ResourceTemplate () |
| 3770 |
{ |
3770 |
{ |
| 3771 |
Register (PCC, |
3771 |
Register (PlatformCommChannel, |
| 3772 |
0x20, // Bit Width |
3772 |
0x20, // Bit Width |
| 3773 |
0x00, // Bit Offset |
3773 |
0x00, // Bit Offset |
| 3774 |
0x0000000000000804, // Address |
3774 |
0x0000000000000804, // Address |
|
Lines 3778-3784
Link Here
|
| 3778 |
|
3778 |
|
| 3779 |
ResourceTemplate () |
3779 |
ResourceTemplate () |
| 3780 |
{ |
3780 |
{ |
| 3781 |
Register (PCC, |
3781 |
Register (PlatformCommChannel, |
| 3782 |
0x20, // Bit Width |
3782 |
0x20, // Bit Width |
| 3783 |
0x00, // Bit Offset |
3783 |
0x00, // Bit Offset |
| 3784 |
0x0000000000000808, // Address |
3784 |
0x0000000000000808, // Address |
|
Lines 3788-3794
Link Here
|
| 3788 |
|
3788 |
|
| 3789 |
ResourceTemplate () |
3789 |
ResourceTemplate () |
| 3790 |
{ |
3790 |
{ |
| 3791 |
Register (PCC, |
3791 |
Register (PlatformCommChannel, |
| 3792 |
0x20, // Bit Width |
3792 |
0x20, // Bit Width |
| 3793 |
0x00, // Bit Offset |
3793 |
0x00, // Bit Offset |
| 3794 |
0x000000000000080C, // Address |
3794 |
0x000000000000080C, // Address |
|
Lines 3798-3804
Link Here
|
| 3798 |
|
3798 |
|
| 3799 |
ResourceTemplate () |
3799 |
ResourceTemplate () |
| 3800 |
{ |
3800 |
{ |
| 3801 |
Register (PCC, |
3801 |
Register (PlatformCommChannel, |
| 3802 |
0x20, // Bit Width |
3802 |
0x20, // Bit Width |
| 3803 |
0x00, // Bit Offset |
3803 |
0x00, // Bit Offset |
| 3804 |
0x0000000000000810, // Address |
3804 |
0x0000000000000810, // Address |
|
Lines 3808-3814
Link Here
|
| 3808 |
|
3808 |
|
| 3809 |
ResourceTemplate () |
3809 |
ResourceTemplate () |
| 3810 |
{ |
3810 |
{ |
| 3811 |
Register (PCC, |
3811 |
Register (PlatformCommChannel, |
| 3812 |
0x20, // Bit Width |
3812 |
0x20, // Bit Width |
| 3813 |
0x00, // Bit Offset |
3813 |
0x00, // Bit Offset |
| 3814 |
0x0000000000000814, // Address |
3814 |
0x0000000000000814, // Address |
|
Lines 3863-3869
Link Here
|
| 3863 |
|
3863 |
|
| 3864 |
ResourceTemplate () |
3864 |
ResourceTemplate () |
| 3865 |
{ |
3865 |
{ |
| 3866 |
Register (PCC, |
3866 |
Register (PlatformCommChannel, |
| 3867 |
0x40, // Bit Width |
3867 |
0x40, // Bit Width |
| 3868 |
0x00, // Bit Offset |
3868 |
0x00, // Bit Offset |
| 3869 |
0x000000000000082C, // Address |
3869 |
0x000000000000082C, // Address |
|
Lines 3873-3879
Link Here
|
| 3873 |
|
3873 |
|
| 3874 |
ResourceTemplate () |
3874 |
ResourceTemplate () |
| 3875 |
{ |
3875 |
{ |
| 3876 |
Register (PCC, |
3876 |
Register (PlatformCommChannel, |
| 3877 |
0x40, // Bit Width |
3877 |
0x40, // Bit Width |
| 3878 |
0x00, // Bit Offset |
3878 |
0x00, // Bit Offset |
| 3879 |
0x0000000000000834, // Address |
3879 |
0x0000000000000834, // Address |
|
Lines 3928-3934
Link Here
|
| 3928 |
|
3928 |
|
| 3929 |
ResourceTemplate () |
3929 |
ResourceTemplate () |
| 3930 |
{ |
3930 |
{ |
| 3931 |
Register (PCC, |
3931 |
Register (PlatformCommChannel, |
| 3932 |
0x20, // Bit Width |
3932 |
0x20, // Bit Width |
| 3933 |
0x00, // Bit Offset |
3933 |
0x00, // Bit Offset |
| 3934 |
0x0000000000000850, // Address |
3934 |
0x0000000000000850, // Address |
|
Lines 4194-4200
Link Here
|
| 4194 |
0x02, |
4194 |
0x02, |
| 4195 |
ResourceTemplate () |
4195 |
ResourceTemplate () |
| 4196 |
{ |
4196 |
{ |
| 4197 |
Register (PCC, |
4197 |
Register (PlatformCommChannel, |
| 4198 |
0x20, // Bit Width |
4198 |
0x20, // Bit Width |
| 4199 |
0x00, // Bit Offset |
4199 |
0x00, // Bit Offset |
| 4200 |
0x0000000000000900, // Address |
4200 |
0x0000000000000900, // Address |
|
Lines 4204-4210
Link Here
|
| 4204 |
|
4204 |
|
| 4205 |
ResourceTemplate () |
4205 |
ResourceTemplate () |
| 4206 |
{ |
4206 |
{ |
| 4207 |
Register (PCC, |
4207 |
Register (PlatformCommChannel, |
| 4208 |
0x20, // Bit Width |
4208 |
0x20, // Bit Width |
| 4209 |
0x00, // Bit Offset |
4209 |
0x00, // Bit Offset |
| 4210 |
0x0000000000000904, // Address |
4210 |
0x0000000000000904, // Address |
|
Lines 4214-4220
Link Here
|
| 4214 |
|
4214 |
|
| 4215 |
ResourceTemplate () |
4215 |
ResourceTemplate () |
| 4216 |
{ |
4216 |
{ |
| 4217 |
Register (PCC, |
4217 |
Register (PlatformCommChannel, |
| 4218 |
0x20, // Bit Width |
4218 |
0x20, // Bit Width |
| 4219 |
0x00, // Bit Offset |
4219 |
0x00, // Bit Offset |
| 4220 |
0x0000000000000908, // Address |
4220 |
0x0000000000000908, // Address |
|
Lines 4224-4230
Link Here
|
| 4224 |
|
4224 |
|
| 4225 |
ResourceTemplate () |
4225 |
ResourceTemplate () |
| 4226 |
{ |
4226 |
{ |
| 4227 |
Register (PCC, |
4227 |
Register (PlatformCommChannel, |
| 4228 |
0x20, // Bit Width |
4228 |
0x20, // Bit Width |
| 4229 |
0x00, // Bit Offset |
4229 |
0x00, // Bit Offset |
| 4230 |
0x000000000000090C, // Address |
4230 |
0x000000000000090C, // Address |
|
Lines 4234-4240
Link Here
|
| 4234 |
|
4234 |
|
| 4235 |
ResourceTemplate () |
4235 |
ResourceTemplate () |
| 4236 |
{ |
4236 |
{ |
| 4237 |
Register (PCC, |
4237 |
Register (PlatformCommChannel, |
| 4238 |
0x20, // Bit Width |
4238 |
0x20, // Bit Width |
| 4239 |
0x00, // Bit Offset |
4239 |
0x00, // Bit Offset |
| 4240 |
0x0000000000000910, // Address |
4240 |
0x0000000000000910, // Address |
|
Lines 4244-4250
Link Here
|
| 4244 |
|
4244 |
|
| 4245 |
ResourceTemplate () |
4245 |
ResourceTemplate () |
| 4246 |
{ |
4246 |
{ |
| 4247 |
Register (PCC, |
4247 |
Register (PlatformCommChannel, |
| 4248 |
0x20, // Bit Width |
4248 |
0x20, // Bit Width |
| 4249 |
0x00, // Bit Offset |
4249 |
0x00, // Bit Offset |
| 4250 |
0x0000000000000914, // Address |
4250 |
0x0000000000000914, // Address |
|
Lines 4299-4305
Link Here
|
| 4299 |
|
4299 |
|
| 4300 |
ResourceTemplate () |
4300 |
ResourceTemplate () |
| 4301 |
{ |
4301 |
{ |
| 4302 |
Register (PCC, |
4302 |
Register (PlatformCommChannel, |
| 4303 |
0x40, // Bit Width |
4303 |
0x40, // Bit Width |
| 4304 |
0x00, // Bit Offset |
4304 |
0x00, // Bit Offset |
| 4305 |
0x000000000000092C, // Address |
4305 |
0x000000000000092C, // Address |
|
Lines 4309-4315
Link Here
|
| 4309 |
|
4309 |
|
| 4310 |
ResourceTemplate () |
4310 |
ResourceTemplate () |
| 4311 |
{ |
4311 |
{ |
| 4312 |
Register (PCC, |
4312 |
Register (PlatformCommChannel, |
| 4313 |
0x40, // Bit Width |
4313 |
0x40, // Bit Width |
| 4314 |
0x00, // Bit Offset |
4314 |
0x00, // Bit Offset |
| 4315 |
0x0000000000000934, // Address |
4315 |
0x0000000000000934, // Address |
|
Lines 4364-4370
Link Here
|
| 4364 |
|
4364 |
|
| 4365 |
ResourceTemplate () |
4365 |
ResourceTemplate () |
| 4366 |
{ |
4366 |
{ |
| 4367 |
Register (PCC, |
4367 |
Register (PlatformCommChannel, |
| 4368 |
0x20, // Bit Width |
4368 |
0x20, // Bit Width |
| 4369 |
0x00, // Bit Offset |
4369 |
0x00, // Bit Offset |
| 4370 |
0x0000000000000950, // Address |
4370 |
0x0000000000000950, // Address |
|
Lines 4630-4636
Link Here
|
| 4630 |
0x02, |
4630 |
0x02, |
| 4631 |
ResourceTemplate () |
4631 |
ResourceTemplate () |
| 4632 |
{ |
4632 |
{ |
| 4633 |
Register (PCC, |
4633 |
Register (PlatformCommChannel, |
| 4634 |
0x20, // Bit Width |
4634 |
0x20, // Bit Width |
| 4635 |
0x00, // Bit Offset |
4635 |
0x00, // Bit Offset |
| 4636 |
0x0000000000000A00, // Address |
4636 |
0x0000000000000A00, // Address |
|
Lines 4640-4646
Link Here
|
| 4640 |
|
4640 |
|
| 4641 |
ResourceTemplate () |
4641 |
ResourceTemplate () |
| 4642 |
{ |
4642 |
{ |
| 4643 |
Register (PCC, |
4643 |
Register (PlatformCommChannel, |
| 4644 |
0x20, // Bit Width |
4644 |
0x20, // Bit Width |
| 4645 |
0x00, // Bit Offset |
4645 |
0x00, // Bit Offset |
| 4646 |
0x0000000000000A04, // Address |
4646 |
0x0000000000000A04, // Address |
|
Lines 4650-4656
Link Here
|
| 4650 |
|
4650 |
|
| 4651 |
ResourceTemplate () |
4651 |
ResourceTemplate () |
| 4652 |
{ |
4652 |
{ |
| 4653 |
Register (PCC, |
4653 |
Register (PlatformCommChannel, |
| 4654 |
0x20, // Bit Width |
4654 |
0x20, // Bit Width |
| 4655 |
0x00, // Bit Offset |
4655 |
0x00, // Bit Offset |
| 4656 |
0x0000000000000A08, // Address |
4656 |
0x0000000000000A08, // Address |
|
Lines 4660-4666
Link Here
|
| 4660 |
|
4660 |
|
| 4661 |
ResourceTemplate () |
4661 |
ResourceTemplate () |
| 4662 |
{ |
4662 |
{ |
| 4663 |
Register (PCC, |
4663 |
Register (PlatformCommChannel, |
| 4664 |
0x20, // Bit Width |
4664 |
0x20, // Bit Width |
| 4665 |
0x00, // Bit Offset |
4665 |
0x00, // Bit Offset |
| 4666 |
0x0000000000000A0C, // Address |
4666 |
0x0000000000000A0C, // Address |
|
Lines 4670-4676
Link Here
|
| 4670 |
|
4670 |
|
| 4671 |
ResourceTemplate () |
4671 |
ResourceTemplate () |
| 4672 |
{ |
4672 |
{ |
| 4673 |
Register (PCC, |
4673 |
Register (PlatformCommChannel, |
| 4674 |
0x20, // Bit Width |
4674 |
0x20, // Bit Width |
| 4675 |
0x00, // Bit Offset |
4675 |
0x00, // Bit Offset |
| 4676 |
0x0000000000000A10, // Address |
4676 |
0x0000000000000A10, // Address |
|
Lines 4680-4686
Link Here
|
| 4680 |
|
4680 |
|
| 4681 |
ResourceTemplate () |
4681 |
ResourceTemplate () |
| 4682 |
{ |
4682 |
{ |
| 4683 |
Register (PCC, |
4683 |
Register (PlatformCommChannel, |
| 4684 |
0x20, // Bit Width |
4684 |
0x20, // Bit Width |
| 4685 |
0x00, // Bit Offset |
4685 |
0x00, // Bit Offset |
| 4686 |
0x0000000000000A14, // Address |
4686 |
0x0000000000000A14, // Address |
|
Lines 4735-4741
Link Here
|
| 4735 |
|
4735 |
|
| 4736 |
ResourceTemplate () |
4736 |
ResourceTemplate () |
| 4737 |
{ |
4737 |
{ |
| 4738 |
Register (PCC, |
4738 |
Register (PlatformCommChannel, |
| 4739 |
0x40, // Bit Width |
4739 |
0x40, // Bit Width |
| 4740 |
0x00, // Bit Offset |
4740 |
0x00, // Bit Offset |
| 4741 |
0x0000000000000A2C, // Address |
4741 |
0x0000000000000A2C, // Address |
|
Lines 4745-4751
Link Here
|
| 4745 |
|
4745 |
|
| 4746 |
ResourceTemplate () |
4746 |
ResourceTemplate () |
| 4747 |
{ |
4747 |
{ |
| 4748 |
Register (PCC, |
4748 |
Register (PlatformCommChannel, |
| 4749 |
0x40, // Bit Width |
4749 |
0x40, // Bit Width |
| 4750 |
0x00, // Bit Offset |
4750 |
0x00, // Bit Offset |
| 4751 |
0x0000000000000A34, // Address |
4751 |
0x0000000000000A34, // Address |
|
Lines 4800-4806
Link Here
|
| 4800 |
|
4800 |
|
| 4801 |
ResourceTemplate () |
4801 |
ResourceTemplate () |
| 4802 |
{ |
4802 |
{ |
| 4803 |
Register (PCC, |
4803 |
Register (PlatformCommChannel, |
| 4804 |
0x20, // Bit Width |
4804 |
0x20, // Bit Width |
| 4805 |
0x00, // Bit Offset |
4805 |
0x00, // Bit Offset |
| 4806 |
0x0000000000000A50, // Address |
4806 |
0x0000000000000A50, // Address |
|
Lines 5066-5072
Link Here
|
| 5066 |
0x02, |
5066 |
0x02, |
| 5067 |
ResourceTemplate () |
5067 |
ResourceTemplate () |
| 5068 |
{ |
5068 |
{ |
| 5069 |
Register (PCC, |
5069 |
Register (PlatformCommChannel, |
| 5070 |
0x20, // Bit Width |
5070 |
0x20, // Bit Width |
| 5071 |
0x00, // Bit Offset |
5071 |
0x00, // Bit Offset |
| 5072 |
0x0000000000000B00, // Address |
5072 |
0x0000000000000B00, // Address |
|
Lines 5076-5082
Link Here
|
| 5076 |
|
5076 |
|
| 5077 |
ResourceTemplate () |
5077 |
ResourceTemplate () |
| 5078 |
{ |
5078 |
{ |
| 5079 |
Register (PCC, |
5079 |
Register (PlatformCommChannel, |
| 5080 |
0x20, // Bit Width |
5080 |
0x20, // Bit Width |
| 5081 |
0x00, // Bit Offset |
5081 |
0x00, // Bit Offset |
| 5082 |
0x0000000000000B04, // Address |
5082 |
0x0000000000000B04, // Address |
|
Lines 5086-5092
Link Here
|
| 5086 |
|
5086 |
|
| 5087 |
ResourceTemplate () |
5087 |
ResourceTemplate () |
| 5088 |
{ |
5088 |
{ |
| 5089 |
Register (PCC, |
5089 |
Register (PlatformCommChannel, |
| 5090 |
0x20, // Bit Width |
5090 |
0x20, // Bit Width |
| 5091 |
0x00, // Bit Offset |
5091 |
0x00, // Bit Offset |
| 5092 |
0x0000000000000B08, // Address |
5092 |
0x0000000000000B08, // Address |
|
Lines 5096-5102
Link Here
|
| 5096 |
|
5096 |
|
| 5097 |
ResourceTemplate () |
5097 |
ResourceTemplate () |
| 5098 |
{ |
5098 |
{ |
| 5099 |
Register (PCC, |
5099 |
Register (PlatformCommChannel, |
| 5100 |
0x20, // Bit Width |
5100 |
0x20, // Bit Width |
| 5101 |
0x00, // Bit Offset |
5101 |
0x00, // Bit Offset |
| 5102 |
0x0000000000000B0C, // Address |
5102 |
0x0000000000000B0C, // Address |
|
Lines 5106-5112
Link Here
|
| 5106 |
|
5106 |
|
| 5107 |
ResourceTemplate () |
5107 |
ResourceTemplate () |
| 5108 |
{ |
5108 |
{ |
| 5109 |
Register (PCC, |
5109 |
Register (PlatformCommChannel, |
| 5110 |
0x20, // Bit Width |
5110 |
0x20, // Bit Width |
| 5111 |
0x00, // Bit Offset |
5111 |
0x00, // Bit Offset |
| 5112 |
0x0000000000000B10, // Address |
5112 |
0x0000000000000B10, // Address |
|
Lines 5116-5122
Link Here
|
| 5116 |
|
5116 |
|
| 5117 |
ResourceTemplate () |
5117 |
ResourceTemplate () |
| 5118 |
{ |
5118 |
{ |
| 5119 |
Register (PCC, |
5119 |
Register (PlatformCommChannel, |
| 5120 |
0x20, // Bit Width |
5120 |
0x20, // Bit Width |
| 5121 |
0x00, // Bit Offset |
5121 |
0x00, // Bit Offset |
| 5122 |
0x0000000000000B14, // Address |
5122 |
0x0000000000000B14, // Address |
|
Lines 5171-5177
Link Here
|
| 5171 |
|
5171 |
|
| 5172 |
ResourceTemplate () |
5172 |
ResourceTemplate () |
| 5173 |
{ |
5173 |
{ |
| 5174 |
Register (PCC, |
5174 |
Register (PlatformCommChannel, |
| 5175 |
0x40, // Bit Width |
5175 |
0x40, // Bit Width |
| 5176 |
0x00, // Bit Offset |
5176 |
0x00, // Bit Offset |
| 5177 |
0x0000000000000B2C, // Address |
5177 |
0x0000000000000B2C, // Address |
|
Lines 5181-5187
Link Here
|
| 5181 |
|
5181 |
|
| 5182 |
ResourceTemplate () |
5182 |
ResourceTemplate () |
| 5183 |
{ |
5183 |
{ |
| 5184 |
Register (PCC, |
5184 |
Register (PlatformCommChannel, |
| 5185 |
0x40, // Bit Width |
5185 |
0x40, // Bit Width |
| 5186 |
0x00, // Bit Offset |
5186 |
0x00, // Bit Offset |
| 5187 |
0x0000000000000B34, // Address |
5187 |
0x0000000000000B34, // Address |
|
Lines 5236-5242
Link Here
|
| 5236 |
|
5236 |
|
| 5237 |
ResourceTemplate () |
5237 |
ResourceTemplate () |
| 5238 |
{ |
5238 |
{ |
| 5239 |
Register (PCC, |
5239 |
Register (PlatformCommChannel, |
| 5240 |
0x20, // Bit Width |
5240 |
0x20, // Bit Width |
| 5241 |
0x00, // Bit Offset |
5241 |
0x00, // Bit Offset |
| 5242 |
0x0000000000000B50, // Address |
5242 |
0x0000000000000B50, // Address |
|
Lines 5502-5508
Link Here
|
| 5502 |
0x02, |
5502 |
0x02, |
| 5503 |
ResourceTemplate () |
5503 |
ResourceTemplate () |
| 5504 |
{ |
5504 |
{ |
| 5505 |
Register (PCC, |
5505 |
Register (PlatformCommChannel, |
| 5506 |
0x20, // Bit Width |
5506 |
0x20, // Bit Width |
| 5507 |
0x00, // Bit Offset |
5507 |
0x00, // Bit Offset |
| 5508 |
0x0000000000000C00, // Address |
5508 |
0x0000000000000C00, // Address |
|
Lines 5512-5518
Link Here
|
| 5512 |
|
5512 |
|
| 5513 |
ResourceTemplate () |
5513 |
ResourceTemplate () |
| 5514 |
{ |
5514 |
{ |
| 5515 |
Register (PCC, |
5515 |
Register (PlatformCommChannel, |
| 5516 |
0x20, // Bit Width |
5516 |
0x20, // Bit Width |
| 5517 |
0x00, // Bit Offset |
5517 |
0x00, // Bit Offset |
| 5518 |
0x0000000000000C04, // Address |
5518 |
0x0000000000000C04, // Address |
|
Lines 5522-5528
Link Here
|
| 5522 |
|
5522 |
|
| 5523 |
ResourceTemplate () |
5523 |
ResourceTemplate () |
| 5524 |
{ |
5524 |
{ |
| 5525 |
Register (PCC, |
5525 |
Register (PlatformCommChannel, |
| 5526 |
0x20, // Bit Width |
5526 |
0x20, // Bit Width |
| 5527 |
0x00, // Bit Offset |
5527 |
0x00, // Bit Offset |
| 5528 |
0x0000000000000C08, // Address |
5528 |
0x0000000000000C08, // Address |
|
Lines 5532-5538
Link Here
|
| 5532 |
|
5532 |
|
| 5533 |
ResourceTemplate () |
5533 |
ResourceTemplate () |
| 5534 |
{ |
5534 |
{ |
| 5535 |
Register (PCC, |
5535 |
Register (PlatformCommChannel, |
| 5536 |
0x20, // Bit Width |
5536 |
0x20, // Bit Width |
| 5537 |
0x00, // Bit Offset |
5537 |
0x00, // Bit Offset |
| 5538 |
0x0000000000000C0C, // Address |
5538 |
0x0000000000000C0C, // Address |
|
Lines 5542-5548
Link Here
|
| 5542 |
|
5542 |
|
| 5543 |
ResourceTemplate () |
5543 |
ResourceTemplate () |
| 5544 |
{ |
5544 |
{ |
| 5545 |
Register (PCC, |
5545 |
Register (PlatformCommChannel, |
| 5546 |
0x20, // Bit Width |
5546 |
0x20, // Bit Width |
| 5547 |
0x00, // Bit Offset |
5547 |
0x00, // Bit Offset |
| 5548 |
0x0000000000000C10, // Address |
5548 |
0x0000000000000C10, // Address |
|
Lines 5552-5558
Link Here
|
| 5552 |
|
5552 |
|
| 5553 |
ResourceTemplate () |
5553 |
ResourceTemplate () |
| 5554 |
{ |
5554 |
{ |
| 5555 |
Register (PCC, |
5555 |
Register (PlatformCommChannel, |
| 5556 |
0x20, // Bit Width |
5556 |
0x20, // Bit Width |
| 5557 |
0x00, // Bit Offset |
5557 |
0x00, // Bit Offset |
| 5558 |
0x0000000000000C14, // Address |
5558 |
0x0000000000000C14, // Address |
|
Lines 5607-5613
Link Here
|
| 5607 |
|
5607 |
|
| 5608 |
ResourceTemplate () |
5608 |
ResourceTemplate () |
| 5609 |
{ |
5609 |
{ |
| 5610 |
Register (PCC, |
5610 |
Register (PlatformCommChannel, |
| 5611 |
0x40, // Bit Width |
5611 |
0x40, // Bit Width |
| 5612 |
0x00, // Bit Offset |
5612 |
0x00, // Bit Offset |
| 5613 |
0x0000000000000C2C, // Address |
5613 |
0x0000000000000C2C, // Address |
|
Lines 5617-5623
Link Here
|
| 5617 |
|
5617 |
|
| 5618 |
ResourceTemplate () |
5618 |
ResourceTemplate () |
| 5619 |
{ |
5619 |
{ |
| 5620 |
Register (PCC, |
5620 |
Register (PlatformCommChannel, |
| 5621 |
0x40, // Bit Width |
5621 |
0x40, // Bit Width |
| 5622 |
0x00, // Bit Offset |
5622 |
0x00, // Bit Offset |
| 5623 |
0x0000000000000C34, // Address |
5623 |
0x0000000000000C34, // Address |
|
Lines 5672-5678
Link Here
|
| 5672 |
|
5672 |
|
| 5673 |
ResourceTemplate () |
5673 |
ResourceTemplate () |
| 5674 |
{ |
5674 |
{ |
| 5675 |
Register (PCC, |
5675 |
Register (PlatformCommChannel, |
| 5676 |
0x20, // Bit Width |
5676 |
0x20, // Bit Width |
| 5677 |
0x00, // Bit Offset |
5677 |
0x00, // Bit Offset |
| 5678 |
0x0000000000000C50, // Address |
5678 |
0x0000000000000C50, // Address |
|
Lines 5938-5944
Link Here
|
| 5938 |
0x02, |
5938 |
0x02, |
| 5939 |
ResourceTemplate () |
5939 |
ResourceTemplate () |
| 5940 |
{ |
5940 |
{ |
| 5941 |
Register (PCC, |
5941 |
Register (PlatformCommChannel, |
| 5942 |
0x20, // Bit Width |
5942 |
0x20, // Bit Width |
| 5943 |
0x00, // Bit Offset |
5943 |
0x00, // Bit Offset |
| 5944 |
0x0000000000000D00, // Address |
5944 |
0x0000000000000D00, // Address |
|
Lines 5948-5954
Link Here
|
| 5948 |
|
5948 |
|
| 5949 |
ResourceTemplate () |
5949 |
ResourceTemplate () |
| 5950 |
{ |
5950 |
{ |
| 5951 |
Register (PCC, |
5951 |
Register (PlatformCommChannel, |
| 5952 |
0x20, // Bit Width |
5952 |
0x20, // Bit Width |
| 5953 |
0x00, // Bit Offset |
5953 |
0x00, // Bit Offset |
| 5954 |
0x0000000000000D04, // Address |
5954 |
0x0000000000000D04, // Address |
|
Lines 5958-5964
Link Here
|
| 5958 |
|
5958 |
|
| 5959 |
ResourceTemplate () |
5959 |
ResourceTemplate () |
| 5960 |
{ |
5960 |
{ |
| 5961 |
Register (PCC, |
5961 |
Register (PlatformCommChannel, |
| 5962 |
0x20, // Bit Width |
5962 |
0x20, // Bit Width |
| 5963 |
0x00, // Bit Offset |
5963 |
0x00, // Bit Offset |
| 5964 |
0x0000000000000D08, // Address |
5964 |
0x0000000000000D08, // Address |
|
Lines 5968-5974
Link Here
|
| 5968 |
|
5968 |
|
| 5969 |
ResourceTemplate () |
5969 |
ResourceTemplate () |
| 5970 |
{ |
5970 |
{ |
| 5971 |
Register (PCC, |
5971 |
Register (PlatformCommChannel, |
| 5972 |
0x20, // Bit Width |
5972 |
0x20, // Bit Width |
| 5973 |
0x00, // Bit Offset |
5973 |
0x00, // Bit Offset |
| 5974 |
0x0000000000000D0C, // Address |
5974 |
0x0000000000000D0C, // Address |
|
Lines 5978-5984
Link Here
|
| 5978 |
|
5978 |
|
| 5979 |
ResourceTemplate () |
5979 |
ResourceTemplate () |
| 5980 |
{ |
5980 |
{ |
| 5981 |
Register (PCC, |
5981 |
Register (PlatformCommChannel, |
| 5982 |
0x20, // Bit Width |
5982 |
0x20, // Bit Width |
| 5983 |
0x00, // Bit Offset |
5983 |
0x00, // Bit Offset |
| 5984 |
0x0000000000000D10, // Address |
5984 |
0x0000000000000D10, // Address |
|
Lines 5988-5994
Link Here
|
| 5988 |
|
5988 |
|
| 5989 |
ResourceTemplate () |
5989 |
ResourceTemplate () |
| 5990 |
{ |
5990 |
{ |
| 5991 |
Register (PCC, |
5991 |
Register (PlatformCommChannel, |
| 5992 |
0x20, // Bit Width |
5992 |
0x20, // Bit Width |
| 5993 |
0x00, // Bit Offset |
5993 |
0x00, // Bit Offset |
| 5994 |
0x0000000000000D14, // Address |
5994 |
0x0000000000000D14, // Address |
|
Lines 6043-6049
Link Here
|
| 6043 |
|
6043 |
|
| 6044 |
ResourceTemplate () |
6044 |
ResourceTemplate () |
| 6045 |
{ |
6045 |
{ |
| 6046 |
Register (PCC, |
6046 |
Register (PlatformCommChannel, |
| 6047 |
0x40, // Bit Width |
6047 |
0x40, // Bit Width |
| 6048 |
0x00, // Bit Offset |
6048 |
0x00, // Bit Offset |
| 6049 |
0x0000000000000D2C, // Address |
6049 |
0x0000000000000D2C, // Address |
|
Lines 6053-6059
Link Here
|
| 6053 |
|
6053 |
|
| 6054 |
ResourceTemplate () |
6054 |
ResourceTemplate () |
| 6055 |
{ |
6055 |
{ |
| 6056 |
Register (PCC, |
6056 |
Register (PlatformCommChannel, |
| 6057 |
0x40, // Bit Width |
6057 |
0x40, // Bit Width |
| 6058 |
0x00, // Bit Offset |
6058 |
0x00, // Bit Offset |
| 6059 |
0x0000000000000D34, // Address |
6059 |
0x0000000000000D34, // Address |
|
Lines 6108-6114
Link Here
|
| 6108 |
|
6108 |
|
| 6109 |
ResourceTemplate () |
6109 |
ResourceTemplate () |
| 6110 |
{ |
6110 |
{ |
| 6111 |
Register (PCC, |
6111 |
Register (PlatformCommChannel, |
| 6112 |
0x20, // Bit Width |
6112 |
0x20, // Bit Width |
| 6113 |
0x00, // Bit Offset |
6113 |
0x00, // Bit Offset |
| 6114 |
0x0000000000000D50, // Address |
6114 |
0x0000000000000D50, // Address |
|
Lines 6374-6380
Link Here
|
| 6374 |
0x02, |
6374 |
0x02, |
| 6375 |
ResourceTemplate () |
6375 |
ResourceTemplate () |
| 6376 |
{ |
6376 |
{ |
| 6377 |
Register (PCC, |
6377 |
Register (PlatformCommChannel, |
| 6378 |
0x20, // Bit Width |
6378 |
0x20, // Bit Width |
| 6379 |
0x00, // Bit Offset |
6379 |
0x00, // Bit Offset |
| 6380 |
0x0000000000000E00, // Address |
6380 |
0x0000000000000E00, // Address |
|
Lines 6384-6390
Link Here
|
| 6384 |
|
6384 |
|
| 6385 |
ResourceTemplate () |
6385 |
ResourceTemplate () |
| 6386 |
{ |
6386 |
{ |
| 6387 |
Register (PCC, |
6387 |
Register (PlatformCommChannel, |
| 6388 |
0x20, // Bit Width |
6388 |
0x20, // Bit Width |
| 6389 |
0x00, // Bit Offset |
6389 |
0x00, // Bit Offset |
| 6390 |
0x0000000000000E04, // Address |
6390 |
0x0000000000000E04, // Address |
|
Lines 6394-6400
Link Here
|
| 6394 |
|
6394 |
|
| 6395 |
ResourceTemplate () |
6395 |
ResourceTemplate () |
| 6396 |
{ |
6396 |
{ |
| 6397 |
Register (PCC, |
6397 |
Register (PlatformCommChannel, |
| 6398 |
0x20, // Bit Width |
6398 |
0x20, // Bit Width |
| 6399 |
0x00, // Bit Offset |
6399 |
0x00, // Bit Offset |
| 6400 |
0x0000000000000E08, // Address |
6400 |
0x0000000000000E08, // Address |
|
Lines 6404-6410
Link Here
|
| 6404 |
|
6404 |
|
| 6405 |
ResourceTemplate () |
6405 |
ResourceTemplate () |
| 6406 |
{ |
6406 |
{ |
| 6407 |
Register (PCC, |
6407 |
Register (PlatformCommChannel, |
| 6408 |
0x20, // Bit Width |
6408 |
0x20, // Bit Width |
| 6409 |
0x00, // Bit Offset |
6409 |
0x00, // Bit Offset |
| 6410 |
0x0000000000000E0C, // Address |
6410 |
0x0000000000000E0C, // Address |
|
Lines 6414-6420
Link Here
|
| 6414 |
|
6414 |
|
| 6415 |
ResourceTemplate () |
6415 |
ResourceTemplate () |
| 6416 |
{ |
6416 |
{ |
| 6417 |
Register (PCC, |
6417 |
Register (PlatformCommChannel, |
| 6418 |
0x20, // Bit Width |
6418 |
0x20, // Bit Width |
| 6419 |
0x00, // Bit Offset |
6419 |
0x00, // Bit Offset |
| 6420 |
0x0000000000000E10, // Address |
6420 |
0x0000000000000E10, // Address |
|
Lines 6424-6430
Link Here
|
| 6424 |
|
6424 |
|
| 6425 |
ResourceTemplate () |
6425 |
ResourceTemplate () |
| 6426 |
{ |
6426 |
{ |
| 6427 |
Register (PCC, |
6427 |
Register (PlatformCommChannel, |
| 6428 |
0x20, // Bit Width |
6428 |
0x20, // Bit Width |
| 6429 |
0x00, // Bit Offset |
6429 |
0x00, // Bit Offset |
| 6430 |
0x0000000000000E14, // Address |
6430 |
0x0000000000000E14, // Address |
|
Lines 6479-6485
Link Here
|
| 6479 |
|
6479 |
|
| 6480 |
ResourceTemplate () |
6480 |
ResourceTemplate () |
| 6481 |
{ |
6481 |
{ |
| 6482 |
Register (PCC, |
6482 |
Register (PlatformCommChannel, |
| 6483 |
0x40, // Bit Width |
6483 |
0x40, // Bit Width |
| 6484 |
0x00, // Bit Offset |
6484 |
0x00, // Bit Offset |
| 6485 |
0x0000000000000E2C, // Address |
6485 |
0x0000000000000E2C, // Address |
|
Lines 6489-6495
Link Here
|
| 6489 |
|
6489 |
|
| 6490 |
ResourceTemplate () |
6490 |
ResourceTemplate () |
| 6491 |
{ |
6491 |
{ |
| 6492 |
Register (PCC, |
6492 |
Register (PlatformCommChannel, |
| 6493 |
0x40, // Bit Width |
6493 |
0x40, // Bit Width |
| 6494 |
0x00, // Bit Offset |
6494 |
0x00, // Bit Offset |
| 6495 |
0x0000000000000E34, // Address |
6495 |
0x0000000000000E34, // Address |
|
Lines 6544-6550
Link Here
|
| 6544 |
|
6544 |
|
| 6545 |
ResourceTemplate () |
6545 |
ResourceTemplate () |
| 6546 |
{ |
6546 |
{ |
| 6547 |
Register (PCC, |
6547 |
Register (PlatformCommChannel, |
| 6548 |
0x20, // Bit Width |
6548 |
0x20, // Bit Width |
| 6549 |
0x00, // Bit Offset |
6549 |
0x00, // Bit Offset |
| 6550 |
0x0000000000000E50, // Address |
6550 |
0x0000000000000E50, // Address |
|
Lines 6810-6816
Link Here
|
| 6810 |
0x02, |
6810 |
0x02, |
| 6811 |
ResourceTemplate () |
6811 |
ResourceTemplate () |
| 6812 |
{ |
6812 |
{ |
| 6813 |
Register (PCC, |
6813 |
Register (PlatformCommChannel, |
| 6814 |
0x20, // Bit Width |
6814 |
0x20, // Bit Width |
| 6815 |
0x00, // Bit Offset |
6815 |
0x00, // Bit Offset |
| 6816 |
0x0000000000000F00, // Address |
6816 |
0x0000000000000F00, // Address |
|
Lines 6820-6826
Link Here
|
| 6820 |
|
6820 |
|
| 6821 |
ResourceTemplate () |
6821 |
ResourceTemplate () |
| 6822 |
{ |
6822 |
{ |
| 6823 |
Register (PCC, |
6823 |
Register (PlatformCommChannel, |
| 6824 |
0x20, // Bit Width |
6824 |
0x20, // Bit Width |
| 6825 |
0x00, // Bit Offset |
6825 |
0x00, // Bit Offset |
| 6826 |
0x0000000000000F04, // Address |
6826 |
0x0000000000000F04, // Address |
|
Lines 6830-6836
Link Here
|
| 6830 |
|
6830 |
|
| 6831 |
ResourceTemplate () |
6831 |
ResourceTemplate () |
| 6832 |
{ |
6832 |
{ |
| 6833 |
Register (PCC, |
6833 |
Register (PlatformCommChannel, |
| 6834 |
0x20, // Bit Width |
6834 |
0x20, // Bit Width |
| 6835 |
0x00, // Bit Offset |
6835 |
0x00, // Bit Offset |
| 6836 |
0x0000000000000F08, // Address |
6836 |
0x0000000000000F08, // Address |
|
Lines 6840-6846
Link Here
|
| 6840 |
|
6840 |
|
| 6841 |
ResourceTemplate () |
6841 |
ResourceTemplate () |
| 6842 |
{ |
6842 |
{ |
| 6843 |
Register (PCC, |
6843 |
Register (PlatformCommChannel, |
| 6844 |
0x20, // Bit Width |
6844 |
0x20, // Bit Width |
| 6845 |
0x00, // Bit Offset |
6845 |
0x00, // Bit Offset |
| 6846 |
0x0000000000000F0C, // Address |
6846 |
0x0000000000000F0C, // Address |
|
Lines 6850-6856
Link Here
|
| 6850 |
|
6850 |
|
| 6851 |
ResourceTemplate () |
6851 |
ResourceTemplate () |
| 6852 |
{ |
6852 |
{ |
| 6853 |
Register (PCC, |
6853 |
Register (PlatformCommChannel, |
| 6854 |
0x20, // Bit Width |
6854 |
0x20, // Bit Width |
| 6855 |
0x00, // Bit Offset |
6855 |
0x00, // Bit Offset |
| 6856 |
0x0000000000000F10, // Address |
6856 |
0x0000000000000F10, // Address |
|
Lines 6860-6866
Link Here
|
| 6860 |
|
6860 |
|
| 6861 |
ResourceTemplate () |
6861 |
ResourceTemplate () |
| 6862 |
{ |
6862 |
{ |
| 6863 |
Register (PCC, |
6863 |
Register (PlatformCommChannel, |
| 6864 |
0x20, // Bit Width |
6864 |
0x20, // Bit Width |
| 6865 |
0x00, // Bit Offset |
6865 |
0x00, // Bit Offset |
| 6866 |
0x0000000000000F14, // Address |
6866 |
0x0000000000000F14, // Address |
|
Lines 6915-6921
Link Here
|
| 6915 |
|
6915 |
|
| 6916 |
ResourceTemplate () |
6916 |
ResourceTemplate () |
| 6917 |
{ |
6917 |
{ |
| 6918 |
Register (PCC, |
6918 |
Register (PlatformCommChannel, |
| 6919 |
0x40, // Bit Width |
6919 |
0x40, // Bit Width |
| 6920 |
0x00, // Bit Offset |
6920 |
0x00, // Bit Offset |
| 6921 |
0x0000000000000F2C, // Address |
6921 |
0x0000000000000F2C, // Address |
|
Lines 6925-6931
Link Here
|
| 6925 |
|
6925 |
|
| 6926 |
ResourceTemplate () |
6926 |
ResourceTemplate () |
| 6927 |
{ |
6927 |
{ |
| 6928 |
Register (PCC, |
6928 |
Register (PlatformCommChannel, |
| 6929 |
0x40, // Bit Width |
6929 |
0x40, // Bit Width |
| 6930 |
0x00, // Bit Offset |
6930 |
0x00, // Bit Offset |
| 6931 |
0x0000000000000F34, // Address |
6931 |
0x0000000000000F34, // Address |
|
Lines 6980-6986
Link Here
|
| 6980 |
|
6980 |
|
| 6981 |
ResourceTemplate () |
6981 |
ResourceTemplate () |
| 6982 |
{ |
6982 |
{ |
| 6983 |
Register (PCC, |
6983 |
Register (PlatformCommChannel, |
| 6984 |
0x20, // Bit Width |
6984 |
0x20, // Bit Width |
| 6985 |
0x00, // Bit Offset |
6985 |
0x00, // Bit Offset |
| 6986 |
0x0000000000000F50, // Address |
6986 |
0x0000000000000F50, // Address |
|
Lines 7131-7137
Link Here
|
| 7131 |
{ |
7131 |
{ |
| 7132 |
Name (_HID, "APMC0D06") // _HID: Hardware ID |
7132 |
Name (_HID, "APMC0D06") // _HID: Hardware ID |
| 7133 |
OperationRegion (SRST, SystemMemory, 0x1F10C000, 0x04) |
7133 |
OperationRegion (SRST, SystemMemory, 0x1F10C000, 0x04) |
| 7134 |
OperationRegion (CLKE, SystemMemory, 0x1F10C004, 0x04) |
7134 |
// OperationRegion (CLKE, SystemMemory, 0x1F10C004, 0x04) |
| 7135 |
Field (SRST, DWordAcc, NoLock, Preserve) |
7135 |
Field (SRST, DWordAcc, NoLock, Preserve) |
| 7136 |
{ |
7136 |
{ |
| 7137 |
IC5R, 1, |
7137 |
IC5R, 1, |
|
Lines 7149-7170
Link Here
|
| 7149 |
CSRR, 1 |
7149 |
CSRR, 1 |
| 7150 |
} |
7150 |
} |
| 7151 |
|
7151 |
|
| 7152 |
Field (CLKE, DWordAcc, NoLock, Preserve) |
7152 |
/* Field (CLKE, DWordAcc, NoLock, Preserve) */ |
| 7153 |
{ |
7153 |
/* { */ |
| 7154 |
IC5E, 1, |
7154 |
/* IC5E, 1, */ |
| 7155 |
SP1E, 1, |
7155 |
/* SP1E, 1, */ |
| 7156 |
UT4E, 1, |
7156 |
/* UT4E, 1, */ |
| 7157 |
APBE, 1, |
7157 |
/* APBE, 1, */ |
| 7158 |
IC2E, 1, |
7158 |
/* IC2E, 1, */ |
| 7159 |
IC3E, 1, |
7159 |
/* IC3E, 1, */ |
| 7160 |
IC4E, 1, |
7160 |
/* IC4E, 1, */ |
| 7161 |
SP0E, 1, |
7161 |
/* SP0E, 1, */ |
| 7162 |
UT3E, 1, |
7162 |
/* UT3E, 1, */ |
| 7163 |
UT2E, 1, |
7163 |
/* UT2E, 1, */ |
| 7164 |
UT1E, 1, |
7164 |
/* UT1E, 1, */ |
| 7165 |
UT0E, 1, |
7165 |
/* UT0E, 1, */ |
| 7166 |
CSRE, 1 |
7166 |
/* CSRE, 1 */ |
| 7167 |
} |
7167 |
/* } */ |
| 7168 |
|
7168 |
|
| 7169 |
Name (_CCA, One) // _CCA: Cache Coherency Attribute |
7169 |
Name (_CCA, One) // _CCA: Cache Coherency Attribute |
| 7170 |
Method (_STA, 0, NotSerialized) // _STA: Status |
7170 |
Method (_STA, 0, NotSerialized) // _STA: Status |
|
Lines 7196-7212
Link Here
|
| 7196 |
}) |
7196 |
}) |
| 7197 |
Method (_INI, 0, NotSerialized) // _INI: Initialize |
7197 |
Method (_INI, 0, NotSerialized) // _INI: Initialize |
| 7198 |
{ |
7198 |
{ |
| 7199 |
If ((IC4E == Zero)) |
7199 |
/* If ((IC4E == Zero)) */ |
| 7200 |
{ |
7200 |
/* { */ |
| 7201 |
If ((IC4R == Zero)) |
7201 |
/* If ((IC4R == Zero)) */ |
| 7202 |
{ |
7202 |
/* { */ |
| 7203 |
IC4R = One |
7203 |
/* IC4R = One */ |
| 7204 |
Stall (0x64) |
7204 |
/* Stall (0x64) */ |
| 7205 |
} |
7205 |
/* } */ |
| 7206 |
|
7206 |
|
| 7207 |
IC4E = One |
7207 |
/* IC4E = One */ |
| 7208 |
IC4R = Zero |
7208 |
/* IC4R = Zero */ |
| 7209 |
} |
7209 |
/* } */ |
| 7210 |
} |
7210 |
} |
| 7211 |
|
7211 |
|
| 7212 |
Device (IPI) |
7212 |
Device (IPI) |