Lines 77-85
Link Here
|
77 |
PCPU_SET(awake, 1); |
77 |
PCPU_SET(awake, 1); |
78 |
__asm __volatile("msync; isync"); |
78 |
__asm __volatile("msync; isync"); |
79 |
|
79 |
|
|
|
80 |
powerpc_sync(); |
80 |
while (ap_letgo == 0) |
81 |
while (ap_letgo == 0) |
81 |
__asm __volatile("or 31,31,31"); |
82 |
powerpc_sync(); |
82 |
__asm __volatile("or 6,6,6"); |
83 |
isync(); |
83 |
|
84 |
|
84 |
/* |
85 |
/* |
85 |
* Set timebase as soon as possible to meet an implicit rendezvous |
86 |
* Set timebase as soon as possible to meet an implicit rendezvous |
Lines 262-269
Link Here
|
262 |
__asm __volatile("msync; isync"); |
263 |
__asm __volatile("msync; isync"); |
263 |
|
264 |
|
264 |
/* Let APs continue */ |
265 |
/* Let APs continue */ |
265 |
atomic_store_rel_int(&ap_letgo, 1); |
266 |
ap_letgo= 1; // depend on prior sync, no need to lwsync first |
266 |
|
267 |
|
|
|
268 |
powerpc_sync(); // analogous to what the ap's do (more similar time frame?) |
269 |
if (ap_letgo) isync(); |
270 |
|
267 |
platform_smp_timebase_sync(ap_timebase, 0); |
271 |
platform_smp_timebase_sync(ap_timebase, 0); |
268 |
|
272 |
|
269 |
while (ap_awake < smp_cpus) |
273 |
while (ap_awake < smp_cpus) |