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Lines 77-85
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| 77 |
PCPU_SET(awake, 1); |
77 |
PCPU_SET(awake, 1); |
| 78 |
__asm __volatile("msync; isync"); |
78 |
__asm __volatile("msync; isync"); |
| 79 |
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powerpc_sync(); |
| 80 |
while (ap_letgo == 0) |
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while (ap_letgo == 0) |
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{ |
| 81 |
__asm __volatile("or 31,31,31"); |
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__asm __volatile("or 31,31,31"); |
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powerpc_sync(); |
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} |
| 82 |
__asm __volatile("or 6,6,6"); |
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__asm __volatile("or 6,6,6"); |
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isync(); |
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| 84 |
/* |
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/* |
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* Set timebase as soon as possible to meet an implicit rendezvous |
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* Set timebase as soon as possible to meet an implicit rendezvous |
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Lines 262-269
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| 262 |
__asm __volatile("msync; isync"); |
267 |
__asm __volatile("msync; isync"); |
| 263 |
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| 264 |
/* Let APs continue */ |
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/* Let APs continue */ |
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atomic_store_rel_int(&ap_letgo, 1); |
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ap_letgo= 1; // depend on prior sync, no need to lwsync first |
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powerpc_sync(); // analogous to what the ap's do (more similar time frame?) |
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if (ap_letgo) isync(); |
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platform_smp_timebase_sync(ap_timebase, 0); |
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platform_smp_timebase_sync(ap_timebase, 0); |
| 268 |
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| 269 |
while (ap_awake < smp_cpus) |
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while (ap_awake < smp_cpus) |