Attachment #204974 for bug #238484

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# $FreeBSD$

PORTNAME=	yosys
PORTVERSION=	g20190531
DISTVERSION=	0.8
PORTREVISION=	2
CATEGORIES=	devel

MAINTAINER=	jsorocil@gmail.com


USES=		bison compiler:c++11-lang gmake pkgconfig python:3.6+ readline \
		shebangfix tcl

SHEBANG_FILES=	backends/smt2/smtbmc.py \
		misc/yosys-config.in

USE_GITHUB=	yes
GH_ACCOUNT=	YosysHQ
GH_TAGNAME=		90ec2cda

BINARY_ALIAS=	python3=${PYTHON_CMD} tclsh=${TCLSH}
MAKE_ARGS=	ABCEXTERNAL=abc

Lines 1-3 Link Here

(-)b/devel/yosys/distinfo (-3 / +3 lines)
1	TIMESTAMP = 1540309364	1	TIMESTAMP = 1559409264
2	SHA256 (YosysHQ-yosys-yosys-0.8_GH0.tar.gz) = 07760fe732003585b26d97f9e02bcddf242ff7fc33dbd415446ac7c70e85c66f	2	SHA256 (YosysHQ-yosys-g20190531-90ec2cda_GH0.tar.gz) = 5918b3e44414d59b51977dd06fe783eba532297355366ae1a00e481384a7edb9
3	SIZE (YosysHQ-yosys-yosys-0.8_GH0.tar.gz) = 1118433	3	SIZE (YosysHQ-yosys-g20190531-90ec2cda_GH0.tar.gz) = 1284045




%%DATADIR%%/achronix/speedster22i/cells_map.v
%%DATADIR%%/achronix/speedster22i/cells_sim.v
%%DATADIR%%/adff2dff.v
%%DATADIR%%/anlogic/arith_map.v
%%DATADIR%%/anlogic/cells_map.v
%%DATADIR%%/anlogic/cells_sim.v
%%DATADIR%%/anlogic/dram_init_16x4.vh
%%DATADIR%%/anlogic/drams.txt
%%DATADIR%%/anlogic/drams_map.v
%%DATADIR%%/anlogic/eagle_bb.v
%%DATADIR%%/cells.lib
%%DATADIR%%/cmp2lut.v
%%DATADIR%%/coolrunner2/cells_latch.v
%%DATADIR%%/coolrunner2/cells_sim.v
%%DATADIR%%/coolrunner2/tff_extract.v
%%DATADIR%%/coolrunner2/xc2_dff.lib
%%DATADIR%%/dff2ff.v
%%DATADIR%%/ecp5/arith_map.v
%%DATADIR%%/ecp5/bram.txt
%%DATADIR%%/ecp5/bram_conn_1.vh
%%DATADIR%%/ecp5/bram_conn_18.vh
%%DATADIR%%/ecp5/bram_conn_2.vh
%%DATADIR%%/ecp5/bram_conn_4.vh
%%DATADIR%%/ecp5/bram_conn_9.vh
%%DATADIR%%/ecp5/bram_init_1_2_4.vh
%%DATADIR%%/ecp5/bram_init_9_18_36.vh
%%DATADIR%%/ecp5/brams_map.v
%%DATADIR%%/ecp5/cells_bb.v
%%DATADIR%%/ecp5/cells_map.v
%%DATADIR%%/ecp5/cells_sim.v
%%DATADIR%%/ecp5/dram.txt
%%DATADIR%%/ecp5/drams_map.v
%%DATADIR%%/ecp5/latches_map.v
%%DATADIR%%/gate2lut.v
%%DATADIR%%/gowin/arith_map.v
%%DATADIR%%/gowin/bram.txt
%%DATADIR%%/gowin/brams_init3.vh
%%DATADIR%%/gowin/brams_map.v
%%DATADIR%%/gowin/cells_map.v
%%DATADIR%%/gowin/cells_sim.v
%%DATADIR%%/gowin/dram.txt
%%DATADIR%%/gowin/drams_map.v
%%DATADIR%%/greenpak4/cells_blackbox.v
%%DATADIR%%/greenpak4/cells_latch.v
%%DATADIR%%/greenpak4/cells_map.v

%%DATADIR%%/intel/max10/cells_sim.v
%%DATADIR%%/pmux2mux.v
%%DATADIR%%/python3/smtio.py
%%DATADIR%%/sf2/arith_map.v
%%DATADIR%%/sf2/cells_map.v
%%DATADIR%%/sf2/cells_sim.v
%%DATADIR%%/simcells.v
%%DATADIR%%/simlib.v
%%DATADIR%%/techmap.v

%%DATADIR%%/xilinx/cells_xtra.v
%%DATADIR%%/xilinx/drams.txt
%%DATADIR%%/xilinx/drams_map.v
%%DATADIR%%/xilinx/ff_map.v
%%DATADIR%%/xilinx/lut_map.v
- 

Return to bug 238484

Lines 2-10 Link Here

(-)b/devel/yosys/Makefile (-3 / +3 lines)
2	# $FreeBSD$	2	# $FreeBSD$
3		3
4	PORTNAME= yosys	4	PORTNAME= yosys
5	DISTVERSIONPREFIX= yosys-	5	PORTVERSION= g20190531
6	DISTVERSION= 0.8
7	PORTREVISION= 2
8	CATEGORIES= devel	6	CATEGORIES= devel
9		7
10	MAINTAINER= jsorocil@gmail.com	8	MAINTAINER= jsorocil@gmail.com
Lines 20-30 LIB_DEPENDS= libffi.so:devel/libffi Link Here
20		18
21	USES= bison compiler:c++11-lang gmake pkgconfig python:3.6+ readline \	19	USES= bison compiler:c++11-lang gmake pkgconfig python:3.6+ readline \
22	shebangfix tcl	20	shebangfix tcl
		21
23	SHEBANG_FILES= backends/smt2/smtbmc.py \	22	SHEBANG_FILES= backends/smt2/smtbmc.py \
24	misc/yosys-config.in	23	misc/yosys-config.in
25		24
26	USE_GITHUB= yes	25	USE_GITHUB= yes
27	GH_ACCOUNT= YosysHQ	26	GH_ACCOUNT= YosysHQ
		27	GH_TAGNAME= 90ec2cda
28		28
29	BINARY_ALIAS= python3=${PYTHON_CMD} tclsh=${TCLSH}	29	BINARY_ALIAS= python3=${PYTHON_CMD} tclsh=${TCLSH}
30	MAKE_ARGS= ABCEXTERNAL=abc	30	MAKE_ARGS= ABCEXTERNAL=abc

Lines 5-23 bin/yosys-smtbmc Link Here

(-)b/devel/yosys/pkg-plist (-2 / +31 lines)
5	%%DATADIR%%/achronix/speedster22i/cells_map.v	5	%%DATADIR%%/achronix/speedster22i/cells_map.v
6	%%DATADIR%%/achronix/speedster22i/cells_sim.v	6	%%DATADIR%%/achronix/speedster22i/cells_sim.v
7	%%DATADIR%%/adff2dff.v	7	%%DATADIR%%/adff2dff.v
		8	%%DATADIR%%/anlogic/arith_map.v
		9	%%DATADIR%%/anlogic/cells_map.v
		10	%%DATADIR%%/anlogic/cells_sim.v
		11	%%DATADIR%%/anlogic/dram_init_16x4.vh
		12	%%DATADIR%%/anlogic/drams.txt
		13	%%DATADIR%%/anlogic/drams_map.v
		14	%%DATADIR%%/anlogic/eagle_bb.v
8	%%DATADIR%%/cells.lib	15	%%DATADIR%%/cells.lib
		16	%%DATADIR%%/cmp2lut.v
9	%%DATADIR%%/coolrunner2/cells_latch.v	17	%%DATADIR%%/coolrunner2/cells_latch.v
10	%%DATADIR%%/coolrunner2/cells_sim.v	18	%%DATADIR%%/coolrunner2/cells_sim.v
11	%%DATADIR%%/coolrunner2/tff_extract.v	19	%%DATADIR%%/coolrunner2/tff_extract.v
12	%%DATADIR%%/coolrunner2/xc2_dff.lib	20	%%DATADIR%%/coolrunner2/xc2_dff.lib
13	%%DATADIR%%/dff2ff.v	21	%%DATADIR%%/dff2ff.v
14	%%DATADIR%%/ecp5/arith_map.v	22	%%DATADIR%%/ecp5/arith_map.v
		23	%%DATADIR%%/ecp5/bram.txt
		24	%%DATADIR%%/ecp5/bram_conn_1.vh
		25	%%DATADIR%%/ecp5/bram_conn_18.vh
		26	%%DATADIR%%/ecp5/bram_conn_2.vh
		27	%%DATADIR%%/ecp5/bram_conn_4.vh
		28	%%DATADIR%%/ecp5/bram_conn_9.vh
		29	%%DATADIR%%/ecp5/bram_init_1_2_4.vh
		30	%%DATADIR%%/ecp5/bram_init_9_18_36.vh
		31	%%DATADIR%%/ecp5/brams_map.v
		32	%%DATADIR%%/ecp5/cells_bb.v
15	%%DATADIR%%/ecp5/cells_map.v	33	%%DATADIR%%/ecp5/cells_map.v
16	%%DATADIR%%/ecp5/cells_sim.v	34	%%DATADIR%%/ecp5/cells_sim.v
17	%%DATADIR%%/ecp5/dram.txt	35	%%DATADIR%%/ecp5/dram.txt
18	%%DATADIR%%/ecp5/drams_map.v	36	%%DATADIR%%/ecp5/drams_map.v
		37	%%DATADIR%%/ecp5/latches_map.v
		38	%%DATADIR%%/gate2lut.v
		39	%%DATADIR%%/gowin/arith_map.v
		40	%%DATADIR%%/gowin/bram.txt
		41	%%DATADIR%%/gowin/brams_init3.vh
		42	%%DATADIR%%/gowin/brams_map.v
19	%%DATADIR%%/gowin/cells_map.v	43	%%DATADIR%%/gowin/cells_map.v
20	%%DATADIR%%/gowin/cells_sim.v	44	%%DATADIR%%/gowin/cells_sim.v
		45	%%DATADIR%%/gowin/dram.txt
		46	%%DATADIR%%/gowin/drams_map.v
21	%%DATADIR%%/greenpak4/cells_blackbox.v	47	%%DATADIR%%/greenpak4/cells_blackbox.v
22	%%DATADIR%%/greenpak4/cells_latch.v	48	%%DATADIR%%/greenpak4/cells_latch.v
23	%%DATADIR%%/greenpak4/cells_map.v	49	%%DATADIR%%/greenpak4/cells_map.v
Lines 72-77 bin/yosys-smtbmc Link Here
72	%%DATADIR%%/intel/max10/cells_sim.v	98	%%DATADIR%%/intel/max10/cells_sim.v
73	%%DATADIR%%/pmux2mux.v	99	%%DATADIR%%/pmux2mux.v
74	%%DATADIR%%/python3/smtio.py	100	%%DATADIR%%/python3/smtio.py
		101	%%DATADIR%%/sf2/arith_map.v
		102	%%DATADIR%%/sf2/cells_map.v
		103	%%DATADIR%%/sf2/cells_sim.v
75	%%DATADIR%%/simcells.v	104	%%DATADIR%%/simcells.v
76	%%DATADIR%%/simlib.v	105	%%DATADIR%%/simlib.v
77	%%DATADIR%%/techmap.v	106	%%DATADIR%%/techmap.v
Lines 88-91 bin/yosys-smtbmc Link Here
88	%%DATADIR%%/xilinx/cells_xtra.v	117	%%DATADIR%%/xilinx/cells_xtra.v
89	%%DATADIR%%/xilinx/drams.txt	118	%%DATADIR%%/xilinx/drams.txt
90	%%DATADIR%%/xilinx/drams_map.v	119	%%DATADIR%%/xilinx/drams_map.v
91	%%DATADIR%%/xilinx/lut2lut.v	120	%%DATADIR%%/xilinx/ff_map.v
		121	%%DATADIR%%/xilinx/lut_map.v
92	-