--- ig4_pci.oc	2019-06-24 15:01:04.213604000 +0200
+++ ig4_pci.c	2019-06-29 20:05:19.529047000 +0200
@@ -249,8 +249,8 @@
 
 	/* RESETS spec (22.2.36) recommends saving and re-initializing registers */
 	for (int i = 0; i < IG4_REGS_CONTEXT_SIZE; i++) {
-		bus_barrier(sc->regs_res, regs_context_ids[i], 4, BUS_SPACE_BARRIER_READ);
 		sc->regs_context[i] = bus_read_4(sc->regs_res, regs_context_ids[i]);
+		bus_barrier(sc->regs_res, regs_context_ids[i], 4, BUS_SPACE_BARRIER_READ);
 	}
 
 	/* 
@@ -259,10 +259,10 @@
 	 */
 	if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
 		bus_write_4(sc->regs_res, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW);
-		bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_READ);
+		bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_WRITE);
 	} else if (sc->version == IG4_SKYLAKE) {
 		bus_write_4(sc->regs_res, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
-		bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_READ);
+		bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_WRITE);
 	} else {
 		device_printf(dev, "Unable to assert reset, reset register unavailable\n");
 	}
@@ -281,10 +281,10 @@
 	/* wake the controller before its children */
 	if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
 		bus_write_4(sc->regs_res, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW);
-		bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_READ);
+		bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_WRITE);
 	} else if (sc->version == IG4_SKYLAKE) {
 		bus_write_4(sc->regs_res, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);
-		bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_READ);
+		bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_WRITE);
 	} else {
 		device_printf(dev, "Unable to deassert reset, reset register unavailable\n");
 	}