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Lines 259-268
Link Here
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| 259 |
*/ |
259 |
*/ |
| 260 |
if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { |
260 |
if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { |
| 261 |
bus_write_4(sc->regs_res, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW); |
261 |
bus_write_4(sc->regs_res, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW); |
| 262 |
bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_READ); |
262 |
bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_WRITE); |
| 263 |
} else if (sc->version == IG4_SKYLAKE) { |
263 |
} else if (sc->version == IG4_SKYLAKE) { |
| 264 |
bus_write_4(sc->regs_res, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); |
264 |
bus_write_4(sc->regs_res, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); |
| 265 |
bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_READ); |
265 |
bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_WRITE); |
| 266 |
} else { |
266 |
} else { |
| 267 |
device_printf(dev, "Unable to assert reset, reset register unavailable\n"); |
267 |
device_printf(dev, "Unable to assert reset, reset register unavailable\n"); |
| 268 |
} |
268 |
} |
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Lines 281-290
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| 281 |
/* wake the controller before its children */ |
281 |
/* wake the controller before its children */ |
| 282 |
if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { |
282 |
if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { |
| 283 |
bus_write_4(sc->regs_res, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW); |
283 |
bus_write_4(sc->regs_res, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW); |
| 284 |
bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_READ); |
284 |
bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_WRITE); |
| 285 |
} else if (sc->version == IG4_SKYLAKE) { |
285 |
} else if (sc->version == IG4_SKYLAKE) { |
| 286 |
bus_write_4(sc->regs_res, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL); |
286 |
bus_write_4(sc->regs_res, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL); |
| 287 |
bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_READ); |
287 |
bus_barrier(sc->regs_res, IG4_REG_RESETS_HSW, 4, BUS_SPACE_BARRIER_WRITE); |
| 288 |
} else { |
288 |
} else { |
| 289 |
device_printf(dev, "Unable to deassert reset, reset register unavailable\n"); |
289 |
device_printf(dev, "Unable to deassert reset, reset register unavailable\n"); |
| 290 |
} |
290 |
} |