Attachment 207365 Details for Bug 240485 – Patch (Revision 1)

[patch] Patch (Revision 1)

cannon-lake-i2c.patch (text/plain), 2.27 KB, created by Neel Chauhan on 2019-09-11 01:43:09 UTC

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Creator: Neel Chauhan

Created: 2019-09-11 01:43:09 UTC

Size: 2.27 KB

patch

obsolete

>Index: sys/dev/ichiic/ig4_pci.c
>===================================================================
>--- sys/dev/ichiic/ig4_pci.c	(revision 352137)
>+++ sys/dev/ichiic/ig4_pci.c	(working copy)
>@@ -82,6 +82,16 @@
> #define PCI_CHIP_SKYLAKE_I2C_5		0x9d658086
> #define PCI_CHIP_KABYLAKE_I2C_0		0xa1608086
> #define PCI_CHIP_KABYLAKE_I2C_1		0xa1618086
>+#define PCI_CHIP_CANNONLAKE_LP_I2C_0	0x9dc58086
>+#define PCI_CHIP_CANNONLAKE_LP_I2C_1	0x9dc68086
>+#define PCI_CHIP_CANNONLAKE_LP_I2C_2	0x9de88086
>+#define PCI_CHIP_CANNONLAKE_LP_I2C_3	0x9de98086
>+#define PCI_CHIP_CANNONLAKE_LP_I2C_4	0x9dea8086
>+#define PCI_CHIP_CANNONLAKE_LP_I2C_5	0x9deb8086
>+#define PCI_CHIP_CANNONLAKE_H_I2C_0	0xa3688086
>+#define PCI_CHIP_CANNONLAKE_H_I2C_1	0xa3698086
>+#define PCI_CHIP_CANNONLAKE_H_I2C_2	0xa36a8086
>+#define PCI_CHIP_CANNONLAKE_H_I2C_3	0xa36b8086
> #define PCI_CHIP_APL_I2C_0		0x5aac8086
> #define PCI_CHIP_APL_I2C_1		0x5aae8086
> #define PCI_CHIP_APL_I2C_2		0x5ab08086
>@@ -114,6 +124,16 @@
> 	{ PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE},
> 	{ PCI_CHIP_KABYLAKE_I2C_0, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE},
> 	{ PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE},
>+	{ PCI_CHIP_CANNONLAKE_LP_I2C_0, "Intel Cannon Lake-LP I2C Controller-0", IG4_SKYLAKE},
>+	{ PCI_CHIP_CANNONLAKE_LP_I2C_1, "Intel Cannon Lake-LP I2C Controller-1", IG4_SKYLAKE},
>+	{ PCI_CHIP_CANNONLAKE_LP_I2C_2, "Intel Cannon Lake-LP I2C Controller-2", IG4_SKYLAKE},
>+	{ PCI_CHIP_CANNONLAKE_LP_I2C_3, "Intel Cannon Lake-LP I2C Controller-3", IG4_SKYLAKE},
>+	{ PCI_CHIP_CANNONLAKE_LP_I2C_4, "Intel Cannon Lake-LP I2C Controller-4", IG4_SKYLAKE},
>+	{ PCI_CHIP_CANNONLAKE_LP_I2C_5, "Intel Cannon Lake-LP I2C Controller-5", IG4_SKYLAKE},
>+	{ PCI_CHIP_CANNONLAKE_H_I2C_0, "Intel Cannon Lake-H I2C Controller-0", IG4_SKYLAKE},
>+	{ PCI_CHIP_CANNONLAKE_H_I2C_1, "Intel Cannon Lake-H I2C Controller-1", IG4_SKYLAKE},
>+	{ PCI_CHIP_CANNONLAKE_H_I2C_2, "Intel Cannon Lake-H I2C Controller-2", IG4_SKYLAKE},
>+	{ PCI_CHIP_CANNONLAKE_H_I2C_3, "Intel Cannon Lake-H I2C Controller-3", IG4_SKYLAKE},
> 	{ PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL},
> 	{ PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL},
> 	{ PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL},

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