Attachment 207677 Details for Bug 240722 – v1

[patch] v1

bug240722.v1.diff (text/plain), 4.34 KB, created by Jan Beich on 2019-09-21 12:53:55 UTC

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Creator: Jan Beich

Created: 2019-09-21 12:53:55 UTC

Size: 4.34 KB

patch

obsolete

>From 12dbc5475810ebc453e22328ef25a78943ad845f Mon Sep 17 00:00:00 2001
>From: Jan Beich <jbeich@FreeBSD.org>
>Date: Sat, 21 Sep 2019 11:18:37 +0000
>Subject: [PATCH] graphics/mesa-dri: fix rendering on AMD devices after r512440
>
>PR:		240722
>Reported by:	Rozhuk Ivan <rozhuk.im@gmail.com>
>---
> graphics/mesa-dri/Makefile            |  2 +-
> graphics/mesa-dri/files/patch-39d0c68 | 16 ++++++++++
> graphics/mesa-dri/files/patch-dded2ed | 46 +++++++++++++++++++++++++++
> 3 files changed, 63 insertions(+), 1 deletion(-)
> create mode 100644 graphics/mesa-dri/files/patch-39d0c68
> create mode 100644 graphics/mesa-dri/files/patch-dded2ed
>
>diff --git a/graphics/mesa-dri/Makefile b/graphics/mesa-dri/Makefile
>index 7e3a4796157bb..0d154cabaec30 100644
>--- a/graphics/mesa-dri/Makefile
>+++ b/graphics/mesa-dri/Makefile
>@@ -3,7 +3,7 @@
> 
> PORTNAME=	mesa-dri
> PORTVERSION=	${MESAVERSION}
>-PORTREVISION=	5
>+PORTREVISION=	6
> CATEGORIES=	graphics
> 
> COMMENT=	OpenGL hardware acceleration drivers for DRI2+
>diff --git a/graphics/mesa-dri/files/patch-39d0c68 b/graphics/mesa-dri/files/patch-39d0c68
>new file mode 100644
>index 0000000000000..251141d58cfed
>--- /dev/null
>+++ b/graphics/mesa-dri/files/patch-39d0c68
>@@ -0,0 +1,16 @@
>+https://gitlab.freedesktop.org/mesa/mesa/commit/39d0c68321df
>+
>+--- src/amd/common/ac_llvm_build.c.orig	2019-01-17 11:26:22 UTC
>++++ src/amd/common/ac_llvm_build.c
>+@@ -401,8 +401,9 @@ ac_build_optimization_barrier(struct ac_llvm_context *
>+ LLVMValueRef
>+ ac_build_shader_clock(struct ac_llvm_context *ctx)
>+ {
>+-	LLVMValueRef tmp = ac_build_intrinsic(ctx, "llvm.readcyclecounter",
>+-					      ctx->i64, NULL, 0, 0);
>++	const char *intr = HAVE_LLVM >= 0x0900 && ctx->chip_class >= VI ?
>++				"llvm.amdgcn.s.memrealtime" : "llvm.readcyclecounter";
>++	LLVMValueRef tmp = ac_build_intrinsic(ctx, intr, ctx->i64, NULL, 0, 0);
>+ 	return LLVMBuildBitCast(ctx->builder, tmp, ctx->v2i32, "");
>+ }
>+ 
>diff --git a/graphics/mesa-dri/files/patch-dded2ed b/graphics/mesa-dri/files/patch-dded2ed
>new file mode 100644
>index 0000000000000..46c966660099d
>--- /dev/null
>+++ b/graphics/mesa-dri/files/patch-dded2ed
>@@ -0,0 +1,46 @@
>+https://gitlab.freedesktop.org/mesa/mesa/commit/dded2edf8bed
>+
>+--- src/gallium/auxiliary/gallivm/lp_bld_arit.c.orig	2019-01-17 11:26:22 UTC
>++++ src/gallium/auxiliary/gallivm/lp_bld_arit.c
>+@@ -555,6 +555,12 @@ lp_build_add(struct lp_build_context *bld,
>+         return bld->one;
>+ 
>+       if (!type.floating && !type.fixed) {
>++         if (HAVE_LLVM >= 0x0900) {
>++            char intrin[32];
>++            intrinsic = type.sign ? "llvm.sadd.sat" : "llvm.uadd.sat";
>++            lp_format_intrinsic(intrin, sizeof intrin, intrinsic, bld->vec_type);
>++            return lp_build_intrinsic_binary(builder, intrin, bld->vec_type, a, b);
>++         }
>+          if (type.width * type.length == 128) {
>+             if (util_cpu_caps.has_sse2) {
>+                if (type.width == 8)
>+@@ -625,6 +631,7 @@ lp_build_add(struct lp_build_context *bld,
>+           * NOTE: cmp/select does sext/trunc of the mask. Does not seem to
>+           * interfere with llvm's ability to recognize the pattern but seems
>+           * a bit brittle.
>++          * NOTE: llvm 9+ always uses (non arch specific) intrinsic.
>+           */
>+          LLVMValueRef overflowed = lp_build_cmp(bld, PIPE_FUNC_GREATER, a, res);
>+          res = lp_build_select(bld, overflowed,
>+@@ -876,6 +883,12 @@ lp_build_sub(struct lp_build_context *bld,
>+         return bld->zero;
>+ 
>+       if (!type.floating && !type.fixed) {
>++         if (HAVE_LLVM >= 0x0900) {
>++            char intrin[32];
>++            intrinsic = type.sign ? "llvm.ssub.sat" : "llvm.usub.sat";
>++            lp_format_intrinsic(intrin, sizeof intrin, intrinsic, bld->vec_type);
>++            return lp_build_intrinsic_binary(builder, intrin, bld->vec_type, a, b);
>++         }
>+          if (type.width * type.length == 128) {
>+             if (util_cpu_caps.has_sse2) {
>+                if (type.width == 8)
>+@@ -925,6 +938,7 @@ lp_build_sub(struct lp_build_context *bld,
>+           * NOTE: cmp/select does sext/trunc of the mask. Does not seem to
>+           * interfere with llvm's ability to recognize the pattern but seems
>+           * a bit brittle.
>++          * NOTE: llvm 9+ always uses (non arch specific) intrinsic.
>+           */
>+          LLVMValueRef no_ov = lp_build_cmp(bld, PIPE_FUNC_GREATER, a, b);
>+          a = lp_build_select(bld, no_ov, a, b);

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