Attachment #207905 for bug #240485




ig4iic_acpi_probe(device_t dev)
{
	ig4iic_softc_t *sc;
	char *hid;
	int rv;

	sc = device_get_softc(dev);
	if (acpi_disabled("ig4iic"))
		return (ENXIO);
	rv = ACPI_ID_PROBE(device_get_parent(dev), dev, ig4iic_ids, NULL);
	if (rv > 0)
		return (rv);

        if (strcmp("AMDI0010", hid) == 0)
                sc->access_intr_mask = 1;
	device_set_desc(dev, "Designware I2C Controller");
	return (rv);
}

	return (0);
}

static int
ig4iic_acpi_suspend(device_t dev)
{
	ig4iic_softc_t *sc = device_get_softc(dev);

	return (ig4iic_suspend(sc));
}

static int
ig4iic_acpi_resume(device_t dev)
{
	ig4iic_softc_t *sc  = device_get_softc(dev);

	return (ig4iic_resume(sc));
}

static device_method_t ig4iic_acpi_methods[] = {
	/* Device interface */
	DEVMETHOD(device_probe, ig4iic_acpi_probe),
	DEVMETHOD(device_attach, ig4iic_acpi_attach),
	DEVMETHOD(device_detach, ig4iic_acpi_detach),
	DEVMETHOD(device_suspend, ig4iic_acpi_suspend),
	DEVMETHOD(device_resume, ig4iic_acpi_resume),

	/* Bus interface */
	DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
	DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
	DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
	DEVMETHOD(bus_release_resource, bus_generic_release_resource),
	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
	DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
	DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
	DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),

	/* iicbus interface */
	DEVMETHOD(iicbus_transfer, ig4iic_transfer),
	DEVMETHOD(iicbus_reset, ig4iic_reset),
	DEVMETHOD(iicbus_callback, ig4iic_callback),

	DEVMETHOD_END
};

static driver_t ig4iic_acpi_driver = {
	"ig4iic",
	ig4iic_acpi_methods,
	sizeof(struct ig4iic_softc),
};

static devclass_t ig4iic_acpi_devclass;
DRIVER_MODULE(ig4iic, acpi, ig4iic_acpi_driver, ig4iic_acpi_devclass, 0, 0);

MODULE_DEPEND(ig4iic, acpi, 1, 1, 1);
MODULE_DEPEND(ig4iic, pci, 1, 1, 1);
MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);
MODULE_VERSION(ig4iic, 1);

Lines 43-55 __FBSDID("$FreeBSD$"); Link Here

(-)b/sys/dev/ichiic/ig4_iic.c (-239 / +630 lines)
43	* See ig4_var.h for locking semantics.	43	* See ig4_var.h for locking semantics.
44	*/	44	*/
45		45
		46	#include "opt_acpi.h"
		47
46	#include <sys/param.h>	48	#include <sys/param.h>
47	#include <sys/systm.h>	49	#include <sys/systm.h>
48	#include <sys/kernel.h>	50	#include <sys/kernel.h>
49	#include <sys/module.h>	51	#include <sys/module.h>
50	#include <sys/errno.h>	52	#include <sys/errno.h>
		53	#include <sys/kdb.h>
51	#include <sys/lock.h>	54	#include <sys/lock.h>
52	#include <sys/mutex.h>	55	#include <sys/mutex.h>
		56	#include <sys/proc.h>
53	#include <sys/sx.h>	57	#include <sys/sx.h>
54	#include <sys/syslog.h>	58	#include <sys/syslog.h>
55	#include <sys/bus.h>	59	#include <sys/bus.h>
Lines 58-76 __FBSDID("$FreeBSD$"); Link Here
58	#include <machine/bus.h>	62	#include <machine/bus.h>
59	#include <sys/rman.h>	63	#include <sys/rman.h>
60		64
61	#include <dev/pci/pcivar.h>	65	#ifdef DEV_ACPI
62	#include <dev/pci/pcireg.h>	66	#include <contrib/dev/acpica/include/acpi.h>
		67	#include <contrib/dev/acpica/include/accommon.h>
		68	#include <dev/acpica/acpivar.h>
		69	#endif
		70
63	#include <dev/iicbus/iicbus.h>	71	#include <dev/iicbus/iicbus.h>
64	#include <dev/iicbus/iiconf.h>	72	#include <dev/iicbus/iiconf.h>
65		73
66	#include <dev/ichiic/ig4_reg.h>	74	#include <dev/ichiic/ig4_reg.h>
67	#include <dev/ichiic/ig4_var.h>	75	#include <dev/ichiic/ig4_var.h>
68		76
69	#define TRANS_NORMAL 1	77	#define DO_POLL(sc) (cold \|\| kdb_active \|\| SCHEDULER_STOPPED() \|\| sc->poll)
70	#define TRANS_PCALL 2
71	#define TRANS_BLOCK 3
72		78
73	static void ig4iic_start(void *xdev);	79	/*
		80	* Clock register values calculation formulas and timings are snarfed from
		81	* Linux driver.
		82	* S_SCL_HCNT = IC clock rate (tHIGH + SDA falling time) - 3
		83	* S_SCL_LCNT = IC clock rate (tLOW + SCL falling time) - 1
		84	* SDA_TX_HOLD = IC clock rate * SDA hold time
		85	* All results are rounded to nearest.
		86	*
		87	* tLOW and tHIGH periods of the SCL clock are taken from I2C specification:
		88	* Speed mode STD FAST FAST+ HIGH
		89	* tHIGH 4.0 ns 0.6 ns 0.26 ns 0.06-0.12 ns
		90	* tLOW 4.7 ns 1.3 ns 0.5 ns 0.16-0.32 ns
		91	*
		92	* HIGH Speed mode tHIGH/tLOW values are depend on bus capacitance.
		93	*/
		94	static const struct ig4_cfg ig4iic_configs[] = {
		95	[IG4_HASWELL] = {
		96	.bus_speed = IG4_CTL_SPEED_FAST,
		97	.ss_scl_hcnt = 432,
		98	.ss_scl_lcnt = 507,
		99	.fs_scl_hcnt = 110,
		100	.fs_scl_lcnt = 160,
		101	.sda_tx_hold = 9,
		102	.txfifo_depth = 32,
		103	.rxfifo_depth = 32,
		104	},
		105	[IG4_ATOM] = {
		106	.bus_speed = IG4_CTL_SPEED_FAST,
		107	.ss_scl_hcnt = 512,
		108	.ss_scl_lcnt = 512,
		109	.fs_scl_hcnt = 85,
		110	.fs_scl_lcnt = 153,
		111	.sda_tx_hold = 6,
		112	.txfifo_depth = 32,
		113	.rxfifo_depth = 32,
		114	},
		115	[IG4_SKYLAKE] = {
		116	/*
		117	* IC clock rate: 120 MHz
		118	* SDA hold time: 230 ns
		119	* SDA falling time: 300 ns
		120	* SCL falling time: 300 ns
		121	*/
		122	.bus_speed = IG4_CTL_SPEED_FAST,
		123	.ss_scl_hcnt = 513,
		124	.ss_scl_lcnt = 599,
		125	.fs_scl_hcnt = 105,
		126	.fs_scl_lcnt = 191,
		127	.sda_tx_hold = 28,
		128	.txfifo_depth = 64,
		129	.rxfifo_depth = 64,
		130	},
		131	[IG4_APL] = {
		132	/*
		133	* IC clock rate: 133 MHz
		134	* SDA hold time: 207 ns
		135	* SDA falling time: 171 ns
		136	* SCL falling time: 208 ns
		137	*/
		138	.bus_speed = IG4_CTL_SPEED_FAST,
		139	.ss_scl_hcnt = 552,
		140	.ss_scl_lcnt = 652,
		141	.fs_scl_hcnt = 100,
		142	.fs_scl_lcnt = 200,
		143	.sda_tx_hold = 28,
144	},
145	[IG4_CANNONLAKE] = {
146	/*
147	* IC clock rate: 216 MHz
148	* SDA hold time: 230 ns
149	* SDA falling time: 300 ns
150	* SCL falling time: 300 ns
151	*/
152	.bus_speed = IG4_CTL_SPEED_FAST,
153	.ss_scl_hcnt = 926,
154	.ss_scl_lcnt = 1079,
155	.fs_scl_hcnt = 192,
156	.fs_scl_lcnt = 345,
157	.sda_tx_hold = 50,
158	.txfifo_depth = 64,
159	.rxfifo_depth = 64,
160	},
161	};
162
163	static int ig4iic_set_config(ig4iic_softc_t *sc, bool reset);
74	static void ig4iic_intr(void *cookie);	164	static void ig4iic_intr(void *cookie);
75	static void ig4iic_dump(ig4iic_softc_t *sc);	165	static void ig4iic_dump(ig4iic_softc_t *sc);
76		166
Lines 78-83 static int ig4_dump; Link Here
78	SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW,	168	SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW,
79	&ig4_dump, 0, "Dump controller registers");	169	&ig4_dump, 0, "Dump controller registers");
80		170
		171	static int ig4_timings;
		172	SYSCTL_INT(_debug, OID_AUTO, ig4_timings, CTLFLAG_RDTUN, &ig4_timings, 0,
		173	"Controller timings 0=ACPI, 1=predefined, 2=legacy, 3=do not change");
		174
81	/*	175	/*
82	* Low-level inline support functions	176	* Low-level inline support functions
83	*/	177	*/
Lines 98-103 reg_read(ig4iic_softc_t *sc, uint32_t reg) Link Here
98	return (value);	192	return (value);
99	}	193	}
100		194
		195	static void
		196	set_intr_mask(ig4iic_softc_t *sc, uint32_t val)
		197	{
		198	if (sc->intr_mask != val) {
		199	reg_write(sc, IG4_REG_INTR_MASK, val);
		200	sc->intr_mask = val;
		201	}
		202	}
		203
		204	static int
		205	intrstat2iic(ig4iic_softc_t *sc, uint32_t val)
		206	{
		207	uint32_t src;
		208
		209	if (val & IG4_INTR_RX_UNDER)
		210	reg_read(sc, IG4_REG_CLR_RX_UNDER);
		211	if (val & IG4_INTR_RX_OVER)
		212	reg_read(sc, IG4_REG_CLR_RX_OVER);
		213	if (val & IG4_INTR_TX_OVER)
		214	reg_read(sc, IG4_REG_CLR_TX_OVER);
		215
		216	if (val & IG4_INTR_TX_ABRT) {
		217	src = reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
		218	reg_read(sc, IG4_REG_CLR_TX_ABORT);
		219	/* User-requested abort. Not really a error */
		220	if (src & IG4_ABRTSRC_TRANSFER)
		221	return (IIC_ESTATUS);
		222	/* Master has lost arbitration */
		223	if (src & IG4_ABRTSRC_ARBLOST)
		224	return (IIC_EBUSBSY);
		225	/* Did not receive an acknowledge from the remote slave */
		226	if (src & (IG4_ABRTSRC_TXNOACK_ADDR7 \|
		227	IG4_ABRTSRC_TXNOACK_ADDR10_1 \|
		228	IG4_ABRTSRC_TXNOACK_ADDR10_2 \|
		229	IG4_ABRTSRC_TXNOACK_DATA \|
		230	IG4_ABRTSRC_GENCALL_NOACK))
		231	return (IIC_ENOACK);
		232	/* Programming errors */
		233	if (src & (IG4_ABRTSRC_GENCALL_READ \|
		234	IG4_ABRTSRC_NORESTART_START \|
		235	IG4_ABRTSRC_NORESTART_10))
		236	return (IIC_ENOTSUPP);
		237	/* Other errors */
		238	if (src & IG4_ABRTSRC_ACKED_START)
		239	return (IIC_EBUSERR);
		240	}
		241	/*
		242	* TX_OVER, RX_OVER and RX_UNDER are caused by wrong RX/TX FIFO depth
		243	* detection or driver's read/write pipelining errors.
		244	*/
		245	if (val & (IG4_INTR_TX_OVER \| IG4_INTR_RX_OVER))
		246	return (IIC_EOVERFLOW);
		247	if (val & IG4_INTR_RX_UNDER)
		248	return (IIC_EUNDERFLOW);
		249
		250	return (IIC_NOERR);
		251	}
		252
101	/*	253	/*
102	* Enable or disable the controller and wait for the controller to acknowledge	254	* Enable or disable the controller and wait for the controller to acknowledge
103	* the state change.	255	* the state change.
Lines 113-124 set_controller(ig4iic_softc_t *sc, uint32_t ctl) Link Here
113	* When the controller is enabled, interrupt on STOP detect	265	* When the controller is enabled, interrupt on STOP detect
114	* or receive character ready and clear pending interrupts.	266	* or receive character ready and clear pending interrupts.
115	*/	267	*/
116	if (ctl & IG4_I2C_ENABLE) {	268	set_intr_mask(sc, 0);
117	reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET \|	269	if (ctl & IG4_I2C_ENABLE)
118	IG4_INTR_RX_FULL);
119	reg_read(sc, IG4_REG_CLR_INTR);	270	reg_read(sc, IG4_REG_CLR_INTR);
120	} else
121	reg_write(sc, IG4_REG_INTR_MASK, 0);
122		271
123	reg_write(sc, IG4_REG_I2C_EN, ctl);	272	reg_write(sc, IG4_REG_I2C_EN, ctl);
124	error = IIC_ETIMEOUT;	273	error = IIC_ETIMEOUT;
Lines 129-147 set_controller(ig4iic_softc_t *sc, uint32_t ctl) Link Here
129	error = 0;	278	error = 0;
130	break;	279	break;
131	}	280	}
132	if (cold)	281	pause("i2cslv", 1);
133	DELAY(1000);
134	else
135	mtx_sleep(sc, &sc->io_lock, 0, "i2cslv", 1);
136	}	282	}
137	return (error);	283	return (error);
138	}	284	}
139		285
140	/*	286	/*
141	* Wait up to 25ms for the requested status using a 25uS polling loop.	287	* Wait up to 25ms for the requested interrupt using a 25uS polling loop.
142	*/	288	*/
143	static int	289	static int
144	wait_status(ig4iic_softc_t *sc, uint32_t status)	290	wait_intr(ig4iic_softc_t *sc, uint32_t intr)
145	{	291	{
146	uint32_t v;	292	uint32_t v;
147	int error;	293	int error;
Lines 151-175 wait_status(ig4iic_softc_t *sc, uint32_t status) Link Here
151		297
152	error = IIC_ETIMEOUT;	298	error = IIC_ETIMEOUT;
153		299
154	for (;;) {	300	while (error == IIC_ETIMEOUT) {
155	/*	301	/*
156	* Check requested status	302	* Check requested status
157	*/	303	*/
158	v = reg_read(sc, IG4_REG_I2C_STA);	304	v = reg_read(sc, IG4_REG_RAW_INTR_STAT);
159	if (v & status) {	305	error = intrstat2iic(sc, v & IG4_INTR_ERR_MASK);
160	error = 0;	306	if (error)
161	break;	307	break;
162	}
163		308
164	/*	309	if (v & intr) {
165	* When waiting for receive data break-out if the interrupt	310	error = 0;
166	* loaded data into the FIFO.	311	break;
167	*/
168	if (status & IG4_STATUS_RX_NOTEMPTY) {
169	if (sc->rpos != sc->rnext) {
170	error = 0;
171	break;
172	}
173	}	312	}
174		313
175	/*	314	/*
Lines 177-183 wait_status(ig4iic_softc_t *sc, uint32_t status) Link Here
177	* reset the timeout if we see a change in the transmit	316	* reset the timeout if we see a change in the transmit
178	* FIFO level as progress is being made.	317	* FIFO level as progress is being made.
179	*/	318	*/
180	if (status & IG4_STATUS_TX_EMPTY) {	319	if (intr & (IG4_INTR_TX_EMPTY \| IG4_INTR_STOP_DET)) {
181	v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;	320	v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;
182	if (txlvl != v) {	321	if (txlvl != v) {
183	txlvl = v;	322	txlvl = v;
Lines 188-232 wait_status(ig4iic_softc_t *sc, uint32_t status) Link Here
188	/*	327	/*
189	* Stop if we've run out of time.	328	* Stop if we've run out of time.
190	*/	329	*/
191	if (count_us >= limit_us)	330	if (count_us >= limit_us) {
		331	error = IIC_ETIMEOUT;
192	break;	332	break;
		333	}
193		334
194	/*	335	/*
195	* When waiting for receive data let the interrupt do its	336	* When polling is not requested let the interrupt do its work.
196	* work, otherwise poll with the lock held.
197	*/	337	*/
198	if (status & IG4_STATUS_RX_NOTEMPTY) {	338	if (!DO_POLL(sc)) {
199	mtx_sleep(sc, &sc->io_lock, 0, "i2cwait",	339	mtx_lock(&sc->io_lock);
		340	sc->error = 0;
		341	set_intr_mask(sc, intr \| IG4_INTR_ERR_MASK);
		342	error = mtx_sleep(sc, &sc->io_lock, 0, "i2cwait",
200	(hz + 99) / 100); /* sleep up to 10ms */	343	(hz + 99) / 100); /* sleep up to 10ms */
		344	if (error != 0)
		345	error = IIC_ETIMEOUT;
		346	else
		347	error = sc->error;
		348	set_intr_mask(sc, 0);
		349	mtx_unlock(&sc->io_lock);
201	count_us += 10000;	350	count_us += 10000;
202	} else {	351	} else {
203	DELAY(25);	352	DELAY(25);
204	count_us += 25;	353	count_us += 25;
		354	error = IIC_ETIMEOUT;
205	}	355	}
206	}	356	}
207		357
208	return (error);	358	return (error);
209	}	359	}
210		360
211	/*
212	* Read I2C data. The data might have already been read by
213	* the interrupt code, otherwise it is sitting in the data
214	* register.
215	*/
216	static uint8_t
217	data_read(ig4iic_softc_t *sc)
218	{
219	uint8_t c;
220
221	if (sc->rpos == sc->rnext) {
222	c = (uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
223	} else {
224	c = sc->rbuf[sc->rpos & IG4_RBUFMASK];
225	++sc->rpos;
226	}
227	return (c);
228	}
229
230	/*	361	/*
231	* Set the slave address. The controller must be disabled when	362	* Set the slave address. The controller must be disabled when
232	* changing the address.	363	* changing the address.
Lines 250-271 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave) Link Here
250		381
251	/*	382	/*
252	* Wait for TXFIFO to drain before disabling the controller.	383	* Wait for TXFIFO to drain before disabling the controller.
253	*
254	* If a write message has not been completed it's really a
255	* programming error, but for now in that case issue an extra
256	* byte + STOP.
257	*
258	* If a read message has not been completed it's also a programming
259	* error, for now just ignore it.
260	*/	384	*/
261	wait_status(sc, IG4_STATUS_TX_NOTFULL);	385	wait_intr(sc, IG4_INTR_TX_EMPTY);
262	if (sc->write_started) {
263	reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_STOP);
264	sc->write_started = 0;
265	}
266	if (sc->read_started)
267	sc->read_started = 0;
268	wait_status(sc, IG4_STATUS_TX_EMPTY);
269		386
270	set_controller(sc, 0);	387	set_controller(sc, 0);
271	ctl = reg_read(sc, IG4_REG_CTL);	388	ctl = reg_read(sc, IG4_REG_CTL);
Lines 288-335 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave) Link Here
288	* IICBUS API FUNCTIONS	405	* IICBUS API FUNCTIONS
289	*/	406	*/
290	static int	407	static int
291	ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave)	408	ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave, bool repeated_start)
292	{	409	{
293	set_slave_addr(sc, slave >> 1);	410	set_slave_addr(sc, slave >> 1);
		411
		412	if (!repeated_start) {
		413	/*
		414	* Clear any previous TX/RX FIFOs overflow/underflow bits
		415	* and I2C bus STOP condition.
		416	*/
		417	reg_read(sc, IG4_REG_CLR_INTR);
		418	}
		419
294	return (0);	420	return (0);
295	}	421	}
296		422
		423	static int
		424	ig4iic_xfer_abort(ig4iic_softc_t *sc)
		425	{
		426	int error;
		427
		428	/* Request send of STOP condition and flush of TX FIFO */
		429	set_controller(sc, IG4_I2C_ABORT \| IG4_I2C_ENABLE);
		430	/*
		431	* Wait for the TX_ABRT interrupt with ABRTSRC_TRANSFER
		432	* bit set in TX_ABRT_SOURCE register.
		433	*/
		434	error = wait_intr(sc, IG4_INTR_STOP_DET);
		435	set_controller(sc, IG4_I2C_ENABLE);
		436
		437	return (error == IIC_ESTATUS ? 0 : error);
		438	}
		439
		440	/*
		441	* Amount of unread data before next burst to get better I2C bus utilization.
		442	* 2 bytes is enough in FAST mode. 8 bytes is better in FAST+ and HIGH modes.
		443	* Intel-recommended value is 16 for DMA transfers with 64-byte depth FIFOs.
		444	*/
		445	#define IG4_FIFO_LOWAT 2
		446
297	static int	447	static int
298	ig4iic_read(ig4iic_softc_t sc, uint8_t buf, uint16_t len,	448	ig4iic_read(ig4iic_softc_t sc, uint8_t buf, uint16_t len,
299	bool repeated_start, bool stop)	449	bool repeated_start, bool stop)
300	{	450	{
301	uint32_t cmd;	451	uint32_t cmd;
302	uint16_t i;	452	int requested = 0;
		453	int received = 0;
		454	int burst, target, lowat = 0;
303	int error;	455	int error;
304		456
305	if (len == 0)	457	if (len == 0)
306	return (0);	458	return (0);
307		459
308	cmd = IG4_DATA_COMMAND_RD;	460	while (received < len) {
309	cmd \|= repeated_start ? IG4_DATA_RESTART : 0;	461	burst = sc->cfg.txfifo_depth -
310	cmd \|= stop && len == 1 ? IG4_DATA_STOP : 0;	462	(reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);
311		463	if (burst <= 0) {
312	/* Issue request for the first byte (could be last as well). */	464	error = wait_intr(sc, IG4_INTR_TX_EMPTY);
313	reg_write(sc, IG4_REG_DATA_CMD, cmd);	465	if (error)
314		466	break;
315	for (i = 0; i < len; i++) {	467	burst = sc->cfg.txfifo_depth;
316	/*	468	}
317	* Maintain a pipeline by queueing the allowance for the next	469	/* Ensure we have enough free space in RXFIFO */
318	* read before waiting for the current read.	470	burst = MIN(burst, sc->cfg.rxfifo_depth - lowat);
319	*/	471	target = MIN(requested + burst, (int)len);
320	cmd = IG4_DATA_COMMAND_RD;	472	while (requested < target) {
321	if (i < len - 1) {
322	cmd = IG4_DATA_COMMAND_RD;	473	cmd = IG4_DATA_COMMAND_RD;
323	cmd \|= stop && i == len - 2 ? IG4_DATA_STOP : 0;	474	if (repeated_start && requested == 0)
		475	cmd \|= IG4_DATA_RESTART;
		476	if (stop && requested == len - 1)
		477	cmd \|= IG4_DATA_STOP;
324	reg_write(sc, IG4_REG_DATA_CMD, cmd);	478	reg_write(sc, IG4_REG_DATA_CMD, cmd);
		479	requested++;
		480	}
		481	/* Leave some data queued to maintain the hardware pipeline */
		482	lowat = 0;
		483	if (requested != len && requested - received > IG4_FIFO_LOWAT)
		484	lowat = IG4_FIFO_LOWAT;
		485	/* After TXFLR fills up, clear it by reading available data */
		486	while (received < requested - lowat) {
		487	burst = MIN((int)len - received,
		488	reg_read(sc, IG4_REG_RXFLR) & IG4_FIFOLVL_MASK);
		489	if (burst > 0) {
		490	while (burst--)
		491	buf[received++] = 0xFF &
		492	reg_read(sc, IG4_REG_DATA_CMD);
		493	} else {
		494	error = wait_intr(sc, IG4_INTR_RX_FULL);
		495	if (error)
		496	goto out;
		497	}
325	}	498	}
326	error = wait_status(sc, IG4_STATUS_RX_NOTEMPTY);
327	if (error)
328	break;
329	buf[i] = data_read(sc);
330	}	499	}
331		500	out:
332	(void)reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
333	return (error);	501	return (error);
334	}	502	}
335		503
Lines 338-361 ig4iic_write(ig4iic_softc_t sc, uint8_t buf, uint16_t len, Link Here
338	bool repeated_start, bool stop)	506	bool repeated_start, bool stop)
339	{	507	{
340	uint32_t cmd;	508	uint32_t cmd;
341	uint16_t i;	509	int sent = 0;
		510	int burst, target;
342	int error;	511	int error;
		512	bool lowat_set = false;
343		513
344	if (len == 0)	514	if (len == 0)
345	return (0);	515	return (0);
346		516
347	cmd = repeated_start ? IG4_DATA_RESTART : 0;	517	while (sent < len) {
348	for (i = 0; i < len; i++) {	518	burst = sc->cfg.txfifo_depth -
349	error = wait_status(sc, IG4_STATUS_TX_NOTFULL);	519	(reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);
350	if (error)	520	target = MIN(sent + burst, (int)len);
351	break;	521	/* Leave some data queued to maintain the hardware pipeline */
352	cmd \|= buf[i];	522	if (sent == 0 && target != len) {
353	cmd \|= stop && i == len - 1 ? IG4_DATA_STOP : 0;	523	lowat_set = true;
354	reg_write(sc, IG4_REG_DATA_CMD, cmd);	524	reg_write(sc, IG4_REG_TX_TL, IG4_FIFO_LOWAT);
355	cmd = 0;	525	}
		526	while(sent < target) {
		527	cmd = buf[sent];
		528	if (repeated_start && sent == 0)
		529	cmd \|= IG4_DATA_RESTART;
		530	if (stop && sent == len - 1)
		531	cmd \|= IG4_DATA_STOP;
		532	reg_write(sc, IG4_REG_DATA_CMD, cmd);
		533	sent++;
		534	}
		535	if (sent < len) {
		536	error = wait_intr(sc, IG4_INTR_TX_EMPTY);
		537	if (error)
		538	break;
		539	}
356	}	540	}
		541	if (lowat_set)
		542	reg_write(sc, IG4_REG_TX_TL, 0);
357		543
358	(void)reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
359	return (error);	544	return (error);
360	}	545	}
361		546
Lines 369-374 ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) Link Here
369	int unit;	554	int unit;
370	bool rpstart;	555	bool rpstart;
371	bool stop;	556	bool stop;
		557	bool allocated;
372		558
373	/*	559	/*
374	* The hardware interface imposes limits on allowed I2C messages.	560	* The hardware interface imposes limits on allowed I2C messages.
Lines 429-436 ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) Link Here
429	return (IIC_ENOTSUPP);	615	return (IIC_ENOTSUPP);
430	}	616	}
431		617
432	sx_xlock(&sc->call_lock);	618	/* Check if device is already allocated with iicbus_request_bus() */
433	mtx_lock(&sc->io_lock);	619	allocated = sx_xlocked(&sc->call_lock) != 0;
		620	if (!allocated)
		621	sx_xlock(&sc->call_lock);
434		622
435	/* Debugging - dump registers. */	623	/* Debugging - dump registers. */
436	if (ig4_dump) {	624	if (ig4_dump) {
Lines 447-467 ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) Link Here
447	*/	635	*/
448	reg_read(sc, IG4_REG_CLR_TX_ABORT);	636	reg_read(sc, IG4_REG_CLR_TX_ABORT);
449		637
450	/*
451	* Clean out any previously received data.
452	*/
453	if (sc->rpos != sc->rnext && bootverbose) {
454	device_printf(sc->dev, "discarding %d bytes of spurious data\n",
455	sc->rnext - sc->rpos);
456	}
457	sc->rpos = 0;
458	sc->rnext = 0;
459
460	rpstart = false;	638	rpstart = false;
461	error = 0;	639	error = 0;
462	for (i = 0; i < nmsgs; i++) {	640	for (i = 0; i < nmsgs; i++) {
463	if ((msgs[i].flags & IIC_M_NOSTART) == 0) {	641	if ((msgs[i].flags & IIC_M_NOSTART) == 0) {
464	error = ig4iic_xfer_start(sc, msgs[i].slave);	642	error = ig4iic_xfer_start(sc, msgs[i].slave, rpstart);
465	} else {	643	} else {
466	if (!sc->slave_valid \|\|	644	if (!sc->slave_valid \|\|
467	(msgs[i].slave >> 1) != sc->last_slave) {	645	(msgs[i].slave >> 1) != sc->last_slave) {
Lines 482-495 ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) Link Here
482	else	660	else
483	error = ig4iic_write(sc, msgs[i].buf, msgs[i].len,	661	error = ig4iic_write(sc, msgs[i].buf, msgs[i].len,
484	rpstart, stop);	662	rpstart, stop);
485	if (error != 0)	663
		664	/* Wait for error or stop condition occurred on the I2C bus */
		665	if (stop && error == 0) {
		666	error = wait_intr(sc, IG4_INTR_STOP_DET);
		667	if (error == 0)
		668	reg_read(sc, IG4_REG_CLR_INTR);
		669	}
		670
		671	if (error != 0) {
		672	/*
		673	* Send STOP condition if it's not done yet and flush
		674	* both FIFOs. Do a controller soft reset if transfer
		675	* abort is failed.
		676	*/
		677	if (((reg_read(sc, IG4_REG_RAW_INTR_STAT) &
		678	(IG4_INTR_START_DET \| IG4_INTR_STOP_DET))
		679	== IG4_INTR_START_DET) &&
		680	ig4iic_xfer_abort(sc) != 0) {
		681	device_printf(sc->dev, "Failed to abort "
		682	"transfer. Do the controller reset.\n");
		683	ig4iic_set_config(sc, true);
		684	} else {
		685	while (reg_read(sc, IG4_REG_I2C_STA) &
		686	IG4_STATUS_RX_NOTEMPTY)
		687	reg_read(sc, IG4_REG_DATA_CMD);
		688	reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
		689	reg_read(sc, IG4_REG_CLR_INTR);
		690	}
486	break;	691	break;
		692	}
487		693
488	rpstart = !stop;	694	rpstart = !stop;
489	}	695	}
490		696
491	mtx_unlock(&sc->io_lock);	697	if (!allocated)
492	sx_unlock(&sc->call_lock);	698	sx_unlock(&sc->call_lock);
493	return (error);	699	return (error);
494	}	700	}
495		701
Lines 497-505 int Link Here
497	ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)	703	ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
498	{	704	{
499	ig4iic_softc_t *sc = device_get_softc(dev);	705	ig4iic_softc_t *sc = device_get_softc(dev);
		706	bool allocated;
500		707
501	sx_xlock(&sc->call_lock);	708	allocated = sx_xlocked(&sc->call_lock) != 0;
502	mtx_lock(&sc->io_lock);	709	if (!allocated)
		710	sx_xlock(&sc->call_lock);
503		711
504	/* TODO handle speed configuration? */	712	/* TODO handle speed configuration? */
505	if (oldaddr != NULL)	713	if (oldaddr != NULL)
Lines 508-538 ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) Link Here
508	if (addr == IIC_UNKNOWN)	716	if (addr == IIC_UNKNOWN)
509	sc->slave_valid = false;	717	sc->slave_valid = false;
510		718
511	mtx_unlock(&sc->io_lock);	719	if (!allocated)
512	sx_unlock(&sc->call_lock);	720	sx_unlock(&sc->call_lock);
513	return (0);	721	return (0);
514	}	722	}
515		723
516	/*
517	* Called from ig4iic_pci_attach/detach()
518	*/
519	int	724	int
520	ig4iic_attach(ig4iic_softc_t *sc)	725	ig4iic_callback(device_t dev, int index, caddr_t data)
		726	{
		727	ig4iic_softc_t *sc = device_get_softc(dev);
		728	int error = 0;
		729	int how;
		730
		731	/*
		732	* Unfortunately, iicbus_request_bus() can return error code in both
		733	* formats, POSIX and IIC. Here we use EAGAIN instead of IIC_EBUSBSY
		734	* to match other possibly buggy iicbus_callback implementations.
		735	* As iicbus_poll() returns IIC_EBUSBSY, caller should check returned
		736	* value for both EAGAIN and IIC_EBUSBSY. Other error codes are POSIX.
		737	*/
		738	switch (index) {
		739	case IIC_REQUEST_BUS:
		740	/* force polling if ig4iic is requested with IIC_DONTWAIT */
		741	how = (int )data;
		742	if ((how & IIC_WAIT) == 0) {
		743	if (sx_try_xlock(&sc->call_lock) == 0)
		744	error = EWOULDBLOCK;
		745	else
		746	sc->poll = true;
		747	} else
		748	sx_xlock(&sc->call_lock);
		749	break;
		750
		751	case IIC_RELEASE_BUS:
		752	sc->poll = false;
		753	sx_unlock(&sc->call_lock);
		754	break;
		755
		756	default:
		757	error = EINVAL;
		758	}
		759
		760	return (error);
		761	}
		762
		763	#ifdef DEV_ACPI
		764	static int
		765	ig4iic_acpi_params(ig4iic_softc_t sc, char method,
		766	uint16_t scl_hcnt, uint16_t scl_lcnt, uint16_t *sda_tx_hold)
521	{	767	{
		768	ACPI_BUFFER buf;
		769	ACPI_HANDLE handle;
		770	ACPI_OBJECT obj, elems;
522	int error;	771	int error;
		772
		773	handle = acpi_get_handle(sc->dev);
		774	if (handle == NULL)
		775	return (ENXIO);
		776
		777	buf.Pointer = NULL;
		778	buf.Length = ACPI_ALLOCATE_BUFFER;
		779
		780	if (ACPI_FAILURE(AcpiEvaluateObject(handle, method, NULL, &buf)))
		781	return (ENXIO);
		782
		783	error = ENXIO;
		784	obj = (ACPI_OBJECT *)buf.Pointer;
		785	if (obj->Type == ACPI_TYPE_PACKAGE && obj->Package.Count == 3) {
		786	elems = obj->Package.Elements;
		787	*scl_hcnt = elems[0].Integer.Value & IG4_SCL_CLOCK_MASK;
		788	*scl_lcnt = elems[1].Integer.Value & IG4_SCL_CLOCK_MASK;
		789	*sda_tx_hold = elems[2].Integer.Value & IG4_SDA_TX_HOLD_MASK;
		790	error = 0;
		791	}
		792
		793	AcpiOsFree(obj);
		794
		795	return (error);
		796	}
		797	#endif /* DEV_ACPI */
		798
		799	static void
		800	ig4iic_get_config(ig4iic_softc_t *sc)
		801	{
		802	const struct ig4_cfg *cfg;
523	uint32_t v;	803	uint32_t v;
		804	#ifdef DEV_ACPI
		805	uint16_t sda_tx_hold;
		806	#endif
524		807
525	mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_DEF);	808	/* Fetch default hardware config from controller */
526	sx_init(&sc->call_lock, "IG4 call lock");	809	sc->cfg.version = reg_read(sc, IG4_REG_COMP_VER);
		810	sc->cfg.bus_speed = reg_read(sc, IG4_REG_CTL) & IG4_CTL_SPEED_MASK;
		811	sc->cfg.ss_scl_hcnt =
		812	reg_read(sc, IG4_REG_SS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;
		813	sc->cfg.ss_scl_lcnt =
		814	reg_read(sc, IG4_REG_SS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;
		815	sc->cfg.fs_scl_hcnt =
		816	reg_read(sc, IG4_REG_FS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;
		817	sc->cfg.fs_scl_lcnt =
		818	reg_read(sc, IG4_REG_FS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;
		819	sc->cfg.sda_tx_hold =
		820	reg_read(sc, IG4_REG_SDA_HOLD) & IG4_SDA_TX_HOLD_MASK;
		821
		822	if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {
		823	/* REG_COMP_PARAM1 register is not documented in Intel specs */
		824	v = reg_read(sc, IG4_REG_COMP_PARAM1);
		825	if (IG4_PARAM1_TXFIFO_DEPTH(v) != 0)
		826	sc->cfg.txfifo_depth = IG4_PARAM1_TXFIFO_DEPTH(v);
		827	if (IG4_PARAM1_RXFIFO_DEPTH(v) != 0)
		828	sc->cfg.rxfifo_depth = IG4_PARAM1_RXFIFO_DEPTH(v);
		829	} else {
		830	/*
		831	* Hardware does not allow FIFO Threshold Levels value to be
		832	* set larger than the depth of the buffer. If an attempt is
		833	* made to do that, the actual value set will be the maximum
		834	* depth of the buffer.
		835	*/
		836	v = reg_read(sc, IG4_REG_TX_TL);
		837	reg_write(sc, IG4_REG_TX_TL, v \| IG4_FIFO_MASK);
		838	sc->cfg.txfifo_depth =
		839	(reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1;
		840	reg_write(sc, IG4_REG_TX_TL, v);
		841	v = reg_read(sc, IG4_REG_RX_TL);
		842	reg_write(sc, IG4_REG_RX_TL, v \| IG4_FIFO_MASK);
		843	sc->cfg.rxfifo_depth =
		844	(reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1;
		845	reg_write(sc, IG4_REG_RX_TL, v);
		846	}
		847
		848	/* Override hardware config with precalculated counter values */
		849	if (ig4_timings < 2 && sc->version < nitems(ig4iic_configs)) {
		850	cfg = &ig4iic_configs[sc->version];
		851	if (cfg->bus_speed != 0)
		852	sc->cfg.bus_speed = cfg->bus_speed;
		853	if (cfg->ss_scl_hcnt != 0)
		854	sc->cfg.ss_scl_hcnt = cfg->ss_scl_hcnt;
		855	if (cfg->ss_scl_lcnt != 0)
		856	sc->cfg.ss_scl_lcnt = cfg->ss_scl_lcnt;
		857	if (cfg->fs_scl_hcnt != 0)
		858	sc->cfg.fs_scl_hcnt = cfg->fs_scl_hcnt;
		859	if (cfg->fs_scl_lcnt != 0)
		860	sc->cfg.fs_scl_lcnt = cfg->fs_scl_lcnt;
		861	if (cfg->sda_tx_hold != 0)
		862	sc->cfg.sda_tx_hold = cfg->sda_tx_hold;
		863	if (cfg->txfifo_depth != 0)
		864	sc->cfg.txfifo_depth = cfg->txfifo_depth;
		865	if (cfg->rxfifo_depth != 0)
		866	sc->cfg.rxfifo_depth = cfg->rxfifo_depth;
		867	} else if (ig4_timings == 2) {
		868	/*
		869	* Traditional (Haswell?) timings of original ig4 driver.
		870	* Program based on a 25000 Hz clock. This is a bit of a
		871	* hack (obviously). The defaults are 400 and 470 for standard
		872	* and 60 and 130 for fast. The defaults for standard fail
		873	* utterly (presumably cause an abort) because the clock time
874	* is ~18.8ms by default. This brings it down to ~4ms.
875	*/
876	sc->cfg.bus_speed = IG4_CTL_SPEED_STD;
877	sc->cfg.ss_scl_hcnt = 100;
878	sc->cfg.ss_scl_lcnt = 125;
879	sc->cfg.fs_scl_hcnt = 100;
880	sc->cfg.fs_scl_lcnt = 125;
881	/* XXX: SDA_HOLD=28 is valid for Skylake controllers only */
882	if (IG4_HAS_ADDREGS(sc->version))
883	sc->cfg.sda_tx_hold = 28;
884	sc->cfg.txfifo_depth = 16; /* Very conservative value */
885	sc->cfg.rxfifo_depth = 16;
886	}
887
888	if (sc->cfg.bus_speed != IG4_CTL_SPEED_STD)
889	sc->cfg.bus_speed = IG4_CTL_SPEED_FAST;
890
891	#ifdef DEV_ACPI
892	/* Evaluate SSCN and FMCN ACPI methods to fetch timings */
893	if (ig4_timings == 0 &&
894	ig4iic_acpi_params(sc, "SSCN",
895	&sc->cfg.ss_scl_hcnt, &sc->cfg.ss_scl_lcnt, &sda_tx_hold) == 0 &&
896	sc->cfg.bus_speed == IG4_CTL_SPEED_STD &&
897	sda_tx_hold != 0)
898	sc->cfg.sda_tx_hold = sda_tx_hold;
899	if (ig4_timings == 0 &&
900	ig4iic_acpi_params(sc, "FMCN",
901	&sc->cfg.fs_scl_hcnt, &sc->cfg.fs_scl_lcnt, &sda_tx_hold) == 0 &&
902	sc->cfg.bus_speed == IG4_CTL_SPEED_FAST &&
903	sda_tx_hold != 0)
904	sc->cfg.sda_tx_hold = sda_tx_hold;
905	#endif
906	}
907
908	static int
909	ig4iic_set_config(ig4iic_softc_t *sc, bool reset)
910	{
911	uint32_t v;
527		912
528	v = reg_read(sc, IG4_REG_DEVIDLE_CTRL);	913	v = reg_read(sc, IG4_REG_DEVIDLE_CTRL);
529	if (sc->version == IG4_SKYLAKE && (v & IG4_RESTORE_REQUIRED) ) {	914	if (IG4_HAS_ADDREGS(sc->version) && (v & IG4_RESTORE_REQUIRED)) {
530	reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE \| IG4_RESTORE_REQUIRED);	915	reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE \| IG4_RESTORE_REQUIRED);
531	reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0);	916	reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0);
		917	pause("i2crst", 1);
		918	reset = true;
		919	}
532		920
		921	if ((sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) && reset) {
		922	reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW);
		923	reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW);
		924	} else if (IG4_HAS_ADDREGS(sc->version) && reset) {
533	reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);	925	reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
534	reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);	926	reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);
535	DELAY(1000);
536	}	927	}
537		928
538	if (sc->version == IG4_ATOM)	929	if (sc->version == IG4_ATOM)
Lines 556-597 ig4iic_attach(ig4iic_softc_t *sc) Link Here
556	if (sc->version == IG4_HASWELL) {	947	if (sc->version == IG4_HASWELL) {
557	v = reg_read(sc, IG4_REG_SW_LTR_VALUE);	948	v = reg_read(sc, IG4_REG_SW_LTR_VALUE);
558	v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);	949	v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);
559	} else if (sc->version == IG4_SKYLAKE) {	950	} else if (IG4_HAS_ADDREGS(sc->version)) {
560	v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE);	951	v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE);
561	v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE);	952	v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE);
562	}	953	}
563		954
564	if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {	955	if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {
565	v = reg_read(sc, IG4_REG_COMP_VER);	956	v = reg_read(sc, IG4_REG_COMP_VER);
566	if (v < IG4_COMP_MIN_VER) {	957	if (v < IG4_COMP_MIN_VER)
567	error = ENXIO;	958	return(ENXIO);
568	goto done;
569	}
570	}	959	}
571	v = reg_read(sc, IG4_REG_SS_SCL_HCNT);
572	v = reg_read(sc, IG4_REG_SS_SCL_LCNT);
573	v = reg_read(sc, IG4_REG_FS_SCL_HCNT);
574	v = reg_read(sc, IG4_REG_FS_SCL_LCNT);
575	v = reg_read(sc, IG4_REG_SDA_HOLD);
576		960
577	v = reg_read(sc, IG4_REG_SS_SCL_HCNT);	961	if (set_controller(sc, 0)) {
578	reg_write(sc, IG4_REG_FS_SCL_HCNT, v);	962	device_printf(sc->dev, "controller error during attach-1\n");
579	v = reg_read(sc, IG4_REG_SS_SCL_LCNT);	963	return (ENXIO);
580	reg_write(sc, IG4_REG_FS_SCL_LCNT, v);	964	}
581		965
582	/*	966	reg_read(sc, IG4_REG_CLR_INTR);
583	* Program based on a 25000 Hz clock. This is a bit of a	967	reg_write(sc, IG4_REG_INTR_MASK, 0);
584	* hack (obviously). The defaults are 400 and 470 for standard	968	sc->intr_mask = 0;
585	* and 60 and 130 for fast. The defaults for standard fail	969
586	* utterly (presumably cause an abort) because the clock time	970	reg_write(sc, IG4_REG_SS_SCL_HCNT, sc->cfg.ss_scl_hcnt);
587	* is ~18.8ms by default. This brings it down to ~4ms (for now).	971	reg_write(sc, IG4_REG_SS_SCL_LCNT, sc->cfg.ss_scl_lcnt);
588	*/	972	reg_write(sc, IG4_REG_FS_SCL_HCNT, sc->cfg.fs_scl_hcnt);
589	reg_write(sc, IG4_REG_SS_SCL_HCNT, 100);	973	reg_write(sc, IG4_REG_FS_SCL_LCNT, sc->cfg.fs_scl_lcnt);
590	reg_write(sc, IG4_REG_SS_SCL_LCNT, 125);	974	reg_write(sc, IG4_REG_SDA_HOLD, sc->cfg.sda_tx_hold);
591	reg_write(sc, IG4_REG_FS_SCL_HCNT, 100);
592	reg_write(sc, IG4_REG_FS_SCL_LCNT, 125);
593	if (sc->version == IG4_SKYLAKE)
594	reg_write(sc, IG4_REG_SDA_HOLD, 28);
595		975
596	/*	976	/*
597	* Use a threshold of 1 so we get interrupted on each character,	977	* Use a threshold of 1 so we get interrupted on each character,
Lines 600-612 ig4iic_attach(ig4iic_softc_t *sc) Link Here
600	*	980	*
601	* See ig4_var.h for details on interrupt handler synchronization.	981	* See ig4_var.h for details on interrupt handler synchronization.
602	*/	982	*/
603	reg_write(sc, IG4_REG_RX_TL, 1);	983	reg_write(sc, IG4_REG_RX_TL, 0);
		984	reg_write(sc, IG4_REG_TX_TL, 0);
604		985
605	reg_write(sc, IG4_REG_CTL,	986	reg_write(sc, IG4_REG_CTL,
606	IG4_CTL_MASTER \|	987	IG4_CTL_MASTER \|
607	IG4_CTL_SLAVE_DISABLE \|	988	IG4_CTL_SLAVE_DISABLE \|
608	IG4_CTL_RESTARTEN \|	989	IG4_CTL_RESTARTEN \|
609	IG4_CTL_SPEED_STD);	990	(sc->cfg.bus_speed & IG4_CTL_SPEED_MASK));
		991
		992	/* Force setting of the target address on the next transfer */
		993	sc->slave_valid = 0;
		994
		995	return (0);
		996	}
		997
		998	/*
		999	* Called from ig4iic_pci_attach/detach()
		1000	*/
		1001	int
		1002	ig4iic_attach(ig4iic_softc_t *sc)
		1003	{
		1004	int error;
		1005
		1006	mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_DEF);
		1007	sx_init(&sc->call_lock, "IG4 call lock");
		1008
		1009	ig4iic_get_config(sc);
		1010
		1011	error = ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version));
		1012	if (error)
		1013	goto done;
610		1014
611	sc->iicbus = device_add_child(sc->dev, "iicbus", -1);	1015	sc->iicbus = device_add_child(sc->dev, "iicbus", -1);
612	if (sc->iicbus == NULL) {	1016	if (sc->iicbus == NULL) {
Lines 615-639 ig4iic_attach(ig4iic_softc_t *sc) Link Here
615	goto done;	1019	goto done;
616	}	1020	}
617		1021
618	#if 0	1022	if (set_controller(sc, IG4_I2C_ENABLE)) {
619	/*
620	* Don't do this, it blows up the PCI config
621	*/
622	if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {
623	reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW);
624	reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW);
625	} else if (sc->version = IG4_SKYLAKE) {
626	reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
627	reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);
628	}
629	#endif
630
631	mtx_lock(&sc->io_lock);
632	if (set_controller(sc, 0))
633	device_printf(sc->dev, "controller error during attach-1\n");
634	if (set_controller(sc, IG4_I2C_ENABLE))
635	device_printf(sc->dev, "controller error during attach-2\n");	1023	device_printf(sc->dev, "controller error during attach-2\n");
636	mtx_unlock(&sc->io_lock);	1024	error = ENXIO;
		1025	goto done;
		1026	}
		1027	if (set_controller(sc, 0)) {
		1028	device_printf(sc->dev, "controller error during attach-3\n");
		1029	error = ENXIO;
		1030	goto done;
		1031	}
637	error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC \| INTR_MPSAFE,	1032	error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC \| INTR_MPSAFE,
638	NULL, ig4iic_intr, sc, &sc->intr_handle);	1033	NULL, ig4iic_intr, sc, &sc->intr_handle);
639	if (error) {	1034	if (error) {
Lines 641-678 ig4iic_attach(ig4iic_softc_t *sc) Link Here
641	"Unable to setup irq: error %d\n", error);	1036	"Unable to setup irq: error %d\n", error);
642	}	1037	}
643		1038
644	sc->enum_hook.ich_func = ig4iic_start;
645	sc->enum_hook.ich_arg = sc->dev;
646
647	/*
648	* We have to wait until interrupts are enabled. I2C read and write
649	* only works if the interrupts are available.
650	*/
651	if (config_intrhook_establish(&sc->enum_hook) != 0)
652	error = ENOMEM;
653	else
654	error = 0;
655
656	done:
657	return (error);
658	}
659
660	void
661	ig4iic_start(void *xdev)
662	{
663	int error;
664	ig4iic_softc_t *sc;
665	device_t dev = (device_t)xdev;
666
667	sc = device_get_softc(dev);
668
669	config_intrhook_disestablish(&sc->enum_hook);
670
671	error = bus_generic_attach(sc->dev);	1039	error = bus_generic_attach(sc->dev);
672	if (error) {	1040	if (error) {
673	device_printf(sc->dev,	1041	device_printf(sc->dev,
674	"failed to attach child: error %d\n", error);	1042	"failed to attach child: error %d\n", error);
675	}	1043	}
		1044
		1045	done:
		1046	return (error);
676	}	1047	}
677		1048
678	int	1049	int
Lines 691-704 ig4iic_detach(ig4iic_softc_t *sc) Link Here
691	bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle);	1062	bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle);
692		1063
693	sx_xlock(&sc->call_lock);	1064	sx_xlock(&sc->call_lock);
694	mtx_lock(&sc->io_lock);
695		1065
696	sc->iicbus = NULL;	1066	sc->iicbus = NULL;
697	sc->intr_handle = NULL;	1067	sc->intr_handle = NULL;
698	reg_write(sc, IG4_REG_INTR_MASK, 0);	1068	reg_write(sc, IG4_REG_INTR_MASK, 0);
699	set_controller(sc, 0);	1069	set_controller(sc, 0);
700		1070
701	mtx_unlock(&sc->io_lock);
702	sx_xunlock(&sc->call_lock);	1071	sx_xunlock(&sc->call_lock);
703		1072
704	mtx_destroy(&sc->io_lock);	1073	mtx_destroy(&sc->io_lock);
Lines 707-712 ig4iic_detach(ig4iic_softc_t *sc) Link Here
707	return (0);	1076	return (0);
708	}	1077	}
709		1078
		1079	int
		1080	ig4iic_suspend(ig4iic_softc_t *sc)
		1081	{
		1082	int error;
		1083
		1084	/* suspend all children */
		1085	error = bus_generic_suspend(sc->dev);
		1086
		1087	sx_xlock(&sc->call_lock);
		1088	set_controller(sc, 0);
		1089	if (IG4_HAS_ADDREGS(sc->version)) {
		1090	/*
		1091	* Place the device in the idle state, just to be safe
		1092	*/
		1093	reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE);
		1094	/*
		1095	* Controller can become unfunctional if I2C lines are pulled
		1096	* down when suspend procedure turns off power to I2C device.
		1097	* Place device in the reset state to avoid this.
		1098	*/
		1099	reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
		1100	}
		1101	sx_xunlock(&sc->call_lock);
		1102
		1103	return (error);
		1104	}
		1105
		1106	int ig4iic_resume(ig4iic_softc_t *sc)
		1107	{
		1108	int error;
		1109
		1110	sx_xlock(&sc->call_lock);
		1111	if (ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version)))
		1112	device_printf(sc->dev, "controller error during resume\n");
		1113	sx_xunlock(&sc->call_lock);
		1114
		1115	error = bus_generic_resume(sc->dev);
		1116
		1117	return (error);
		1118	}
		1119
710	/*	1120	/*
711	* Interrupt Operation, see ig4_var.h for locking semantics.	1121	* Interrupt Operation, see ig4_var.h for locking semantics.
712	*/	1122	*/
Lines 717-745 ig4iic_intr(void *cookie) Link Here
717	uint32_t status;	1127	uint32_t status;
718		1128
719	mtx_lock(&sc->io_lock);	1129	mtx_lock(&sc->io_lock);
720	/* reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET);*/	1130	if (sc->intr_mask != 0) {
721	reg_read(sc, IG4_REG_CLR_INTR);	1131	status = reg_read(sc, IG4_REG_INTR_STAT);
722	status = reg_read(sc, IG4_REG_I2C_STA);	1132	set_intr_mask(sc, 0);
723	while (status & IG4_STATUS_RX_NOTEMPTY) {	1133	sc->error = intrstat2iic(sc, status);
724	sc->rbuf[sc->rnext & IG4_RBUFMASK] =	1134	wakeup(sc);
725	(uint8_t)reg_read(sc, IG4_REG_DATA_CMD);	1135	} else
726	++sc->rnext;	1136	reg_write(sc, IG4_REG_INTR_MASK, 0);
727	status = reg_read(sc, IG4_REG_I2C_STA);
728	}
729
730	/*
731	* Workaround to trigger pending interrupt if IG4_REG_INTR_STAT
732	* is changed after clearing it
733	*/
734	if (sc->access_intr_mask != 0) {
735	status = reg_read(sc, IG4_REG_INTR_MASK);
736	if (status != 0) {
737	reg_write(sc, IG4_REG_INTR_MASK, 0);
738	reg_write(sc, IG4_REG_INTR_MASK, status);
739	}
740	}
741
742	wakeup(sc);
743	mtx_unlock(&sc->io_lock);	1137	mtx_unlock(&sc->io_lock);
744	}	1138	}
745		1139
Lines 773-782 ig4iic_dump(ig4iic_softc_t *sc) Link Here
773	REGDUMP(sc, IG4_REG_DMA_RDLR);	1167	REGDUMP(sc, IG4_REG_DMA_RDLR);
774	REGDUMP(sc, IG4_REG_SDA_SETUP);	1168	REGDUMP(sc, IG4_REG_SDA_SETUP);
775	REGDUMP(sc, IG4_REG_ENABLE_STATUS);	1169	REGDUMP(sc, IG4_REG_ENABLE_STATUS);
776	if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {	1170	REGDUMP(sc, IG4_REG_COMP_PARAM1);
777	REGDUMP(sc, IG4_REG_COMP_PARAM1);	1171	REGDUMP(sc, IG4_REG_COMP_VER);
778	REGDUMP(sc, IG4_REG_COMP_VER);
779	}
780	if (sc->version == IG4_ATOM) {	1172	if (sc->version == IG4_ATOM) {
781	REGDUMP(sc, IG4_REG_COMP_TYPE);	1173	REGDUMP(sc, IG4_REG_COMP_TYPE);
782	REGDUMP(sc, IG4_REG_CLK_PARMS);	1174	REGDUMP(sc, IG4_REG_CLK_PARMS);
Lines 790-801 ig4iic_dump(ig4iic_softc_t *sc) Link Here
790	if (sc->version == IG4_HASWELL) {	1182	if (sc->version == IG4_HASWELL) {
791	REGDUMP(sc, IG4_REG_SW_LTR_VALUE);	1183	REGDUMP(sc, IG4_REG_SW_LTR_VALUE);
792	REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);	1184	REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);
793	} else if (sc->version == IG4_SKYLAKE) {	1185	} else if (IG4_HAS_ADDREGS(sc->version)) {
794	REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE);	1186	REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE);
795	REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE);	1187	REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE);
796	}	1188	}
797	}	1189	}
798	#undef REGDUMP	1190	#undef REGDUMP
799		1191
800	DRIVER_MODULE(iicbus, ig4iic_acpi, iicbus_driver, iicbus_devclass, NULL, NULL);	1192	DRIVER_MODULE(iicbus, ig4iic, iicbus_driver, iicbus_devclass, NULL, NULL);
801	DRIVER_MODULE(iicbus, ig4iic_pci, iicbus_driver, iicbus_devclass, NULL, NULL);

Lines 90-95 static int ig4iic_pci_detach(device_t dev); Link Here

(-)b/sys/dev/ichiic/ig4_pci.c (-8 / +58 lines)
90	#define PCI_CHIP_APL_I2C_5 0x5ab68086	90	#define PCI_CHIP_APL_I2C_5 0x5ab68086
91	#define PCI_CHIP_APL_I2C_6 0x5ab88086	91	#define PCI_CHIP_APL_I2C_6 0x5ab88086
92	#define PCI_CHIP_APL_I2C_7 0x5aba8086	92	#define PCI_CHIP_APL_I2C_7 0x5aba8086
		93	#define PCI_CHIP_CANNONLAKE_LP_I2C_0 0x9dc58086
		94	#define PCI_CHIP_CANNONLAKE_LP_I2C_1 0x9dc68086
		95	#define PCI_CHIP_CANNONLAKE_LP_I2C_2 0x9de88086
		96	#define PCI_CHIP_CANNONLAKE_LP_I2C_3 0x9de98086
		97	#define PCI_CHIP_CANNONLAKE_LP_I2C_4 0x9dea8086
		98	#define PCI_CHIP_CANNONLAKE_LP_I2C_5 0x9deb8086
		99	#define PCI_CHIP_CANNONLAKE_H_I2C_0 0xa3688086
		100	#define PCI_CHIP_CANNONLAKE_H_I2C_1 0xa3698086
		101	#define PCI_CHIP_CANNONLAKE_H_I2C_2 0xa36a8086
		102	#define PCI_CHIP_CANNONLAKE_H_I2C_3 0xa36b8086
93		103
94	struct ig4iic_pci_device {	104	struct ig4iic_pci_device {
95	uint32_t devid;	105	uint32_t devid;
Lines 121-127 static struct ig4iic_pci_device ig4iic_pci_devices[] = { Link Here
121	{ PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL},	131	{ PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL},
122	{ PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL},	132	{ PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL},
123	{ PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL},	133	{ PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL},
124	{ PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL}	134	{ PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL},
		135	{ PCI_CHIP_CANNONLAKE_LP_I2C_0, "Intel Cannon Lake-LP I2C Controller-0", IG4_CANNONLAKE},
		136	{ PCI_CHIP_CANNONLAKE_LP_I2C_1, "Intel Cannon Lake-LP I2C Controller-1", IG4_CANNONLAKE},
		137	{ PCI_CHIP_CANNONLAKE_LP_I2C_2, "Intel Cannon Lake-LP I2C Controller-2", IG4_CANNONLAKE},
		138	{ PCI_CHIP_CANNONLAKE_LP_I2C_3, "Intel Cannon Lake-LP I2C Controller-3", IG4_CANNONLAKE},
		139	{ PCI_CHIP_CANNONLAKE_LP_I2C_4, "Intel Cannon Lake-LP I2C Controller-4", IG4_CANNONLAKE},
		140	{ PCI_CHIP_CANNONLAKE_LP_I2C_5, "Intel Cannon Lake-LP I2C Controller-5", IG4_CANNONLAKE},
		141	{ PCI_CHIP_CANNONLAKE_H_I2C_0, "Intel Cannon Lake-H I2C Controller-0", IG4_CANNONLAKE},
		142	{ PCI_CHIP_CANNONLAKE_H_I2C_1, "Intel Cannon Lake-H I2C Controller-1", IG4_CANNONLAKE},
		143	{ PCI_CHIP_CANNONLAKE_H_I2C_2, "Intel Cannon Lake-H I2C Controller-2", IG4_CANNONLAKE},
		144	{ PCI_CHIP_CANNONLAKE_H_I2C_3, "Intel Cannon Lake-H I2C Controller-3", IG4_CANNONLAKE},
125	};	145	};
126		146
127	static int	147	static int
Lines 206-236 ig4iic_pci_detach(device_t dev) Link Here
206	return (0);	226	return (0);
207	}	227	}
208		228
		229	static int
		230	ig4iic_pci_suspend(device_t dev)
		231	{
		232	ig4iic_softc_t *sc = device_get_softc(dev);
		233
		234	return (ig4iic_suspend(sc));
		235	}
		236
		237	static int
		238	ig4iic_pci_resume(device_t dev)
		239	{
		240	ig4iic_softc_t *sc = device_get_softc(dev);
		241
		242	return (ig4iic_resume(sc));
		243	}
		244
209	static device_method_t ig4iic_pci_methods[] = {	245	static device_method_t ig4iic_pci_methods[] = {
210	/* Device interface */	246	/* Device interface */
211	DEVMETHOD(device_probe, ig4iic_pci_probe),	247	DEVMETHOD(device_probe, ig4iic_pci_probe),
212	DEVMETHOD(device_attach, ig4iic_pci_attach),	248	DEVMETHOD(device_attach, ig4iic_pci_attach),
213	DEVMETHOD(device_detach, ig4iic_pci_detach),	249	DEVMETHOD(device_detach, ig4iic_pci_detach),
		250	DEVMETHOD(device_suspend, ig4iic_pci_suspend),
		251	DEVMETHOD(device_resume, ig4iic_pci_resume),
		252
		253	/* Bus interface */
		254	DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
		255	DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
		256	DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
		257	DEVMETHOD(bus_release_resource, bus_generic_release_resource),
		258	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
		259	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
		260	DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
		261	DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
		262	DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
214		263
		264	/* iicbus interface */
215	DEVMETHOD(iicbus_transfer, ig4iic_transfer),	265	DEVMETHOD(iicbus_transfer, ig4iic_transfer),
216	DEVMETHOD(iicbus_reset, ig4iic_reset),	266	DEVMETHOD(iicbus_reset, ig4iic_reset),
217	DEVMETHOD(iicbus_callback, iicbus_null_callback),	267	DEVMETHOD(iicbus_callback, ig4iic_callback),
218		268
219	DEVMETHOD_END	269	DEVMETHOD_END
220	};	270	};
221		271
222	static driver_t ig4iic_pci_driver = {	272	static driver_t ig4iic_pci_driver = {
223	"ig4iic_pci",	273	"ig4iic",
224	ig4iic_pci_methods,	274	ig4iic_pci_methods,
225	sizeof(struct ig4iic_softc)	275	sizeof(struct ig4iic_softc)
226	};	276	};
227		277
228	static devclass_t ig4iic_pci_devclass;	278	static devclass_t ig4iic_pci_devclass;
229		279
230	DRIVER_MODULE_ORDERED(ig4iic_pci, pci, ig4iic_pci_driver, ig4iic_pci_devclass, 0, 0,	280	DRIVER_MODULE_ORDERED(ig4iic, pci, ig4iic_pci_driver, ig4iic_pci_devclass, 0, 0,
231	SI_ORDER_ANY);	281	SI_ORDER_ANY);
232	MODULE_DEPEND(ig4iic_pci, pci, 1, 1, 1);	282	MODULE_DEPEND(ig4iic, pci, 1, 1, 1);
233	MODULE_DEPEND(ig4iic_pci, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);	283	MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);
234	MODULE_VERSION(ig4iic_pci, 1);	284	MODULE_VERSION(ig4iic, 1);
235	MODULE_PNP_INFO("W32:vendor/device", pci, ig4iic_pci, ig4iic_pci_devices,	285	MODULE_PNP_INFO("W32:vendor/device", pci, ig4iic, ig4iic_pci_devices,
236	nitems(ig4iic_pci_devices));	286	nitems(ig4iic_pci_devices));




#define IG4_REG_SDA_SETUP	0x0094	/* RW	SDA Setup */
#define IG4_REG_ACK_GENERAL_CALL 0x0098	/* RW	I2C ACK General Call */
#define IG4_REG_ENABLE_STATUS	0x009C	/* RO	Enable Status */
/* Available at least on Atom SoCs, Haswell mobile and some Skylakes. */
#define IG4_REG_COMP_PARAM1	0x00F4	/* RO	Component Parameter */
#define IG4_REG_COMP_VER	0x00F8	/* RO	Component Version */
/* Available at least on Atom SoCs */
#define IG4_REG_COMP_TYPE	0x00FC	/* RO	Probe width/endian? (linux) */
/* 0x200-0x2FF - Additional registers available on Skylake-U/Y and others */
#define IG4_REG_RESETS_SKL	0x0204	/* RW	Reset Register */
#define IG4_REG_ACTIVE_LTR_VALUE 0x0210	/* RW	Active LTR Value */
#define IG4_REG_IDLE_LTR_VALUE	0x0214	/* RW	Idle LTR Value */

#define IG4_CTL_SLAVE_DISABLE	0x0040	/* snarfed from linux */
#define IG4_CTL_RESTARTEN	0x0020	/* Allow Restart when master */
#define IG4_CTL_10BIT		0x0010	/* ctlr accepts 10-bit addresses */
#define IG4_CTL_SPEED_MASK	0x0006	/* speed at which the I2C operates */
#define IG4_CTL_MASTER		0x0001	/* snarfed from linux */

#define IG4_CTL_SPEED_HIGH	0x0006	/* snarfed from linux */
#define IG4_CTL_SPEED_FAST	0x0004	/* snarfed from linux */
#define IG4_CTL_SPEED_STD	0x0002	/* snarfed from linux */
#define IG4_CTL_MASTER		0x0001	/* snarfed from linux */

/*
 * TAR_ADD - Target Address Register	22.2.2

#define IG4_INTR_RX_OVER	0x0002
#define IG4_INTR_RX_UNDER	0x0001

#define IG4_INTR_ERR_MASK	(IG4_INTR_TX_ABRT | IG4_INTR_TX_OVER | \
				 IG4_INTR_RX_OVER | IG4_INTR_RX_UNDER)

/*
 * RX_TL	- (RW) Receive FIFO Threshold Register		22.2.11
 * TX_TL	- (RW) Transmit FIFO Threshold Register		22.2.12

 * I2C_EN	- (RW) I2C Enable Register			22.2.22
 *
 *	ABORT		Software can abort an I2C transfer by setting this
 *			bit. In response, the controller issues the STOP
 *			condition over the I2C bus, followed by TX FIFO flush.
 *			Hardware will clear the bit once the STOP has
 *			been detected.  This bit can only be set while the
 *			I2C interface is enabled.
 *

 *	FIFOs.  Note that for some reason the mask is 9 bits instead of
 *	the 8 bits the fill level controls.
 */
#define IG4_FIFOLVL_MASK	0x01FF

/*
 * SDA_HOLD	- (RW) SDA Hold Time Length Register		22.2.26
 *
 *	Set the SDA hold time length register in I2C clocks.
 */
#define IG4_SDA_TX_HOLD_MASK	0x0000FFFF

/*
 * TX_ABRT_SOURCE- (RO) Transmit Abort Source Register		22.2.27

#define IG4_ABRTSRC_NORESTART_10	0x00000400 /* RESTART disabled */
#define IG4_ABRTSRC_NORESTART_START	0x00000200 /* RESTART disabled */
#define IG4_ABRTSRC_ACKED_START		0x00000080 /* Improper acked START */
#define IG4_ABRTSRC_GENCALL_READ	0x00000020 /* Improper GENCALL */
#define IG4_ABRTSRC_GENCALL_NOACK	0x00000010 /* Nobody acked GENCALL */
#define IG4_ABRTSRC_TXNOACK_DATA	0x00000008 /* data phase no ACK */
#define IG4_ABRTSRC_TXNOACK_ADDR10_2	0x00000004 /* addr10/1 phase no ACK */
#define IG4_ABRTSRC_TXNOACK_ADDR10_1	0x00000002 /* addr10/2 phase no ACK */

 *
 *	DATAW		- Indicates the internal bus width in bits.
 */
#define IG4_PARAM1_TXFIFO_DEPTH(v)	((((v) >> 16) & 0xFF) + 1)
#define IG4_PARAM1_RXFIFO_DEPTH(v)	((((v) >> 8) & 0xFF) + 1)
#define IG4_PARAM1_CONFIG_VALID		0x00000080
#define IG4_PARAM1_CONFIG_HASDMA	0x00000040
#define IG4_PARAM1_CONFIG_INTR_IO	0x00000020

Lines 43-57 Link Here

(-)b/sys/dev/ichiic/ig4_var.h (-26 / +26 lines)
43	#include "pci_if.h"	43	#include "pci_if.h"
44	#include "iicbus_if.h"	44	#include "iicbus_if.h"
45		45
46	#define IG4_RBUFSIZE 128	46	enum ig4_vers { IG4_HASWELL, IG4_ATOM, IG4_SKYLAKE, IG4_APL, IG4_CANNONLAKE };
47	#define IG4_RBUFMASK (IG4_RBUFSIZE - 1)	47	/* Controller has additional registers */
		48	#define IG4_HAS_ADDREGS(vers) ((vers) == IG4_SKYLAKE \|\| \
		49	(vers) == IG4_APL \|\| (vers) == IG4_CANNONLAKE)
48		50
49	enum ig4_op { IG4_IDLE, IG4_READ, IG4_WRITE };	51	struct ig4_cfg {
50	enum ig4_vers { IG4_HASWELL, IG4_ATOM, IG4_SKYLAKE, IG4_APL };	52	uint32_t version;
		53	uint32_t bus_speed;
		54	uint16_t ss_scl_hcnt;
		55	uint16_t ss_scl_lcnt;
		56	uint16_t fs_scl_hcnt;
		57	uint16_t fs_scl_lcnt;
		58	uint16_t sda_tx_hold;
		59	int txfifo_depth;
		60	int rxfifo_depth;
		61	};
51		62
52	struct ig4iic_softc {	63	struct ig4iic_softc {
53	device_t dev;	64	device_t dev;
54	struct intr_config_hook enum_hook;
55	device_t iicbus;	65	device_t iicbus;
56	struct resource *regs_res;	66	struct resource *regs_res;
57	int regs_rid;	67	int regs_rid;
Lines 60-99 struct ig4iic_softc { Link Here
60	void *intr_handle;	70	void *intr_handle;
61	int intr_type;	71	int intr_type;
62	enum ig4_vers version;	72	enum ig4_vers version;
63	enum ig4_op op;	73	struct ig4_cfg cfg;
64	int cmd;	74	int cmd;
65	int rnext;	75	uint32_t intr_mask;
66	int rpos;
67	char rbuf[IG4_RBUFSIZE];
68	int error;	76	int error;
69	uint8_t last_slave;	77	uint8_t last_slave;
70	int platform_attached : 1;	78	int platform_attached : 1;
71	int use_10bit : 1;	79	int use_10bit : 1;
72	int slave_valid : 1;	80	int slave_valid : 1;
73	int read_started : 1;	81	int poll: 1;
74	int write_started : 1;
75	int access_intr_mask : 1;
76		82
77	/*	83	/*
78	* Locking semantics:	84	* Locking semantics:
79	*	85	*
80	* Functions implementing the icbus interface that interact	86	* Functions implementing the icbus interface that interact
81	* with the controller acquire an exclusive lock on call_lock	87	* with the controller acquire an exclusive lock on call_lock
82	* to prevent interleaving of calls to the interface and a lock on	88	* to prevent interleaving of calls to the interface.
83	* io_lock right afterwards, to synchronize controller I/O activity.
84	*
85	* The interrupt handler can only read data while no iicbus call
86	* is in progress or while io_lock is dropped during mtx_sleep in
87	* wait_status and set_controller. It is safe to drop io_lock in those
88	* places, because the interrupt handler only accesses those registers:
89	*
90	* - IG4_REG_I2C_STA (I2C Status)
91	* - IG4_REG_DATA_CMD (Data Buffer and Command)
92	* - IG4_REG_CLR_INTR (Clear Interrupt)
93	*	89	*
94	* Locking outside of those places is required to make the content	90	* io_lock is used as condition variable to synchronize active process
95	* of rpos/rnext predictable (e.g. whenever data_read is called and in	91	* with the interrupt handler. It should not be used for tasks other
96	* ig4iic_transfer).	92	* than waiting for interrupt and passing parameters to and from
		93	* it's handler.
97	*/	94	*/
98	struct sx call_lock;	95	struct sx call_lock;
99	struct mtx io_lock;	96	struct mtx io_lock;
Lines 104-112 typedef struct ig4iic_softc ig4iic_softc_t; Link Here
104	/* Attach/Detach called from ig4iic_pci_() /	101	/* Attach/Detach called from ig4iic_pci_() /
105	int ig4iic_attach(ig4iic_softc_t *sc);	102	int ig4iic_attach(ig4iic_softc_t *sc);
106	int ig4iic_detach(ig4iic_softc_t *sc);	103	int ig4iic_detach(ig4iic_softc_t *sc);
		104	int ig4iic_suspend(ig4iic_softc_t *sc);
		105	int ig4iic_resume(ig4iic_softc_t *sc);
107		106
108	/* iicbus methods */	107	/* iicbus methods */
109	extern iicbus_transfer_t ig4iic_transfer;	108	extern iicbus_transfer_t ig4iic_transfer;
110	extern iicbus_reset_t ig4iic_reset;	109	extern iicbus_reset_t ig4iic_reset;
		110	extern iicbus_callback_t ig4iic_callback;
111		111
112	#endif /* _ICHIIC_IG4_VAR_H_ */	112	#endif /* _ICHIIC_IG4_VAR_H_ */

Lines 330-335 static device_method_t iicbus_methods[] = { Link Here

(-)b/sys/dev/iicbus/iicbus.c (+2 lines)
330	DEVMETHOD(device_probe, iicbus_probe),	330	DEVMETHOD(device_probe, iicbus_probe),
331	DEVMETHOD(device_attach, iicbus_attach),	331	DEVMETHOD(device_attach, iicbus_attach),
332	DEVMETHOD(device_detach, iicbus_detach),	332	DEVMETHOD(device_detach, iicbus_detach),
		333	DEVMETHOD(device_suspend, bus_generic_suspend),
		334	DEVMETHOD(device_resume, bus_generic_resume),
333		335
334	/* bus interface */	336	/* bus interface */
335	DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),	337	DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),

Return to bug 240485

Lines 69-86 static int Link Here

(-)b/sys/dev/ichiic/ig4_acpi.c (-11 / +37 lines)
69	ig4iic_acpi_probe(device_t dev)	69	ig4iic_acpi_probe(device_t dev)
70	{	70	{
71	ig4iic_softc_t *sc;	71	ig4iic_softc_t *sc;
72	char *hid;
73	int rv;	72	int rv;
74		73
75	sc = device_get_softc(dev);	74	sc = device_get_softc(dev);
76	if (acpi_disabled("ig4iic"))	75	if (acpi_disabled("ig4iic"))
77	return (ENXIO);	76	return (ENXIO);
78	rv = ACPI_ID_PROBE(device_get_parent(dev), dev, ig4iic_ids, &hid);	77	rv = ACPI_ID_PROBE(device_get_parent(dev), dev, ig4iic_ids, NULL);
79	if (rv > 0)	78	if (rv > 0)
80	return (rv);	79	return (rv);
81		80
82	if (strcmp("AMDI0010", hid) == 0)
83	sc->access_intr_mask = 1;
84	device_set_desc(dev, "Designware I2C Controller");	81	device_set_desc(dev, "Designware I2C Controller");
85	return (rv);	82	return (rv);
86	}	83	}
Lines 148-177 ig4iic_acpi_detach(device_t dev) Link Here
148	return (0);	145	return (0);
149	}	146	}
150		147
		148	static int
		149	ig4iic_acpi_suspend(device_t dev)
		150	{
		151	ig4iic_softc_t *sc = device_get_softc(dev);
		152
		153	return (ig4iic_suspend(sc));
		154	}
		155
		156	static int
		157	ig4iic_acpi_resume(device_t dev)
		158	{
		159	ig4iic_softc_t *sc = device_get_softc(dev);
		160
		161	return (ig4iic_resume(sc));
		162	}
		163
151	static device_method_t ig4iic_acpi_methods[] = {	164	static device_method_t ig4iic_acpi_methods[] = {
152	/* Device interface */	165	/* Device interface */
153	DEVMETHOD(device_probe, ig4iic_acpi_probe),	166	DEVMETHOD(device_probe, ig4iic_acpi_probe),
154	DEVMETHOD(device_attach, ig4iic_acpi_attach),	167	DEVMETHOD(device_attach, ig4iic_acpi_attach),
155	DEVMETHOD(device_detach, ig4iic_acpi_detach),	168	DEVMETHOD(device_detach, ig4iic_acpi_detach),
		169	DEVMETHOD(device_suspend, ig4iic_acpi_suspend),
		170	DEVMETHOD(device_resume, ig4iic_acpi_resume),
		171
		172	/* Bus interface */
		173	DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
		174	DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
		175	DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
		176	DEVMETHOD(bus_release_resource, bus_generic_release_resource),
		177	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
		178	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
		179	DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
		180	DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
		181	DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
156		182
157	/* iicbus interface */	183	/* iicbus interface */
158	DEVMETHOD(iicbus_transfer, ig4iic_transfer),	184	DEVMETHOD(iicbus_transfer, ig4iic_transfer),
159	DEVMETHOD(iicbus_reset, ig4iic_reset),	185	DEVMETHOD(iicbus_reset, ig4iic_reset),
160	DEVMETHOD(iicbus_callback, iicbus_null_callback),	186	DEVMETHOD(iicbus_callback, ig4iic_callback),
161		187
162	DEVMETHOD_END	188	DEVMETHOD_END
163	};	189	};
164		190
165	static driver_t ig4iic_acpi_driver = {	191	static driver_t ig4iic_acpi_driver = {
166	"ig4iic_acpi",	192	"ig4iic",
167	ig4iic_acpi_methods,	193	ig4iic_acpi_methods,
168	sizeof(struct ig4iic_softc),	194	sizeof(struct ig4iic_softc),
169	};	195	};
170		196
171	static devclass_t ig4iic_acpi_devclass;	197	static devclass_t ig4iic_acpi_devclass;
172	DRIVER_MODULE(ig4iic_acpi, acpi, ig4iic_acpi_driver, ig4iic_acpi_devclass, 0, 0);	198	DRIVER_MODULE(ig4iic, acpi, ig4iic_acpi_driver, ig4iic_acpi_devclass, 0, 0);
173		199
174	MODULE_DEPEND(ig4iic_acpi, acpi, 1, 1, 1);	200	MODULE_DEPEND(ig4iic, acpi, 1, 1, 1);
175	MODULE_DEPEND(ig4iic_acpi, pci, 1, 1, 1);	201	MODULE_DEPEND(ig4iic, pci, 1, 1, 1);
176	MODULE_DEPEND(ig4iic_acpi, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);	202	MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);
177	MODULE_VERSION(ig4iic_acpi, 1);	203	MODULE_VERSION(ig4iic, 1);

Lines 112-123 Link Here

(-)b/sys/dev/ichiic/ig4_reg.h (-10 / +18 lines)
112	#define IG4_REG_SDA_SETUP 0x0094 /* RW SDA Setup */	112	#define IG4_REG_SDA_SETUP 0x0094 /* RW SDA Setup */
113	#define IG4_REG_ACK_GENERAL_CALL 0x0098 /* RW I2C ACK General Call */	113	#define IG4_REG_ACK_GENERAL_CALL 0x0098 /* RW I2C ACK General Call */
114	#define IG4_REG_ENABLE_STATUS 0x009C /* RO Enable Status */	114	#define IG4_REG_ENABLE_STATUS 0x009C /* RO Enable Status */
115	/* Available at least on Atom SoCs and Haswell mobile. */	115	/* Available at least on Atom SoCs, Haswell mobile and some Skylakes. */
116	#define IG4_REG_COMP_PARAM1 0x00F4 /* RO Component Parameter */	116	#define IG4_REG_COMP_PARAM1 0x00F4 /* RO Component Parameter */
117	#define IG4_REG_COMP_VER 0x00F8 /* RO Component Version */	117	#define IG4_REG_COMP_VER 0x00F8 /* RO Component Version */
118	/* Available at least on Atom SoCs */	118	/* Available at least on Atom SoCs */
119	#define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */	119	#define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */
120	/* Available on Skylake-U/Y and Kaby Lake-U/Y */	120	/* 0x200-0x2FF - Additional registers available on Skylake-U/Y and others */
121	#define IG4_REG_RESETS_SKL 0x0204 /* RW Reset Register */	121	#define IG4_REG_RESETS_SKL 0x0204 /* RW Reset Register */
122	#define IG4_REG_ACTIVE_LTR_VALUE 0x0210 /* RW Active LTR Value */	122	#define IG4_REG_ACTIVE_LTR_VALUE 0x0210 /* RW Active LTR Value */
123	#define IG4_REG_IDLE_LTR_VALUE 0x0214 /* RW Idle LTR Value */	123	#define IG4_REG_IDLE_LTR_VALUE 0x0214 /* RW Idle LTR Value */
Lines 154-162 Link Here
154	#define IG4_CTL_SLAVE_DISABLE 0x0040 /* snarfed from linux */	154	#define IG4_CTL_SLAVE_DISABLE 0x0040 /* snarfed from linux */
155	#define IG4_CTL_RESTARTEN 0x0020 /* Allow Restart when master */	155	#define IG4_CTL_RESTARTEN 0x0020 /* Allow Restart when master */
156	#define IG4_CTL_10BIT 0x0010 /* ctlr accepts 10-bit addresses */	156	#define IG4_CTL_10BIT 0x0010 /* ctlr accepts 10-bit addresses */
		157	#define IG4_CTL_SPEED_MASK 0x0006 /* speed at which the I2C operates */
		158	#define IG4_CTL_MASTER 0x0001 /* snarfed from linux */
		159
		160	#define IG4_CTL_SPEED_HIGH 0x0006 /* snarfed from linux */
157	#define IG4_CTL_SPEED_FAST 0x0004 /* snarfed from linux */	161	#define IG4_CTL_SPEED_FAST 0x0004 /* snarfed from linux */
158	#define IG4_CTL_SPEED_STD 0x0002 /* snarfed from linux */	162	#define IG4_CTL_SPEED_STD 0x0002 /* snarfed from linux */
159	#define IG4_CTL_MASTER 0x0001 /* snarfed from linux */
160		163
161	/*	164	/*
162	* TAR_ADD - Target Address Register 22.2.2	165	* TAR_ADD - Target Address Register 22.2.2
Lines 325-330 Link Here
325	#define IG4_INTR_RX_OVER 0x0002	328	#define IG4_INTR_RX_OVER 0x0002
326	#define IG4_INTR_RX_UNDER 0x0001	329	#define IG4_INTR_RX_UNDER 0x0001
327		330
		331	#define IG4_INTR_ERR_MASK (IG4_INTR_TX_ABRT \| IG4_INTR_TX_OVER \| \
		332	IG4_INTR_RX_OVER \| IG4_INTR_RX_UNDER)
		333
328	/*	334	/*
329	* RX_TL - (RW) Receive FIFO Threshold Register 22.2.11	335	* RX_TL - (RW) Receive FIFO Threshold Register 22.2.11
330	* TX_TL - (RW) Transmit FIFO Threshold Register 22.2.12	336	* TX_TL - (RW) Transmit FIFO Threshold Register 22.2.12
Lines 377-383 Link Here
377	* I2C_EN - (RW) I2C Enable Register 22.2.22	383	* I2C_EN - (RW) I2C Enable Register 22.2.22
378	*	384	*
379	* ABORT Software can abort an I2C transfer by setting this	385	* ABORT Software can abort an I2C transfer by setting this
380	* bit. Hardware will clear the bit once the STOP has	386	* bit. In response, the controller issues the STOP
		387	* condition over the I2C bus, followed by TX FIFO flush.
		388	* Hardware will clear the bit once the STOP has
381	* been detected. This bit can only be set while the	389	* been detected. This bit can only be set while the
382	* I2C interface is enabled.	390	* I2C interface is enabled.
383	*	391	*
Lines 406-419 Link Here
406	* FIFOs. Note that for some reason the mask is 9 bits instead of	414	* FIFOs. Note that for some reason the mask is 9 bits instead of
407	* the 8 bits the fill level controls.	415	* the 8 bits the fill level controls.
408	*/	416	*/
409	#define IG4_FIFOLVL_MASK 0x001F	417	#define IG4_FIFOLVL_MASK 0x01FF
410		418
411	/*	419	/*
412	* SDA_HOLD - (RW) SDA Hold Time Length Register 22.2.26	420	* SDA_HOLD - (RW) SDA Hold Time Length Register 22.2.26
413	*	421	*
414	* Set the SDA hold time length register in I2C clocks.	422	* Set the SDA hold time length register in I2C clocks.
415	*/	423	*/
416	#define IG4_SDA_HOLD_MASK 0x00FF	424	#define IG4_SDA_TX_HOLD_MASK 0x0000FFFF
417		425
418	/*	426	/*
419	* TX_ABRT_SOURCE- (RO) Transmit Abort Source Register 22.2.27	427	* TX_ABRT_SOURCE- (RO) Transmit Abort Source Register 22.2.27
Lines 432-439 Link Here
432	#define IG4_ABRTSRC_NORESTART_10 0x00000400 /* RESTART disabled */	440	#define IG4_ABRTSRC_NORESTART_10 0x00000400 /* RESTART disabled */
433	#define IG4_ABRTSRC_NORESTART_START 0x00000200 /* RESTART disabled */	441	#define IG4_ABRTSRC_NORESTART_START 0x00000200 /* RESTART disabled */
434	#define IG4_ABRTSRC_ACKED_START 0x00000080 /* Improper acked START */	442	#define IG4_ABRTSRC_ACKED_START 0x00000080 /* Improper acked START */
435	#define IG4_ABRTSRC_GENCALL_NOACK 0x00000020 /* Improper GENCALL */	443	#define IG4_ABRTSRC_GENCALL_READ 0x00000020 /* Improper GENCALL */
436	#define IG4_ABRTSRC_GENCALL_READ 0x00000010 /* Nobody acked GENCALL */	444	#define IG4_ABRTSRC_GENCALL_NOACK 0x00000010 /* Nobody acked GENCALL */
437	#define IG4_ABRTSRC_TXNOACK_DATA 0x00000008 /* data phase no ACK */	445	#define IG4_ABRTSRC_TXNOACK_DATA 0x00000008 /* data phase no ACK */
438	#define IG4_ABRTSRC_TXNOACK_ADDR10_2 0x00000004 /* addr10/1 phase no ACK */	446	#define IG4_ABRTSRC_TXNOACK_ADDR10_2 0x00000004 /* addr10/1 phase no ACK */
439	#define IG4_ABRTSRC_TXNOACK_ADDR10_1 0x00000002 /* addr10/2 phase no ACK */	447	#define IG4_ABRTSRC_TXNOACK_ADDR10_1 0x00000002 /* addr10/2 phase no ACK */
Lines 530-537 Link Here
530	*	538	*
531	* DATAW - Indicates the internal bus width in bits.	539	* DATAW - Indicates the internal bus width in bits.
532	*/	540	*/
533	#define IG4_PARAM1_TXFIFO_DEPTH(v) (((v) >> 16) & 0xFF)	541	#define IG4_PARAM1_TXFIFO_DEPTH(v) ((((v) >> 16) & 0xFF) + 1)
534	#define IG4_PARAM1_RXFIFO_DEPTH(v) (((v) >> 8) & 0xFF)	542	#define IG4_PARAM1_RXFIFO_DEPTH(v) ((((v) >> 8) & 0xFF) + 1)
535	#define IG4_PARAM1_CONFIG_VALID 0x00000080	543	#define IG4_PARAM1_CONFIG_VALID 0x00000080
536	#define IG4_PARAM1_CONFIG_HASDMA 0x00000040	544	#define IG4_PARAM1_CONFIG_HASDMA 0x00000040
537	#define IG4_PARAM1_CONFIG_INTR_IO 0x00000020	545	#define IG4_PARAM1_CONFIG_INTR_IO 0x00000020