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(-)www/chromium/files/patch-third__party_boringssl_src_crypto_cpu-aarch64-linux.c (-11 / +22 lines)
Lines 1-6 Link Here
1
--- third_party/boringssl/src/crypto/cpu-aarch64-linux.c.orig	2019-04-30 22:25:51 UTC
1
--- third_party/boringssl/src/crypto/cpu-aarch64-linux.c.orig	2019-04-30 22:25:51 UTC
2
+++ third_party/boringssl/src/crypto/cpu-aarch64-linux.c
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+++ third_party/boringssl/src/crypto/cpu-aarch64-linux.c
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@@ -14,49 +14,35 @@
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@@ -14,49 +14,46 @@
4
 
4
 
5
 #include <openssl/cpu.h>
5
 #include <openssl/cpu.h>
6
 
6
 
Lines 17-28 Link Here
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-
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-
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 extern uint32_t OPENSSL_armcap_P;
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 extern uint32_t OPENSSL_armcap_P;
19
 
19
 
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-void OPENSSL_cpuid_setup(void) {
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-  unsigned long hwcap = getauxval(AT_HWCAP);
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+#include <sys/types.h>
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+#include <sys/types.h>
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+#include <stdint.h>
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+#include <machine/armreg.h>
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+#include <machine/armreg.h>
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+
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 void OPENSSL_cpuid_setup(void) {
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-  unsigned long hwcap = getauxval(AT_HWCAP);
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+  uint64_t id_aa64isar0;
26
 
25
 
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-  // See /usr/include/asm/hwcap.h on an aarch64 installation for the source of
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-  // See /usr/include/asm/hwcap.h on an aarch64 installation for the source of
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-  // these values.
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-  // these values.
Lines 31-37 Link Here
31
-  static const unsigned long kPMULL = 1 << 4;
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-  static const unsigned long kPMULL = 1 << 4;
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-  static const unsigned long kSHA1 = 1 << 5;
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-  static const unsigned long kSHA1 = 1 << 5;
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-  static const unsigned long kSHA256 = 1 << 6;
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-  static const unsigned long kSHA256 = 1 << 6;
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+  id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
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+#ifndef ID_AA64ISAR0_AES_VAL
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+#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
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+#endif
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+#ifndef ID_AA64ISAR0_SHA1_VAL
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+#define ID_AA64ISAR0_SHA1_VAL ID_AA64ISAR0_SHA1
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+#endif
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+#ifndef ID_AA64ISAR0_SHA2_VAL
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+#define ID_AA64ISAR0_SHA2_VAL ID_AA64ISAR0_SHA2
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+#endif
35
 
42
 
36
-  if ((hwcap & kNEON) == 0) {
43
-  if ((hwcap & kNEON) == 0) {
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-    // Matching OpenSSL, if NEON is missing, don't report other features
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-    // Matching OpenSSL, if NEON is missing, don't report other features
Lines 38-60 Link Here
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-    // either.
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-    // either.
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-    return;
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-    return;
40
-  }
47
-  }
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-
48
+void OPENSSL_cpuid_setup(void) {
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+  uint64_t id_aa64isar0;
50
 
51
+  id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
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+
42
   OPENSSL_armcap_P |= ARMV7_NEON;
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   OPENSSL_armcap_P |= ARMV7_NEON;
43
 
54
 
44
-  if (hwcap & kAES) {
55
-  if (hwcap & kAES) {
45
+  if (ID_AA64ISAR0_AES(id_aa64isar0) >= ID_AA64ISAR0_AES_BASE) {
56
+  if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) >= ID_AA64ISAR0_AES_BASE) {
46
     OPENSSL_armcap_P |= ARMV8_AES;
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     OPENSSL_armcap_P |= ARMV8_AES;
47
   }
58
   }
48
-  if (hwcap & kPMULL) {
59
-  if (hwcap & kPMULL) {
49
+  if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) {
60
+  if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) {
50
     OPENSSL_armcap_P |= ARMV8_PMULL;
61
     OPENSSL_armcap_P |= ARMV8_PMULL;
51
   }
62
   }
52
-  if (hwcap & kSHA1) {
63
-  if (hwcap & kSHA1) {
53
+  if (ID_AA64ISAR0_SHA1(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE) {
64
+  if (ID_AA64ISAR0_SHA1_VAL(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE) {
54
     OPENSSL_armcap_P |= ARMV8_SHA1;
65
     OPENSSL_armcap_P |= ARMV8_SHA1;
55
   }
66
   }
56
-  if (hwcap & kSHA256) {
67
-  if (hwcap & kSHA256) {
57
+  if(ID_AA64ISAR0_SHA2(id_aa64isar0) >= ID_AA64ISAR0_SHA2_BASE) {
68
+  if(ID_AA64ISAR0_SHA2_VAL(id_aa64isar0) >= ID_AA64ISAR0_SHA2_BASE) {
58
     OPENSSL_armcap_P |= ARMV8_SHA256;
69
     OPENSSL_armcap_P |= ARMV8_SHA256;
59
   }
70
   }
60
 }
71
 }
(-)www/chromium/files/patch-third__party_crc32c_src_src_crc32c__arm64__linux__check.h (-6 / +14 lines)
Lines 9-15 Link Here
9
 #include <cstddef>
9
 #include <cstddef>
10
 #include <cstdint>
10
 #include <cstdint>
11
 
11
 
12
@@ -16,30 +14,19 @@
12
@@ -16,30 +14,29 @@
13
 
13
 
14
 #if HAVE_ARM64_CRC32C
14
 #if HAVE_ARM64_CRC32C
15
 
15
 
Lines 19-30 Link Here
19
-// getauxval() is not available on Android until API level 20. Link it as a weak
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-// getauxval() is not available on Android until API level 20. Link it as a weak
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-// symbol.
20
-// symbol.
21
-extern "C" unsigned long getauxval(unsigned long type) __attribute__((weak));
21
-extern "C" unsigned long getauxval(unsigned long type) __attribute__((weak));
22
-
22
 
23
-#define AT_HWCAP 16
23
-#define AT_HWCAP 16
24
-#endif  // HAVE_STRONG_GETAUXVAL || HAVE_WEAK_GETAUXVAL
24
-#endif  // HAVE_STRONG_GETAUXVAL || HAVE_WEAK_GETAUXVAL
25
-
25
+#include <stdint.h>
26
+#include <machine/armreg.h>
26
+#include <machine/armreg.h>
27
+#include <sys/types.h>
27
+#include <sys/types.h>
28
 
29
+#ifndef ID_AA64ISAR0_AES_VAL
30
+#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
31
+#endif
32
+#ifndef ID_AA64ISAR0_CRC32_VAL
33
+#define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
34
+#endif
35
+
28
 namespace crc32c {
36
 namespace crc32c {
29
 
37
 
30
-inline bool CanUseArm64Linux() {
38
-inline bool CanUseArm64Linux() {
Lines 42-50 Link Here
42
+  inline bool CanUseArm64Linux() {
50
+  inline bool CanUseArm64Linux() {
43
+    uint64_t id_aa64isar0;
51
+    uint64_t id_aa64isar0;
44
+  
52
+  
45
+    id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
53
+    id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
46
+    if ((ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) && \
54
+    if ((ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) && \
47
+       (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE))
55
+       (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE))
48
+      return true;
56
+      return true;
49
+    return false;
57
+    return false;
50
+  }
58
+  }
(-)www/chromium/files/patch-third__party_zlib_arm__features.c (-6 / +13 lines)
Lines 1-17 Link Here
1
--- third_party/zlib/arm_features.c.orig	2019-06-04 18:55:48 UTC
1
--- third_party/zlib/arm_features.c.orig	2019-06-04 18:55:48 UTC
2
+++ third_party/zlib/arm_features.c
2
+++ third_party/zlib/arm_features.c
3
@@ -16,6 +16,10 @@ int ZLIB_INTERNAL arm_cpu_enable_pmull = 0;
3
@@ -16,6 +16,17 @@ int ZLIB_INTERNAL arm_cpu_enable_pmull = 0;
4
 #include <pthread.h>
4
 #include <pthread.h>
5
 #endif
5
 #endif
6
 
6
 
7
+#if defined(__FreeBSD__)
7
+#if defined(__FreeBSD__)
8
+#include <stdint.h>
8
+#include <machine/armreg.h>
9
+#include <machine/armreg.h>
9
+#include <sys/types.h>
10
+#include <sys/types.h>
11
+#ifndef ID_AA64ISAR0_AES_VAL
12
+#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
13
+#endif
14
+#ifndef ID_AA64ISAR0_CRC32_VAL
15
+#define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
16
+#endif
10
+#else
17
+#else
11
 #if defined(ARMV8_OS_ANDROID)
18
 #if defined(ARMV8_OS_ANDROID)
12
 #include <cpu-features.h>
19
 #include <cpu-features.h>
13
 #elif defined(ARMV8_OS_LINUX)
20
 #elif defined(ARMV8_OS_LINUX)
14
@@ -30,6 +34,7 @@ int ZLIB_INTERNAL arm_cpu_enable_pmull = 0;
21
@@ -30,6 +41,7 @@ int ZLIB_INTERNAL arm_cpu_enable_pmull = 0;
15
 #else
22
 #else
16
 #error arm_features.c ARM feature detection in not defined for your platform
23
 #error arm_features.c ARM feature detection in not defined for your platform
17
 #endif
24
 #endif
Lines 19-33 Link Here
19
 
26
 
20
 static void _arm_check_features(void);
27
 static void _arm_check_features(void);
21
 
28
 
22
@@ -68,14 +73,24 @@ static void _arm_check_features(void)
29
@@ -68,14 +80,24 @@ static void _arm_check_features(void)
23
     arm_cpu_enable_crc32 = !!(features & ANDROID_CPU_ARM_FEATURE_CRC32);
30
     arm_cpu_enable_crc32 = !!(features & ANDROID_CPU_ARM_FEATURE_CRC32);
24
     arm_cpu_enable_pmull = !!(features & ANDROID_CPU_ARM_FEATURE_PMULL);
31
     arm_cpu_enable_pmull = !!(features & ANDROID_CPU_ARM_FEATURE_PMULL);
25
 #elif defined(ARMV8_OS_LINUX) && defined(__aarch64__)
32
 #elif defined(ARMV8_OS_LINUX) && defined(__aarch64__)
26
+#if defined(__FreeBSD__)
33
+#if defined(__FreeBSD__)
27
+    uint64_t id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
34
+    uint64_t id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
28
+    if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL)
35
+    if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL)
29
+        arm_cpu_enable_pmull = 1;
36
+        arm_cpu_enable_pmull = 1;
30
+    if (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE)
37
+    if (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE)
31
+        arm_cpu_enable_crc32 = 1;
38
+        arm_cpu_enable_crc32 = 1;
32
+#else
39
+#else
33
     unsigned long features = getauxval(AT_HWCAP);
40
     unsigned long features = getauxval(AT_HWCAP);

Return to bug 242105