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(-)emulators/qemu-user-static-devel/files/patch-1 (+58 lines)
Line 0 Link Here
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https://lists.gnu.org/archive/html/qemu-arm/2019-01/msg00474.html
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XXX mik enable read from qemu-user-mode
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Although technically not visible to userspace the kernel does make
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them visible via a trap and emulate ABI. We provide a new permission
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mask (PL0U_R) which maps to PL0_R for CONFIG_USER builds and adjust
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the minimum permission check accordingly.
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Signed-off-by: Alex Bennée <address@hidden>
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---
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 target/arm/cpu.h    | 12 ++++++++++++
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 target/arm/helper.c |  6 +++++-
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 2 files changed, 17 insertions(+), 1 deletion(-)
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diff --git a/target/arm/cpu.h b/target/arm/cpu.h
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index ff81db420d..3b3c359cca 100644
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--- target/arm/cpu.h
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+++ target/arm/cpu.h
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@@ -2202,6 +2202,18 @@ static inline bool cptype_valid(int cptype)
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 #define PL0_R (0x02 | PL1_R)
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 #define PL0_W (0x01 | PL1_W)
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+/*
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+ * For user-mode some registers are accessible to EL0 via a kernel
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+ * trap-and-emulate ABI. In this case we define the read permissions
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+ * as actually being PL0_R. However some bits of any given register
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+ * may still be masked.
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+ */
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+//#ifdef CONFIG_USER_ONLY
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+#define PL0U_R PL0_R
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+//#else
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+//#define PL0U_R PL1_R
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+//#endif
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+
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 #define PL3_RW (PL3_R | PL3_W)
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 #define PL2_RW (PL2_R | PL2_W)
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 #define PL1_RW (PL1_R | PL1_W)
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diff --git a/target/arm/helper.c b/target/arm/helper.c
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index 92666e5208..42c1c0b144 100644
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--- target/arm/helper.c
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+++ target/arm/helper.c
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@@ -6731,7 +6731,11 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
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     if (r->state != ARM_CP_STATE_AA32) {
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         int mask = 0;
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         switch (r->opc1) {
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-        case 0: case 1: case 2:
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+        case 0:
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+            /* min_EL EL1, but some accessible to EL0 via kernel ABI */
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+            mask = PL0U_R | PL1_RW;
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+            break;
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+        case 1: case 2:
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             /* min_EL EL1 */
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             mask = PL1_RW;
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             break;
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-- 
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2.17.1
(-)emulators/qemu-user-static-devel/files/patch-2 (+151 lines)
Line 0 Link Here
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https://lists.gnu.org/archive/html/qemu-arm/2019-01/msg00476.html
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3
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A number of CPUID registers are exposed to userspace by modern Linux
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kernels thanks to the "ARM64 CPU Feature Registers" ABI. For QEMU's
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user-mode emulation we don't need to emulate the kernels trap but just
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return the value the trap would have done. For this we use the PL0U_R
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permission mask which allows this access in CONFIG_USER mode.
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Some registers only return a subset of their contents so we need
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specific CONFIG_USER_ONLY logic to do this.
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Signed-off-by: Alex Bennée <address@hidden>
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---
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v4
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  - tweak commit message
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  - use PL0U_R instead of PL1U_R to be less confusing
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  - more CONFIG_USER logic for special cases
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  - mask a bunch of bits for some registers
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---
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 target/arm/helper.c | 51 ++++++++++++++++++++++++++++++++-------------
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 1 file changed, 36 insertions(+), 15 deletions(-)
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--- target/arm/helper.c.orig	2020-01-15 10:57:32.205310000 +0100
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+++ target/arm/helper.c	2020-01-15 11:09:33.857765000 +0100
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@@ -3047,7 +3047,7 @@ static uint64_t mpidr_read(CPUARMState *env, const ARM
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 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
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     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
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       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
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-      .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
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+      .access = PL0U_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
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     REGINFO_SENTINEL
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 };
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@@ -4945,6 +4945,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const A
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     return pfr1;
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 }
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+#ifndef CONFIG_USER_ONLY
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 static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
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 {
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     ARMCPU *cpu = arm_env_get_cpu(env);
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@@ -4955,6 +4956,7 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, con
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     }
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     return pfr0;
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 }
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+#endif
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 void register_cp_regs_for_features(ARMCPU *cpu)
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 {
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@@ -5102,18 +5104,26 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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          * define new registers here.
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          */
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         ARMCPRegInfo v8_idregs[] = {
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-            /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
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-             * know the right value for the GIC field until after we
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-             * define these regs.
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+            /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST for system
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+             * emulation because we don't know the right value for the
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+             * GIC field until after we define these regs. For
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+             * user-mode HWCAP_CPUID emulation the GIC bits are masked
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+             * anyway.
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              */
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             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
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               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
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+#ifndef CONFIG_USER_ONLY
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               .access = PL1_R, .type = ARM_CP_NO_RAW,
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               .readfn = id_aa64pfr0_read,
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-              .writefn = arm_cp_write_ignore },
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+              .writefn = arm_cp_write_ignore
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+#else
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+              .access = PL0U_R, .type = ARM_CP_CONST,
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+              .resetvalue = cpu->isar.id_aa64pfr0 & 0x000f000f0ff0000ULL
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+#endif
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+            },
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             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
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               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
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-              .access = PL1_R, .type = ARM_CP_CONST,
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+              .access = PL0U_R, .type = ARM_CP_CONST,
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               .resetvalue = cpu->isar.id_aa64pfr1},
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             { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
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               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
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@@ -5142,7 +5152,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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               .resetvalue = 0 },
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             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
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               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
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-              .access = PL1_R, .type = ARM_CP_CONST,
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+              .access = PL0U_R, .type = ARM_CP_CONST,
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               .resetvalue = cpu->id_aa64dfr0 },
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             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
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               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
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@@ -5174,11 +5184,16 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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               .resetvalue = 0 },
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             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
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               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
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-              .access = PL1_R, .type = ARM_CP_CONST,
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-              .resetvalue = cpu->isar.id_aa64isar0 },
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+              .access = PL0U_R, .type = ARM_CP_CONST,
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+#ifdef CONFIG_USER_ONLY
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+              .resetvalue = cpu->isar.id_aa64isar0 & 0x000fffffff0ffff0ULL
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+#else
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+              .resetvalue = cpu->isar.id_aa64isar0
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+#endif
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+            },
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             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
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               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
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-              .access = PL1_R, .type = ARM_CP_CONST,
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+              .access = PL0U_R, .type = ARM_CP_CONST,
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               .resetvalue = cpu->isar.id_aa64isar1 },
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             { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
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               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
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@@ -5206,11 +5221,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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               .resetvalue = 0 },
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             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
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               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
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-              .access = PL1_R, .type = ARM_CP_CONST,
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+              .access = PL0U_R, .type = ARM_CP_CONST,
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               .resetvalue = cpu->id_aa64mmfr0 },
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             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
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               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
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-              .access = PL1_R, .type = ARM_CP_CONST,
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+              .access = PL0U_R, .type = ARM_CP_CONST,
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               .resetvalue = cpu->id_aa64mmfr1 },
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             { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
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               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
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@@ -5510,7 +5525,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
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             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
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               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
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-              .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
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+              .access = PL0U_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
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               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
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               .readfn = midr_read },
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             /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
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@@ -5522,7 +5537,13 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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               .access = PL1_R, .resetvalue = cpu->midr },
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             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
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               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
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-              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
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+#ifdef CONFIG_USER_ONLY
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+              .access = PL0U_R, .type = ARM_CP_CONST,
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+              .resetvalue = 0 /* HW_CPUID IMPDEF fields are 0 */ },
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+#else
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+              .access = PL1_R, .type = ARM_CP_CONST,
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+              .resetvalue = cpu->revidr },
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+#endif
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             REGINFO_SENTINEL
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         };
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         ARMCPRegInfo id_cp_reginfo[] = {

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