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(-)www/chromium/files/patch-third__party_boringssl_src_crypto_cpu-aarch64-linux.c (-13 / +22 lines)
Lines 1-6 Link Here
1
--- third_party/boringssl/src/crypto/cpu-aarch64-linux.c.orig	2019-04-30 22:25:51 UTC
1
--- third_party/boringssl/src/crypto/cpu-aarch64-linux.c.orig	2020-01-16 22:52:21 UTC
2
+++ third_party/boringssl/src/crypto/cpu-aarch64-linux.c
2
+++ third_party/boringssl/src/crypto/cpu-aarch64-linux.c
3
@@ -14,49 +14,35 @@
3
@@ -14,49 +14,44 @@
4
 
4
 
5
 #include <openssl/cpu.h>
5
 #include <openssl/cpu.h>
6
 
6
 
Lines 17-28 Link Here
17
-
17
-
18
 extern uint32_t OPENSSL_armcap_P;
18
 extern uint32_t OPENSSL_armcap_P;
19
 
19
 
20
+#include <sys/types.h>
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-void OPENSSL_cpuid_setup(void) {
21
-  unsigned long hwcap = getauxval(AT_HWCAP);
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+#include <machine/armreg.h>
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+#include <machine/armreg.h>
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+
23
 void OPENSSL_cpuid_setup(void) {
24
-  unsigned long hwcap = getauxval(AT_HWCAP);
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+  uint64_t id_aa64isar0;
26
 
23
 
27
-  // See /usr/include/asm/hwcap.h on an aarch64 installation for the source of
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-  // See /usr/include/asm/hwcap.h on an aarch64 installation for the source of
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-  // these values.
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-  // these values.
Lines 31-37 Link Here
31
-  static const unsigned long kPMULL = 1 << 4;
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-  static const unsigned long kPMULL = 1 << 4;
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-  static const unsigned long kSHA1 = 1 << 5;
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-  static const unsigned long kSHA1 = 1 << 5;
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-  static const unsigned long kSHA256 = 1 << 6;
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-  static const unsigned long kSHA256 = 1 << 6;
34
+  id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
31
+#ifndef ID_AA64ISAR0_AES_VAL
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+#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
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+#endif
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+#ifndef ID_AA64ISAR0_SHA1_VAL
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+#define ID_AA64ISAR0_SHA1_VAL ID_AA64ISAR0_SHA1
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+#endif
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+#ifndef ID_AA64ISAR0_SHA2_VAL
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+#define ID_AA64ISAR0_SHA2_VAL ID_AA64ISAR0_SHA2
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+#endif
35
 
40
 
36
-  if ((hwcap & kNEON) == 0) {
41
-  if ((hwcap & kNEON) == 0) {
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-    // Matching OpenSSL, if NEON is missing, don't report other features
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-    // Matching OpenSSL, if NEON is missing, don't report other features
Lines 38-60 Link Here
38
-    // either.
43
-    // either.
39
-    return;
44
-    return;
40
-  }
45
-  }
41
-
46
+void OPENSSL_cpuid_setup(void) {
47
+  uint64_t id_aa64isar0;
48
 
49
+  id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
50
+
42
   OPENSSL_armcap_P |= ARMV7_NEON;
51
   OPENSSL_armcap_P |= ARMV7_NEON;
43
 
52
 
44
-  if (hwcap & kAES) {
53
-  if (hwcap & kAES) {
45
+  if (ID_AA64ISAR0_AES(id_aa64isar0) >= ID_AA64ISAR0_AES_BASE) {
54
+  if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) >= ID_AA64ISAR0_AES_BASE) {
46
     OPENSSL_armcap_P |= ARMV8_AES;
55
     OPENSSL_armcap_P |= ARMV8_AES;
47
   }
56
   }
48
-  if (hwcap & kPMULL) {
57
-  if (hwcap & kPMULL) {
49
+  if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) {
58
+  if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) {
50
     OPENSSL_armcap_P |= ARMV8_PMULL;
59
     OPENSSL_armcap_P |= ARMV8_PMULL;
51
   }
60
   }
52
-  if (hwcap & kSHA1) {
61
-  if (hwcap & kSHA1) {
53
+  if (ID_AA64ISAR0_SHA1(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE) {
62
+  if (ID_AA64ISAR0_SHA1_VAL(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE) {
54
     OPENSSL_armcap_P |= ARMV8_SHA1;
63
     OPENSSL_armcap_P |= ARMV8_SHA1;
55
   }
64
   }
56
-  if (hwcap & kSHA256) {
65
-  if (hwcap & kSHA256) {
57
+  if(ID_AA64ISAR0_SHA2(id_aa64isar0) >= ID_AA64ISAR0_SHA2_BASE) {
66
+  if(ID_AA64ISAR0_SHA2_VAL(id_aa64isar0) >= ID_AA64ISAR0_SHA2_BASE) {
58
     OPENSSL_armcap_P |= ARMV8_SHA256;
67
     OPENSSL_armcap_P |= ARMV8_SHA256;
59
   }
68
   }
60
 }
69
 }
(-)www/chromium/files/patch-third__party_crc32c_src_src_crc32c__arm64__linux__check.h (-9 / +14 lines)
Lines 1-4 Link Here
1
--- third_party/crc32c/src/src/crc32c_arm64_linux_check.h.orig	2019-04-30 22:25:51 UTC
1
--- third_party/crc32c/src/src/crc32c_arm64_linux_check.h.orig	2020-01-16 22:52:22 UTC
2
+++ third_party/crc32c/src/src/crc32c_arm64_linux_check.h
2
+++ third_party/crc32c/src/src/crc32c_arm64_linux_check.h
3
@@ -7,8 +7,6 @@
3
@@ -7,8 +7,6 @@
4
 #ifndef CRC32C_CRC32C_ARM_LINUX_CHECK_H_
4
 #ifndef CRC32C_CRC32C_ARM_LINUX_CHECK_H_
Lines 9-15 Link Here
9
 #include <cstddef>
9
 #include <cstddef>
10
 #include <cstdint>
10
 #include <cstdint>
11
 
11
 
12
@@ -16,30 +14,19 @@
12
@@ -16,30 +14,26 @@
13
 
13
 
14
 #if HAVE_ARM64_CRC32C
14
 #if HAVE_ARM64_CRC32C
15
 
15
 
Lines 19-30 Link Here
19
-// getauxval() is not available on Android until API level 20. Link it as a weak
19
-// getauxval() is not available on Android until API level 20. Link it as a weak
20
-// symbol.
20
-// symbol.
21
-extern "C" unsigned long getauxval(unsigned long type) __attribute__((weak));
21
-extern "C" unsigned long getauxval(unsigned long type) __attribute__((weak));
22
-
22
+#include <machine/armreg.h>
23
 
23
-#define AT_HWCAP 16
24
-#define AT_HWCAP 16
24
-#endif  // HAVE_STRONG_GETAUXVAL || HAVE_WEAK_GETAUXVAL
25
-#endif  // HAVE_STRONG_GETAUXVAL || HAVE_WEAK_GETAUXVAL
25
-
26
+#ifndef ID_AA64ISAR0_AES_VAL
26
+#include <machine/armreg.h>
27
+#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
27
+#include <sys/types.h>
28
+#endif
29
+#ifndef ID_AA64ISAR0_CRC32_VAL
30
+#define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
31
+#endif
32
 
28
 namespace crc32c {
33
 namespace crc32c {
29
 
34
 
30
-inline bool CanUseArm64Linux() {
35
-inline bool CanUseArm64Linux() {
Lines 42-50 Link Here
42
+  inline bool CanUseArm64Linux() {
47
+  inline bool CanUseArm64Linux() {
43
+    uint64_t id_aa64isar0;
48
+    uint64_t id_aa64isar0;
44
+  
49
+  
45
+    id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
50
+    id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
46
+    if ((ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) && \
51
+    if ((ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) && \
47
+       (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE))
52
+       (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE))
48
+      return true;
53
+      return true;
49
+    return false;
54
+    return false;
50
+  }
55
+  }
(-)www/chromium/files/patch-third__party_zlib_arm__features.c (-8 / +13 lines)
Lines 1-17 Link Here
1
--- third_party/zlib/arm_features.c.orig	2019-06-04 18:55:48 UTC
1
--- third_party/zlib/arm_features.c.orig	2020-01-16 22:51:11 UTC
2
+++ third_party/zlib/arm_features.c
2
+++ third_party/zlib/arm_features.c
3
@@ -16,6 +16,10 @@ int ZLIB_INTERNAL arm_cpu_enable_pmull = 0;
3
@@ -16,6 +16,15 @@ int ZLIB_INTERNAL arm_cpu_enable_pmull = 0;
4
 #include <pthread.h>
4
 #include <pthread.h>
5
 #endif
5
 #endif
6
 
6
 
7
+#if defined(__FreeBSD__)
7
+#if defined(__FreeBSD__)
8
+#include <machine/armreg.h>
8
+#include <machine/armreg.h>
9
+#include <sys/types.h>
9
+#ifndef ID_AA64ISAR0_AES_VAL
10
+#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
11
+#endif
12
+#ifndef ID_AA64ISAR0_CRC32_VAL
13
+#define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
14
+#endif
10
+#else
15
+#else
11
 #if defined(ARMV8_OS_ANDROID)
16
 #if defined(ARMV8_OS_ANDROID)
12
 #include <cpu-features.h>
17
 #include <cpu-features.h>
13
 #elif defined(ARMV8_OS_LINUX)
18
 #elif defined(ARMV8_OS_LINUX)
14
@@ -30,6 +34,7 @@ int ZLIB_INTERNAL arm_cpu_enable_pmull = 0;
19
@@ -30,6 +39,7 @@ int ZLIB_INTERNAL arm_cpu_enable_pmull = 0;
15
 #else
20
 #else
16
 #error arm_features.c ARM feature detection in not defined for your platform
21
 #error arm_features.c ARM feature detection in not defined for your platform
17
 #endif
22
 #endif
Lines 19-33 Link Here
19
 
24
 
20
 static void _arm_check_features(void);
25
 static void _arm_check_features(void);
21
 
26
 
22
@@ -68,14 +73,24 @@ static void _arm_check_features(void)
27
@@ -68,14 +78,24 @@ static void _arm_check_features(void)
23
     arm_cpu_enable_crc32 = !!(features & ANDROID_CPU_ARM_FEATURE_CRC32);
28
     arm_cpu_enable_crc32 = !!(features & ANDROID_CPU_ARM_FEATURE_CRC32);
24
     arm_cpu_enable_pmull = !!(features & ANDROID_CPU_ARM_FEATURE_PMULL);
29
     arm_cpu_enable_pmull = !!(features & ANDROID_CPU_ARM_FEATURE_PMULL);
25
 #elif defined(ARMV8_OS_LINUX) && defined(__aarch64__)
30
 #elif defined(ARMV8_OS_LINUX) && defined(__aarch64__)
26
+#if defined(__FreeBSD__)
31
+#if defined(__FreeBSD__)
27
+    uint64_t id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
32
+    uint64_t id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
28
+    if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL)
33
+    if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL)
29
+        arm_cpu_enable_pmull = 1;
34
+        arm_cpu_enable_pmull = 1;
30
+    if (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE)
35
+    if (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE)
31
+        arm_cpu_enable_crc32 = 1;
36
+        arm_cpu_enable_crc32 = 1;
32
+#else
37
+#else
33
     unsigned long features = getauxval(AT_HWCAP);
38
     unsigned long features = getauxval(AT_HWCAP);

Return to bug 242105