Attachment 211107 Details for Bug 242105 – patch

[patch] patch

www_chromium.diff (text/plain), 6.76 KB, created by Mikael Urankar on 2020-01-27 16:14:38 UTC

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Creator: Mikael Urankar

Created: 2020-01-27 16:14:38 UTC

Size: 6.76 KB

patch

obsolete

>Index: www/chromium/files/patch-third__party_boringssl_src_crypto_cpu-aarch64-linux.c
>===================================================================
>--- www/chromium/files/patch-third__party_boringssl_src_crypto_cpu-aarch64-linux.c	(revision 523938)
>+++ www/chromium/files/patch-third__party_boringssl_src_crypto_cpu-aarch64-linux.c	(working copy)
>@@ -1,6 +1,6 @@
>---- third_party/boringssl/src/crypto/cpu-aarch64-linux.c.orig	2019-04-30 22:25:51 UTC
>+--- third_party/boringssl/src/crypto/cpu-aarch64-linux.c.orig	2020-01-16 22:52:21 UTC
> +++ third_party/boringssl/src/crypto/cpu-aarch64-linux.c
>-@@ -14,49 +14,35 @@
>+@@ -14,49 +14,44 @@
>  
>  #include <openssl/cpu.h>
>  
>@@ -17,12 +17,9 @@
> -
>  extern uint32_t OPENSSL_armcap_P;
>  
>-+#include <sys/types.h>
>+-void OPENSSL_cpuid_setup(void) {
>+-  unsigned long hwcap = getauxval(AT_HWCAP);
> +#include <machine/armreg.h>
>-+
>- void OPENSSL_cpuid_setup(void) {
>--  unsigned long hwcap = getauxval(AT_HWCAP);
>-+  uint64_t id_aa64isar0;
>  
> -  // See /usr/include/asm/hwcap.h on an aarch64 installation for the source of
> -  // these values.
>@@ -31,7 +28,15 @@
> -  static const unsigned long kPMULL = 1 << 4;
> -  static const unsigned long kSHA1 = 1 << 5;
> -  static const unsigned long kSHA256 = 1 << 6;
>-+  id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
>++#ifndef ID_AA64ISAR0_AES_VAL
>++#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
>++#endif
>++#ifndef ID_AA64ISAR0_SHA1_VAL
>++#define ID_AA64ISAR0_SHA1_VAL ID_AA64ISAR0_SHA1
>++#endif
>++#ifndef ID_AA64ISAR0_SHA2_VAL
>++#define ID_AA64ISAR0_SHA2_VAL ID_AA64ISAR0_SHA2
>++#endif
>  
> -  if ((hwcap & kNEON) == 0) {
> -    // Matching OpenSSL, if NEON is missing, don't report other features
>@@ -38,23 +43,27 @@
> -    // either.
> -    return;
> -  }
>--
>++void OPENSSL_cpuid_setup(void) {
>++  uint64_t id_aa64isar0;
>+ 
>++  id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
>++
>    OPENSSL_armcap_P |= ARMV7_NEON;
>  
> -  if (hwcap & kAES) {
>-+  if (ID_AA64ISAR0_AES(id_aa64isar0) >= ID_AA64ISAR0_AES_BASE) {
>++  if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) >= ID_AA64ISAR0_AES_BASE) {
>      OPENSSL_armcap_P |= ARMV8_AES;
>    }
> -  if (hwcap & kPMULL) {
>-+  if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) {
>++  if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) {
>      OPENSSL_armcap_P |= ARMV8_PMULL;
>    }
> -  if (hwcap & kSHA1) {
>-+  if (ID_AA64ISAR0_SHA1(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE) {
>++  if (ID_AA64ISAR0_SHA1_VAL(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE) {
>      OPENSSL_armcap_P |= ARMV8_SHA1;
>    }
> -  if (hwcap & kSHA256) {
>-+  if(ID_AA64ISAR0_SHA2(id_aa64isar0) >= ID_AA64ISAR0_SHA2_BASE) {
>++  if(ID_AA64ISAR0_SHA2_VAL(id_aa64isar0) >= ID_AA64ISAR0_SHA2_BASE) {
>      OPENSSL_armcap_P |= ARMV8_SHA256;
>    }
>  }
>Index: www/chromium/files/patch-third__party_crc32c_src_src_crc32c__arm64__linux__check.h
>===================================================================
>--- www/chromium/files/patch-third__party_crc32c_src_src_crc32c__arm64__linux__check.h	(revision 523938)
>+++ www/chromium/files/patch-third__party_crc32c_src_src_crc32c__arm64__linux__check.h	(working copy)
>@@ -1,4 +1,4 @@
>---- third_party/crc32c/src/src/crc32c_arm64_linux_check.h.orig	2019-04-30 22:25:51 UTC
>+--- third_party/crc32c/src/src/crc32c_arm64_linux_check.h.orig	2020-01-16 22:52:22 UTC
> +++ third_party/crc32c/src/src/crc32c_arm64_linux_check.h
> @@ -7,8 +7,6 @@
>  #ifndef CRC32C_CRC32C_ARM_LINUX_CHECK_H_
>@@ -9,7 +9,7 @@
>  #include <cstddef>
>  #include <cstdint>
>  
>-@@ -16,30 +14,19 @@
>+@@ -16,30 +14,26 @@
>  
>  #if HAVE_ARM64_CRC32C
>  
>@@ -19,12 +19,17 @@
> -// getauxval() is not available on Android until API level 20. Link it as a weak
> -// symbol.
> -extern "C" unsigned long getauxval(unsigned long type) __attribute__((weak));
>--
>++#include <machine/armreg.h>
>+ 
> -#define AT_HWCAP 16
> -#endif  // HAVE_STRONG_GETAUXVAL || HAVE_WEAK_GETAUXVAL
>--
>-+#include <machine/armreg.h>
>-+#include <sys/types.h>
>++#ifndef ID_AA64ISAR0_AES_VAL
>++#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
>++#endif
>++#ifndef ID_AA64ISAR0_CRC32_VAL
>++#define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
>++#endif
>+ 
>  namespace crc32c {
>  
> -inline bool CanUseArm64Linux() {
>@@ -42,9 +47,9 @@
> +  inline bool CanUseArm64Linux() {
> +    uint64_t id_aa64isar0;
> +  
>-+    id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
>-+    if ((ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) && \
>-+       (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE))
>++    id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
>++    if ((ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) && \
>++       (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE))
> +      return true;
> +    return false;
> +  }
>Index: www/chromium/files/patch-third__party_zlib_arm__features.c
>===================================================================
>--- www/chromium/files/patch-third__party_zlib_arm__features.c	(revision 523938)
>+++ www/chromium/files/patch-third__party_zlib_arm__features.c	(working copy)
>@@ -1,17 +1,22 @@
>---- third_party/zlib/arm_features.c.orig	2019-06-04 18:55:48 UTC
>+--- third_party/zlib/arm_features.c.orig	2020-01-16 22:51:11 UTC
> +++ third_party/zlib/arm_features.c
>-@@ -16,6 +16,10 @@ int ZLIB_INTERNAL arm_cpu_enable_pmull = 0;
>+@@ -16,6 +16,15 @@ int ZLIB_INTERNAL arm_cpu_enable_pmull = 0;
>  #include <pthread.h>
>  #endif
>  
> +#if defined(__FreeBSD__)
> +#include <machine/armreg.h>
>-+#include <sys/types.h>
>++#ifndef ID_AA64ISAR0_AES_VAL
>++#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
>++#endif
>++#ifndef ID_AA64ISAR0_CRC32_VAL
>++#define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
>++#endif
> +#else
>  #if defined(ARMV8_OS_ANDROID)
>  #include <cpu-features.h>
>  #elif defined(ARMV8_OS_LINUX)
>-@@ -30,6 +34,7 @@ int ZLIB_INTERNAL arm_cpu_enable_pmull = 0;
>+@@ -30,6 +39,7 @@ int ZLIB_INTERNAL arm_cpu_enable_pmull = 0;
>  #else
>  #error arm_features.c ARM feature detection in not defined for your platform
>  #endif
>@@ -19,15 +24,15 @@
>  
>  static void _arm_check_features(void);
>  
>-@@ -68,14 +73,24 @@ static void _arm_check_features(void)
>+@@ -68,14 +78,24 @@ static void _arm_check_features(void)
>      arm_cpu_enable_crc32 = !!(features & ANDROID_CPU_ARM_FEATURE_CRC32);
>      arm_cpu_enable_pmull = !!(features & ANDROID_CPU_ARM_FEATURE_PMULL);
>  #elif defined(ARMV8_OS_LINUX) && defined(__aarch64__)
> +#if defined(__FreeBSD__)
>-+    uint64_t id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
>-+    if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL)
>++    uint64_t id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
>++    if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL)
> +        arm_cpu_enable_pmull = 1;
>-+    if (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE)
>++    if (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE)
> +        arm_cpu_enable_crc32 = 1;
> +#else
>      unsigned long features = getauxval(AT_HWCAP);

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Attachments on bug 242105: 209277 | 211107