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(-)sys/dev/bge/if_bge.c (-4 / +91 lines)
Lines 486-491 Link Here
486
static void bge_stop_fw(struct bge_softc *);
486
static void bge_stop_fw(struct bge_softc *);
487
static int bge_reset(struct bge_softc *);
487
static int bge_reset(struct bge_softc *);
488
static void bge_link_upd(struct bge_softc *);
488
static void bge_link_upd(struct bge_softc *);
489
static void bge_setwol(struct bge_softc *);
490
static void bge_clrwol(struct bge_softc *);
489
491
490
static void bge_ape_lock_init(struct bge_softc *);
492
static void bge_ape_lock_init(struct bge_softc *);
491
static void bge_ape_read_fw_ver(struct bge_softc *);
493
static void bge_ape_read_fw_ver(struct bge_softc *);
Lines 897-902 Link Here
897
static void
899
static void
898
bge_ape_driver_state_change(struct bge_softc *sc, int kind)
900
bge_ape_driver_state_change(struct bge_softc *sc, int kind)
899
{
901
{
902
	struct ifnet *ifp;
900
	uint32_t apedata, event;
903
	uint32_t apedata, event;
901
904
902
	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
905
	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
Lines 929-937 Link Here
929
		event = BGE_APE_EVENT_STATUS_STATE_START;
932
		event = BGE_APE_EVENT_STATUS_STATE_START;
930
		break;
933
		break;
931
	case BGE_RESET_SHUTDOWN:
934
	case BGE_RESET_SHUTDOWN:
932
		APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
935
                /* XXX  Needs rewording
933
		    BGE_APE_HOST_DRVR_STATE_UNLOAD);
936
                 * With the interface we are currently using,
934
		event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
937
                 * APE does not track driver state.  Wiping
938
                 * out the HOST SEGMENT SIGNATURE forces
939
                 * the APE to assume OS absent status.
940
                 */
941
		APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 0);
942
943
		ifp = sc->bge_ifp;
944
		if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
945
		    APE_WRITE_4(sc, BGE_APE_HOST_WOL_SPEED,
946
			BGE_APE_HOST_WOL_SPEED_AUTO);
947
		    APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
948
			BGE_FW_DRV_STATE_WOL);
949
		    event = BGE_APE_EVENT_STATUS_STATE_WOL;
950
		    bge_ifmedia_upd_locked(ifp);
951
		} else {
952
		    APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
953
			BGE_APE_HOST_DRVR_STATE_UNLOAD);
954
		    event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
955
		}
935
		break;
956
		break;
936
	case BGE_RESET_SUSPEND:
957
	case BGE_RESET_SUSPEND:
937
		event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
958
		event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
Lines 3737-3743 Link Here
3737
	if_setsendqready(ifp);
3758
	if_setsendqready(ifp);
3738
	if_sethwassist(ifp, sc->bge_csum_features);
3759
	if_sethwassist(ifp, sc->bge_csum_features);
3739
	if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3760
	if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3740
	    IFCAP_VLAN_MTU);
3761
	    IFCAP_VLAN_MTU | IFCAP_WOL_MAGIC);
3741
	if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3762
	if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3742
		if_sethwassistbits(ifp, CSUM_TSO, 0);
3763
		if_sethwassistbits(ifp, CSUM_TSO, 0);
3743
		if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0);
3764
		if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0);
Lines 3745-3750 Link Here
3745
#ifdef IFCAP_VLAN_HWCSUM
3766
#ifdef IFCAP_VLAN_HWCSUM
3746
	if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
3767
	if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
3747
#endif
3768
#endif
3769
	if (pci_find_cap(dev, PCIY_PMG, &reg) == 0)
3770
		if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0);
3748
	if_setcapenable(ifp, if_getcapabilities(ifp));
3771
	if_setcapenable(ifp, if_getcapabilities(ifp));
3749
#ifdef DEVICE_POLLING
3772
#ifdef DEVICE_POLLING
3750
	if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
3773
	if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
Lines 3930-3935 Link Here
3930
		device_printf(sc->bge_dev, "couldn't set up irq\n");
3953
		device_printf(sc->bge_dev, "couldn't set up irq\n");
3931
		goto fail;
3954
		goto fail;
3932
	}
3955
	}
3956
	BGE_LOCK(sc);
3957
	bge_clrwol(sc);
3958
	BGE_UNLOCK(sc);
3933
3959
3934
	/* Attach driver debugnet methods. */
3960
	/* Attach driver debugnet methods. */
3935
	DEBUGNET_SET(ifp, bge);
3961
	DEBUGNET_SET(ifp, bge);
Lines 5850-5855 Link Here
5850
			}
5876
			}
5851
		}
5877
		}
5852
#endif
5878
#endif
5879
		if ((mask & IFCAP_WOL_MAGIC) != 0 &&
5880
			(if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
5881
				if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
5853
		if ((mask & IFCAP_TXCSUM) != 0 &&
5882
		if ((mask & IFCAP_TXCSUM) != 0 &&
5854
		    (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
5883
		    (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
5855
			if_togglecapenable(ifp, IFCAP_TXCSUM);
5884
			if_togglecapenable(ifp, IFCAP_TXCSUM);
Lines 6077-6082 Link Here
6077
6106
6078
	sc = device_get_softc(dev);
6107
	sc = device_get_softc(dev);
6079
	BGE_LOCK(sc);
6108
	BGE_LOCK(sc);
6109
	bge_setwol(sc);
6080
	bge_stop(sc);
6110
	bge_stop(sc);
6081
	BGE_UNLOCK(sc);
6111
	BGE_UNLOCK(sc);
6082
6112
Lines 6090-6095 Link Here
6090
6120
6091
	sc = device_get_softc(dev);
6121
	sc = device_get_softc(dev);
6092
	BGE_LOCK(sc);
6122
	BGE_LOCK(sc);
6123
	bge_setwol(sc);
6093
	bge_stop(sc);
6124
	bge_stop(sc);
6094
	BGE_UNLOCK(sc);
6125
	BGE_UNLOCK(sc);
6095
6126
Lines 6105-6115 Link Here
6105
	sc = device_get_softc(dev);
6136
	sc = device_get_softc(dev);
6106
	BGE_LOCK(sc);
6137
	BGE_LOCK(sc);
6107
	ifp = sc->bge_ifp;
6138
	ifp = sc->bge_ifp;
6139
	bge_reset(sc);
6108
	if (if_getflags(ifp) & IFF_UP) {
6140
	if (if_getflags(ifp) & IFF_UP) {
6109
		bge_init_locked(sc);
6141
		bge_init_locked(sc);
6110
		if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6142
		if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6111
			bge_start_locked(ifp);
6143
			bge_start_locked(ifp);
6112
	}
6144
	}
6145
	bge_clrwol(sc);
6113
	BGE_UNLOCK(sc);
6146
	BGE_UNLOCK(sc);
6114
6147
6115
	return (0);
6148
	return (0);
Lines 6784-6789 Link Here
6784
	}
6817
	}
6785
}
6818
}
6786
6819
6820
static void
6821
bge_setwol(struct bge_softc *sc)
6822
{
6823
	struct ifnet *ifp;
6824
	uint16_t pmstat;
6825
	int pmc;
6826
6827
	ifp = sc->bge_ifp;
6828
	if ((if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) == 0)
6829
		return;
6830
	if (pci_find_cap(sc->bge_dev, PCIY_PMG, &pmc) != 0)
6831
		return;
6832
	if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
6833
		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_MAGIC_PKT_ENB);
6834
		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_ACPI_PWRON_ENB);
6835
		BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
6836
		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
6837
		BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
6838
	}
6839
	else {
6840
		BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_MAGIC_PKT_ENB);
6841
		BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_ACPI_PWRON_ENB);
6842
	}
6843
6844
	/* Request PME if WOL is requested. */
6845
	pmstat = pci_read_config(sc->bge_dev, pmc + PCIR_POWER_STATUS, 2);
6846
	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
6847
	if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
6848
		pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
6849
	pci_write_config(sc->bge_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
6850
}
6851
6852
static void
6853
bge_clrwol(struct bge_softc *sc)
6854
{
6855
	struct ifnet *ifp;
6856
	uint16_t pmstat;
6857
	int pmc;
6858
6859
	ifp = sc->bge_ifp;
6860
	if ((if_getcapabilities(ifp) & IFCAP_WOL) == 0)
6861
		return;
6862
	if (pci_find_cap(sc->bge_dev, PCIY_PMG, &pmc) != 0)
6863
		return;
6864
	if ((if_getcapenable(ifp) & IFCAP_WOL) == 0)
6865
		return;
6866
	BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_MAGIC_PKT_ENB);
6867
	BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_ACPI_PWRON_ENB);
6868
6869
	pmstat = pci_read_config(sc->bge_dev, pmc + PCIR_POWER_STATUS, 2);
6870
	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
6871
	pci_write_config(sc->bge_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
6872
}
6873
6787
#ifdef DEBUGNET
6874
#ifdef DEBUGNET
6788
static void
6875
static void
6789
bge_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6876
bge_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
(-)sys/dev/bge/if_bgereg.h (-1 / +2 lines)
Lines 459-465 Link Here
459
#define	BGE_PCICLOCKCTL_ALTCLK		0x00001000
459
#define	BGE_PCICLOCKCTL_ALTCLK		0x00001000
460
#define	BGE_PCICLOCKCTL_ALTCLK_SRC	0x00002000
460
#define	BGE_PCICLOCKCTL_ALTCLK_SRC	0x00002000
461
#define	BGE_PCICLOCKCTL_PCIPLL_DISABLE	0x00004000
461
#define	BGE_PCICLOCKCTL_PCIPLL_DISABLE	0x00004000
462
#define	BGE_PCICLOCKCTL_SYSPLL_DISABLE	0x00008000
462
#define	BGE_PCICLOCKCTL_SYSPLL_DISABLE	0x00008000 /* Disable the 133 MHz
463
						    * phase-locked loop */
463
#define	BGE_PCICLOCKCTL_BIST_ENABLE	0x00010000
464
#define	BGE_PCICLOCKCTL_BIST_ENABLE	0x00010000
464
465
465
466

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