Attachment #214840 for bug #204521




#define	RTSX_DMA_MAX_SEGSIZE	0x80000
#define	RTSX_HOSTCMD_MAX	256
#define	RTSX_HOSTCMD_BUFSIZE	(sizeof(uint32_t) * RTSX_HOSTCMD_MAX)
#define	RTSX_DMA_DATA_BUFSIZE	MAXPHYS
#define	RTSX_ADMA_DESC_SIZE	(sizeof(uint64_t) * SDMMC_MAXNSEGS)

#define RTSX_NREG ((0XFDAE - 0XFDA0) + (0xFD69 - 0xFD32) + (0xFE34 - 0xFE20))

		cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ?
			RTSX_MAX_DATA_BLKLEN : cmd->data->len;
				
    RTSX_CLR(sc,RTSX_SD_CFG1,RTSX_CLK_DIVIDE_MASK);
	if (bootverbose)
		device_printf(sc->rtsx_dev, "rtsx_xfer() - %s xfer: %ld bytes with block size %ld\n",
			      read ? "Read" : "Write",

	}

	/* Configure DMA transfer mode parameters. */
    cfg2 =   RTSX_SD_CHECK_CRC16 |
		RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0;
	if (read) {
		dma_dir = RTSX_DMA_DIR_FROM_CARD;

		 * sent the read command and gotten the response, and will
		 * send CMD 12 manually after reading multiple blocks.
		 */
        tmode = RTSX_TM_AUTO_READ1;
        if(cmd->opcode == 18) {
            cfg2 = 0x1; /*RTSX_SD_NO_CHECK_WAIT_CRC_TO|RTSX_SD_CHECK_CRC16 |*/
                //RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0;
            tmode = RTSX_TM_AUTO_READ1;
        }
		cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7;
	} else {
		dma_dir = RTSX_DMA_DIR_TO_CARD;

		 * sent the write command and gotten the response, and will
		 * send CMD 12 manually after writing multiple blocks.
		 */
        tmode = RTSX_TM_AUTO_WRITE1;
		cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7;
	}

    //sc->rtsx_cmd_index = 0;
    rtsx_init_cmd(sc,cmd);
    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L,
              0xff, ((cmd->data->len / cmd->data->xfer_len) & 0xff));
    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H,
              0xff, ((cmd->data->len / cmd->data->xfer_len) >> 8));
    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L,
              0xff, (cmd->data->xfer_len & 0xff));
    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H,
              0xff, (cmd->data->xfer_len >> 8));

    /* Configure DMA controller. */
    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0,
             RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT);
	/* Queue commands to configure data transfer size. */

    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC3,
             0xff, cmd->data->len >> 24);
    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC2,
             0xff, cmd->data->len >> 16);
    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC1,
             0xff, cmd->data->len >> 8);
    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC0,
             0xff, cmd->data->len);
    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMACTL,
             RTSX_DMA_EN | RTSX_DMA_DIR | RTSX_DMA_PACK_SIZE_MASK,
             RTSX_DMA_EN | dma_dir | RTSX_DMA_512);

	/* Use the DMA ring buffer for commands which transfer data. */
	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE,
		      0x01, RTSX_RING_BUFFER);
    /* Queue command to set response type. */
    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2,
             0xff, cfg2);


	/* Configure DMA controller. */
	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0,
		     RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT);
	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC3,
		     0xff, cmd->data->len >> 24);
	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC2,
		     0xff, cmd->data->len >> 16);
	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC1,
		     0xff, cmd->data->len >> 8);
	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC0,
		     0xff, cmd->data->len);
	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMACTL,
		     RTSX_DMA_EN | RTSX_DMA_DIR | RTSX_DMA_PACK_SIZE_MASK,
		     RTSX_DMA_EN | dma_dir | RTSX_DMA_512);

	/* Queue commands to perform SD transfer. */
	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER,


	/* Tell the chip where the data buffer is and run the transfer. */
	WRITE4(sc, RTSX_HDBAR, sc->rtsx_data_buffer);
    WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) |
           (cmd->data->len & 0x00ffffff));

	if ((error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz * sc->rtsx_timeout))) {
		cmd->error = MMC_ERR_TIMEOUT;


	/* Sync command DMA buffer. */
	bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTREAD);
    bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTWRITE);
    if(read)
        memcpy(cmd->data->data, sc->rtsx_data_dmamem, cmd->data->len);
    else
        memcpy(sc->rtsx_data_dmamem,cmd->data->data,cmd->data->len);

	memcpy(cmd->data->data, sc->rtsx_data_dmamem, cmd->data->len);
	
	return (error);
}


	case bus_width_1:
		bus_width = RTSX_BUS_WIDTH_1;
		break;
    case bus_width_4:
		bus_width = RTSX_BUS_WIDTH_4;
		break;
	case bus_width_8:

		break;
	case power_up:
		if (sc->rtsx_power_mode != power_up) {
            rtsx_bus_power_on(sc);
            sc->rtsx_power_mode = power_up;
		}
		break;
	case power_on:
		if (sc->rtsx_power_mode != power_on) {
            rtsx_bus_power_up(sc);
			sc->rtsx_power_mode = power_on;
		}
		break;
	};

    return (0);
}

/* Set output stage logic power voltage */

	if (bootverbose)
		device_printf(sc->rtsx_dev, "rtsx_mmcbr_switch_vccq(%d)\n", vccq);

	rtsx_bus_power_off(sc);

   //rtsx_bus_power_off(sc);

    //DELAY(200);
	
    //rtsx_bus_power_on(sc);
	sc->rtsx_power_mode = power_on;
		
	return (0);


	if (bootverbose)
		device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune()\n");
    sc->rtsx_host.ios.clock=RTSX_SDCLK_50MHZ;
	return (0);

}

	}

	if (cmd->data == NULL) {
        error = rtsx_send_req_get_resp(sc, cmd);
    } else if (cmd->data->len < 512) {
		error = rtsx_xfer_short(sc, cmd);
		if (error) {
			uint8_t stat1;

			}
		}
	} else {
        error = rtsx_xfer(sc, cmd);
		if (!error) {
			error = rtsx_xfer(sc, cmd);
			if (error) {
				uint8_t stat1;
				if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 &&

					cmd->error = MMC_ERR_BADCRC;
				}
			}
		}
	}

 done:

Return to bug 204521

Lines 216-222 static void rtsx_handle_card_present(struct rtsx_softc *sc); Link Here

(-)b/rtsx.c (-52 / +60 lines)
216	#define RTSX_DMA_MAX_SEGSIZE 0x80000	216	#define RTSX_DMA_MAX_SEGSIZE 0x80000
217	#define RTSX_HOSTCMD_MAX 256	217	#define RTSX_HOSTCMD_MAX 256
218	#define RTSX_HOSTCMD_BUFSIZE (sizeof(uint32_t) * RTSX_HOSTCMD_MAX)	218	#define RTSX_HOSTCMD_BUFSIZE (sizeof(uint32_t) * RTSX_HOSTCMD_MAX)
219	#define RTSX_DMA_DATA_BUFSIZE MAXPHYS / 4	219	#define RTSX_DMA_DATA_BUFSIZE MAXPHYS
220	#define RTSX_ADMA_DESC_SIZE (sizeof(uint64_t) * SDMMC_MAXNSEGS)	220	#define RTSX_ADMA_DESC_SIZE (sizeof(uint64_t) * SDMMC_MAXNSEGS)
221		221
222	#define RTSX_NREG ((0XFDAE - 0XFDA0) + (0xFD69 - 0xFD32) + (0xFE34 - 0xFE20))	222	#define RTSX_NREG ((0XFDAE - 0XFDA0) + (0xFD69 - 0xFD32) + (0xFE34 - 0xFE20))
Lines 1630-1635 rtsx_xfer(struct rtsx_softc sc, struct mmc_command cmd) Link Here
1630	cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ?	1630	cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ?
1631	RTSX_MAX_DATA_BLKLEN : cmd->data->len;	1631	RTSX_MAX_DATA_BLKLEN : cmd->data->len;
1632		1632
		1633	RTSX_CLR(sc,RTSX_SD_CFG1,RTSX_CLK_DIVIDE_MASK);
1633	if (bootverbose)	1634	if (bootverbose)
1634	device_printf(sc->rtsx_dev, "rtsx_xfer() - %s xfer: %ld bytes with block size %ld\n",	1635	device_printf(sc->rtsx_dev, "rtsx_xfer() - %s xfer: %ld bytes with block size %ld\n",
1635	read ? "Read" : "Write",	1636	read ? "Read" : "Write",
Lines 1643-1649 rtsx_xfer(struct rtsx_softc sc, struct mmc_command cmd) Link Here
1643	}	1644	}
1644		1645
1645	/* Configure DMA transfer mode parameters. */	1646	/* Configure DMA transfer mode parameters. */
1646	cfg2 = RTSX_SD_NO_CHECK_WAIT_CRC_TO \| RTSX_SD_CHECK_CRC16 \|	1647	cfg2 = RTSX_SD_CHECK_CRC16 \|
1647	RTSX_SD_NO_WAIT_BUSY_END \| RTSX_SD_RSP_LEN_0;	1648	RTSX_SD_NO_WAIT_BUSY_END \| RTSX_SD_RSP_LEN_0;
1648	if (read) {	1649	if (read) {
1649	dma_dir = RTSX_DMA_DIR_FROM_CARD;	1650	dma_dir = RTSX_DMA_DIR_FROM_CARD;
Lines 1652-1658 rtsx_xfer(struct rtsx_softc sc, struct mmc_command cmd) Link Here
1652	* sent the read command and gotten the response, and will	1653	* sent the read command and gotten the response, and will
1653	* send CMD 12 manually after reading multiple blocks.	1654	* send CMD 12 manually after reading multiple blocks.
1654	*/	1655	*/
1655	tmode = RTSX_TM_AUTO_READ3;	1656	tmode = RTSX_TM_AUTO_READ1;
		1657	if(cmd->opcode == 18) {
		1658	cfg2 = 0x1; /RTSX_SD_NO_CHECK_WAIT_CRC_TO\|RTSX_SD_CHECK_CRC16 \|/
		1659	//RTSX_SD_NO_WAIT_BUSY_END \| RTSX_SD_RSP_LEN_0;
		1660	tmode = RTSX_TM_AUTO_READ1;
		1661	}
1656	cfg2 \|= RTSX_SD_CALCULATE_CRC7 \| RTSX_SD_CHECK_CRC7;	1662	cfg2 \|= RTSX_SD_CALCULATE_CRC7 \| RTSX_SD_CHECK_CRC7;
1657	} else {	1663	} else {
1658	dma_dir = RTSX_DMA_DIR_TO_CARD;	1664	dma_dir = RTSX_DMA_DIR_TO_CARD;
Lines 1661-1704 rtsx_xfer(struct rtsx_softc sc, struct mmc_command cmd) Link Here
1661	* sent the write command and gotten the response, and will	1667	* sent the write command and gotten the response, and will
1662	* send CMD 12 manually after writing multiple blocks.	1668	* send CMD 12 manually after writing multiple blocks.
1663	*/	1669	*/
1664	tmode = RTSX_TM_AUTO_WRITE3;	1670	tmode = RTSX_TM_AUTO_WRITE1;
1665	cfg2 \|= RTSX_SD_NO_CALCULATE_CRC7 \| RTSX_SD_NO_CHECK_CRC7;	1671	cfg2 \|= RTSX_SD_NO_CALCULATE_CRC7 \| RTSX_SD_NO_CHECK_CRC7;
1666	}	1672	}
1667		1673
1668	sc->rtsx_cmd_index = 0;	1674	//sc->rtsx_cmd_index = 0;
1669		1675	rtsx_init_cmd(sc,cmd);
1670	/* Queue command to set response type. */	1676	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L,
1671	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2,	1677	0xff, ((cmd->data->len / cmd->data->xfer_len) & 0xff));
1672	0xff, cfg2);	1678	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H,
1673		1679	0xff, ((cmd->data->len / cmd->data->xfer_len) >> 8));
		1680	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L,
		1681	0xff, (cmd->data->xfer_len & 0xff));
		1682	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H,
		1683	0xff, (cmd->data->xfer_len >> 8));
		1684
		1685	/* Configure DMA controller. */
		1686	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0,
		1687	RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT);
1674	/* Queue commands to configure data transfer size. */	1688	/* Queue commands to configure data transfer size. */
1675	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L,	1689
1676	0xff, (cmd->data->xfer_len & 0xff));	1690	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC3,
1677	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H,	1691	0xff, cmd->data->len >> 24);
1678	0xff, (cmd->data->xfer_len >> 8));	1692	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC2,
1679	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L,	1693	0xff, cmd->data->len >> 16);
1680	0xff, ((cmd->data->len / cmd->data->xfer_len) & 0xff));	1694	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC1,
1681	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H,	1695	0xff, cmd->data->len >> 8);
1682	0xff, ((cmd->data->len / cmd->data->xfer_len) >> 8));	1696	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC0,
		1697	0xff, cmd->data->len);
		1698	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMACTL,
		1699	RTSX_DMA_EN \| RTSX_DMA_DIR \| RTSX_DMA_PACK_SIZE_MASK,
		1700	RTSX_DMA_EN \| dma_dir \| RTSX_DMA_512);
1683		1701
1684	/* Use the DMA ring buffer for commands which transfer data. */	1702	/* Use the DMA ring buffer for commands which transfer data. */
1685	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE,	1703	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE,
1686	0x01, RTSX_RING_BUFFER);	1704	0x01, RTSX_RING_BUFFER);
		1705	/* Queue command to set response type. */
		1706	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2,
		1707	0xff, cfg2);
		1708
1687		1709
1688	/* Configure DMA controller. */
1689	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0,
1690	RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT);
1691	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC3,
1692	0xff, cmd->data->len >> 24);
1693	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC2,
1694	0xff, cmd->data->len >> 16);
1695	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC1,
1696	0xff, cmd->data->len >> 8);
1697	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC0,
1698	0xff, cmd->data->len);
1699	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMACTL,
1700	RTSX_DMA_EN \| RTSX_DMA_DIR \| RTSX_DMA_PACK_SIZE_MASK,
1701	RTSX_DMA_EN \| dma_dir \| RTSX_DMA_512);
1702		1710
1703	/* Queue commands to perform SD transfer. */	1711	/* Queue commands to perform SD transfer. */
1704	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER,	1712	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER,
Lines 1717-1724 rtsx_xfer(struct rtsx_softc sc, struct mmc_command cmd) Link Here
1717		1725
1718	/* Tell the chip where the data buffer is and run the transfer. */	1726	/* Tell the chip where the data buffer is and run the transfer. */
1719	WRITE4(sc, RTSX_HDBAR, sc->rtsx_data_buffer);	1727	WRITE4(sc, RTSX_HDBAR, sc->rtsx_data_buffer);
1720	WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA \| (read ? RTSX_DMA_READ : 0) \|	1728	WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA \| (read ? RTSX_DMA_READ : 0) \|
1721	(cmd->data->len & 0x00ffffff));	1729	(cmd->data->len & 0x00ffffff));
1722		1730
1723	if ((error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz * sc->rtsx_timeout))) {	1731	if ((error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz * sc->rtsx_timeout))) {
1724	cmd->error = MMC_ERR_TIMEOUT;	1732	cmd->error = MMC_ERR_TIMEOUT;
Lines 1727-1736 rtsx_xfer(struct rtsx_softc sc, struct mmc_command cmd) Link Here
1727		1735
1728	/* Sync command DMA buffer. */	1736	/* Sync command DMA buffer. */
1729	bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTREAD);	1737	bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTREAD);
1730	bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTWRITE);	1738	bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTWRITE);
		1739	if(read)
		1740	memcpy(cmd->data->data, sc->rtsx_data_dmamem, cmd->data->len);
		1741	else
		1742	memcpy(sc->rtsx_data_dmamem,cmd->data->data,cmd->data->len);
1731		1743
1732	memcpy(cmd->data->data, sc->rtsx_data_dmamem, cmd->data->len);
1733
1734	return (error);	1744	return (error);
1735	}	1745	}
1736		1746
Lines 1870-1876 rtsx_mmcbr_update_ios(device_t bus, device_t child) Link Here
1870	case bus_width_1:	1880	case bus_width_1:
1871	bus_width = RTSX_BUS_WIDTH_1;	1881	bus_width = RTSX_BUS_WIDTH_1;
1872	break;	1882	break;
1873	case bus_width_4:	1883	case bus_width_4:
1874	bus_width = RTSX_BUS_WIDTH_4;	1884	bus_width = RTSX_BUS_WIDTH_4;
1875	break;	1885	break;
1876	case bus_width_8:	1886	case bus_width_8:
Lines 1899-1917 rtsx_mmcbr_update_ios(device_t bus, device_t child) Link Here
1899	break;	1909	break;
1900	case power_up:	1910	case power_up:
1901	if (sc->rtsx_power_mode != power_up) {	1911	if (sc->rtsx_power_mode != power_up) {
1902	rtsx_bus_power_up(sc);	1912	rtsx_bus_power_on(sc);
1903	sc->rtsx_power_mode = power_up;	1913	sc->rtsx_power_mode = power_up;
1904	}	1914	}
1905	break;	1915	break;
1906	case power_on:	1916	case power_on:
1907	if (sc->rtsx_power_mode != power_on) {	1917	if (sc->rtsx_power_mode != power_on) {
1908	rtsx_bus_power_on(sc);	1918	rtsx_bus_power_up(sc);
1909	sc->rtsx_power_mode = power_on;	1919	sc->rtsx_power_mode = power_on;
1910	}	1920	}
1911	break;	1921	break;
1912	};	1922	};
1913		1923
1914	return (0);	1924	return (0);
1915	}	1925	}
1916		1926
1917	/* Set output stage logic power voltage */	1927	/* Set output stage logic power voltage */
Lines 1946-1956 rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused) Link Here
1946	if (bootverbose)	1956	if (bootverbose)
1947	device_printf(sc->rtsx_dev, "rtsx_mmcbr_switch_vccq(%d)\n", vccq);	1957	device_printf(sc->rtsx_dev, "rtsx_mmcbr_switch_vccq(%d)\n", vccq);
1948		1958
1949	rtsx_bus_power_off(sc);
1950		1959
1951	DELAY(200);	1960	//rtsx_bus_power_off(sc);
		1961
		1962	//DELAY(200);
1952		1963
1953	rtsx_bus_power_on(sc);	1964	//rtsx_bus_power_on(sc);
1954	sc->rtsx_power_mode = power_on;	1965	sc->rtsx_power_mode = power_on;
1955		1966
1956	return (0);	1967	return (0);
Lines 1966-1972 rtsx_mmcbr_tune(device_t bus, device_t child __unused, bool hs400 __unused) Link Here
1966		1977
1967	if (bootverbose)	1978	if (bootverbose)
1968	device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune()\n");	1979	device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune()\n");
1969		1980	sc->rtsx_host.ios.clock=RTSX_SDCLK_50MHZ;
1970	return (0);	1981	return (0);
1971		1982
1972	}	1983	}
Lines 2019-2026 rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *re Link Here
2019	}	2030	}
2020		2031
2021	if (cmd->data == NULL) {	2032	if (cmd->data == NULL) {
2022	error = rtsx_send_req_get_resp(sc, cmd);	2033	error = rtsx_send_req_get_resp(sc, cmd);
2023	} else if (cmd->data->len <= 512) {	2034	} else if (cmd->data->len < 512) {
2024	error = rtsx_xfer_short(sc, cmd);	2035	error = rtsx_xfer_short(sc, cmd);
2025	if (error) {	2036	if (error) {
2026	uint8_t stat1;	2037	uint8_t stat1;
Lines 2031-2039 rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *re Link Here
2031	}	2042	}
2032	}	2043	}
2033	} else {	2044	} else {
2034	error = rtsx_send_req_get_resp(sc, cmd);	2045	error = rtsx_xfer(sc, cmd);
2035	if (!error) {
2036	error = rtsx_xfer(sc, cmd);
2037	if (error) {	2046	if (error) {
2038	uint8_t stat1;	2047	uint8_t stat1;
2039	if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 &&	2048	if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 &&
Lines 2042-2048 rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *re Link Here
2042	cmd->error = MMC_ERR_BADCRC;	2051	cmd->error = MMC_ERR_BADCRC;
2043	}	2052	}
2044	}	2053	}
2045	}
2046	}	2054	}
2047		2055
2048	done:	2056	done: