Index: cad/verilator/Makefile =================================================================== --- cad/verilator/Makefile (revision 542534) +++ cad/verilator/Makefile (working copy) @@ -1,7 +1,7 @@ # $FreeBSD$ PORTNAME= verilator -DISTVERSION= 4.036 +DISTVERSION= 4.038 CATEGORIES= cad MASTER_SITES= https://www.veripool.org/ftp/ Index: cad/verilator/distinfo =================================================================== --- cad/verilator/distinfo (revision 542534) +++ cad/verilator/distinfo (working copy) @@ -1,5 +1,5 @@ -TIMESTAMP = 1594246998 -SHA256 (verilator-4.036.tgz) = 307cf2657328b6e529af48c2d7d06b78b98d00d4f0148a484173cf81df15c0eb -SIZE (verilator-4.036.tgz) = 2678827 +TIMESTAMP = 1595108832 +SHA256 (verilator-4.038.tgz) = fa004493216034ac3e26b21b814441bd5801592f4f269c5a4672e3351d73b515 +SIZE (verilator-4.038.tgz) = 2703465 SHA256 (39f16fb155b9e909f919a9d4ae06890395987b16.patch) = 266c63d54bc00d4a67163b701a10cf238faf9c21f04e0c8192bd5495ff000b80 SIZE (39f16fb155b9e909f919a9d4ae06890395987b16.patch) = 590 Index: cad/verilator/files/patch-src-verilog.y =================================================================== --- cad/verilator/files/patch-src-verilog.y (revision 542534) +++ cad/verilator/files/patch-src-verilog.y (working copy) @@ -1,18 +1,18 @@ ---- src/verilog.y.orig 2020-02-08 14:14:33 UTC +--- src/verilog.y.orig 2020-07-11 01:58:03 UTC +++ src/verilog.y -@@ -20,6 +20,7 @@ - // Original code here by Paul Wasson and Duane Galbi +@@ -17,6 +17,7 @@ //************************************************************************* + // clang-format off +%define parse.error verbose %{ - #include "V3Ast.h" - #include "V3Global.h" -@@ -29,7 +30,6 @@ - #include + #ifdef NEVER_JUST_FOR_CLANG_FORMAT + } +@@ -31,7 +32,6 @@ #include + #include --#define YYERROR_VERBOSE 1 - #define YYINITDEPTH 10000 // Older bisons ignore YYMAXDEPTH +-#define YYERROR_VERBOSE 1 // For prior to Bison 3.6 + #define YYINITDEPTH 10000 // Older bisons ignore YYMAXDEPTH #define YYMAXDEPTH 10000