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--- arch/arm/dts/armada-8040-clearfog-gt-8k.dts.orig 2020-10-05 15:15:32.000000000 +0000 |
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+++ arch/arm/dts/armada-8040-clearfog-gt-8k.dts 2021-04-10 16:04:09.421325000 +0000 |
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@@ -104,15 +104,25 @@ |
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marvell,function = <0>; |
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}; |
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|
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- cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { |
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- marvell,pins = < 47 >; |
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+ cpm_pcie1_reset_pins: cpm-pcie1-reset-pins { |
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+ marvell,pins = < 33 >; |
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marvell,function = <0>; |
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}; |
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|
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+ cpm_pcie2_reset_pins: cpm-pcie2-reset-pins { |
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+ marvell,pins = < 34 >; |
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+ marvell,function = <0>; |
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+ }; |
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+ |
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cps_1g_phy_reset: cps-1g-phy-reset { |
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marvell,pins = < 43 >; |
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marvell,function = <0>; |
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}; |
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+ |
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+ cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { |
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+ marvell,pins = < 47 >; |
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+ marvell,function = <0>; |
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+ }; |
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}; |
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|
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/* uSD slot */ |
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@@ -131,6 +141,15 @@ |
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status = "okay"; |
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}; |
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|
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+/* USB */ |
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+&cpm_pcie1 { |
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+ num-lanes = <1>; |
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+ pinctrl-names = "default"; |
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+ pinctrl-0 = <&cpm_pcie2_reset_pins>; |
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+ marvell,reset-gpio = <&cpm_gpio1 2 GPIO_ACTIVE_LOW>; |
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+ status = "okay"; |
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+}; |
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+ |
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&cpm_i2c0 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&cpm_i2c0_pins>; |
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@@ -145,8 +164,9 @@ |
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clock-frequency = <100000>; |
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}; |
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|
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+/* ??? */ |
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&cpm_sata0 { |
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- status = "okay"; |
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+ status = "disabled"; |
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}; |
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|
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&cpm_comphy { |
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@@ -172,7 +192,7 @@ |
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phy-type = <PHY_TYPE_UNCONNECTED>; |
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}; |
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phy4 { |
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- phy-type = <PHY_TYPE_USB3_HOST1>; |
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+ phy-type = <PHY_TYPE_PEX1>; |
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}; |
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phy5 { |
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phy-type = <PHY_TYPE_UNCONNECTED>; |
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@@ -190,19 +210,6 @@ |
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phy-mode = "sfi"; |
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}; |
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|
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-&cps_sata0 { |
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- status = "okay"; |
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-}; |
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- |
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-&cps_usb3_0 { |
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- vbus-supply = <®_usb3h0_vbus>; |
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- status = "okay"; |
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-}; |
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- |
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-&cps_utmi0 { |
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- status = "okay"; |
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-}; |
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- |
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&cps_pinctl { |
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/* |
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* MPP Bus: |
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@@ -272,8 +279,7 @@ |
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* Lane 5: SGMII2 - Connected to Topaz switch |
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*/ |
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phy0 { |
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- phy-type = <PHY_TYPE_SATA1>; |
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- phy-invert = <PHY_POLARITY_RXD_INVERT>; |
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+ phy-type = <PHY_TYPE_PEX0>; |
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}; |
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phy1 { |
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phy-type = <PHY_TYPE_UNCONNECTED>; |
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@@ -292,6 +298,28 @@ |
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phy-type = <PHY_TYPE_SGMII2>; |
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phy-speed = <PHY_SPEED_3_125G>; |
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}; |
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+}; |
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+ |
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+&cps_sata0 { |
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+ status = "disabled"; |
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+}; |
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+ |
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+/* SATA */ |
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+&cps_pcie0 { |
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+ num-lanes = <1>; |
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+ pinctrl-names = "default"; |
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+ pinctrl-0 = <&cpm_pcie1_reset_pins>; |
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+ marvell,reset-gpio = <&cpm_gpio1 1 GPIO_ACTIVE_LOW>; |
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+ status = "okay"; |
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+}; |
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+ |
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+&cps_usb3_0 { |
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+ vbus-supply = <®_usb3h0_vbus>; |
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+ status = "okay"; |
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+}; |
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+ |
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+&cps_utmi0 { |
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+ status = "okay"; |
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}; |
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|
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&cps_mdio { |