--- /dev/null	
+++ sysutils/u-boot-clearfog-gt8k/Makefile	
@@ -0,0 +1,15 @@ 
+# $FreeBSD$
+
+MASTERDIR=	${.CURDIR}/../u-boot-master
+
+OPTIONS_DEFINE=	PCIE3X
+OPTIONS_DEFAULT=
+
+PCIE3X_DESC=	Change U-Boot DTB make all 3 slots PCIe (not SATA/USB)
+PCIE3X_EXTRA_PATCHES+=	${.CURDIR}/files/extra-patch-gt8k-3xpci.diff
+
+MODEL=		clearfog_gt_8k
+BOARD_CONFIG=	clearfog_gt_8k_defconfig
+FAMILY=		armada8040
+
+.include "${MASTERDIR}/Makefile"
--- /dev/null	
+++ sysutils/u-boot-clearfog-gt8k/files/extra-patch-gt8k-3xpci.diff	
@@ -0,0 +1,125 @@ 
+--- arch/arm/dts/armada-8040-clearfog-gt-8k.dts.orig	2020-10-05 15:15:32.000000000 +0000
++++ arch/arm/dts/armada-8040-clearfog-gt-8k.dts	2021-04-10 16:04:09.421325000 +0000
+@@ -104,15 +104,25 @@
+ 		marvell,function = <0>;
+ 	};
+ 
+-	cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
+-		marvell,pins = < 47 >;
++	cpm_pcie1_reset_pins: cpm-pcie1-reset-pins {
++		marvell,pins = < 33 >;
+ 		marvell,function = <0>;
+ 	};
+ 
++	cpm_pcie2_reset_pins: cpm-pcie2-reset-pins {
++		marvell,pins = < 34 >;
++		marvell,function = <0>;
++	};
++
+ 	cps_1g_phy_reset: cps-1g-phy-reset {
+ 		marvell,pins = < 43 >;
+ 		marvell,function = <0>;
+ 	};
++
++	cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
++		marvell,pins = < 47 >;
++		marvell,function = <0>;
++	};
+ };
+ 
+ /* uSD slot */
+@@ -131,6 +141,15 @@
+ 	status = "okay";
+ };
+ 
++/* USB */
++&cpm_pcie1 {
++	num-lanes = <1>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&cpm_pcie2_reset_pins>;
++	marvell,reset-gpio = <&cpm_gpio1 2 GPIO_ACTIVE_LOW>;
++	status = "okay";
++};
++
+ &cpm_i2c0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&cpm_i2c0_pins>;
+@@ -145,8 +164,9 @@
+ 	clock-frequency = <100000>;
+ };
+ 
++/* ??? */
+ &cpm_sata0 {
+-	status = "okay";
++	status = "disabled";
+ };
+ 
+ &cpm_comphy {
+@@ -172,7 +192,7 @@
+ 		phy-type = <PHY_TYPE_UNCONNECTED>;
+ 	};
+ 	phy4 {
+-		phy-type = <PHY_TYPE_USB3_HOST1>;
++		phy-type = <PHY_TYPE_PEX1>;
+ 	};
+ 	phy5 {
+ 		phy-type = <PHY_TYPE_UNCONNECTED>;
+@@ -190,19 +210,6 @@
+         phy-mode = "sfi";
+ };
+ 
+-&cps_sata0 {
+-	status = "okay";
+-};
+-
+-&cps_usb3_0 {
+-	vbus-supply = <&reg_usb3h0_vbus>;
+-	status = "okay";
+-};
+-
+-&cps_utmi0 {
+-	status = "okay";
+-};
+-
+ &cps_pinctl {
+ 	/*
+ 	 * MPP Bus:
+@@ -272,8 +279,7 @@
+ 	 * Lane 5: SGMII2 - Connected to Topaz switch
+ 	 */
+ 	phy0 {
+-		phy-type = <PHY_TYPE_SATA1>;
+-		phy-invert = <PHY_POLARITY_RXD_INVERT>;
++		phy-type = <PHY_TYPE_PEX0>;
+ 	};
+ 	phy1 {
+ 		phy-type = <PHY_TYPE_UNCONNECTED>;
+@@ -292,6 +298,28 @@
+ 		phy-type = <PHY_TYPE_SGMII2>;
+ 		phy-speed = <PHY_SPEED_3_125G>;
+ 	};
++};
++
++&cps_sata0 {
++	status = "disabled";
++};
++
++/* SATA */
++&cps_pcie0 {
++	num-lanes = <1>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&cpm_pcie1_reset_pins>;
++	marvell,reset-gpio = <&cpm_gpio1 1 GPIO_ACTIVE_LOW>;
++	status = "okay";
++};
++
++&cps_usb3_0 {
++	vbus-supply = <&reg_usb3h0_vbus>;
++	status = "okay";
++};
++
++&cps_utmi0 {
++	status = "okay";
+ };
+ 
+ &cps_mdio {
--- /dev/null	
+++ sysutils/u-boot-clearfog-gt8k/pkg-descr	
@@ -0,0 +1,10 @@ 
+U-Boot loader for the SolidRun ClearFog GT 8K.
+
+u-boot.bin should not be written out to any storage
+for any device directly.
+It is used as input for atf-marvell-gt8k.
+
+If you set the 3x mPCIe option you will also have to
+patch the base system dts file.
+
+WWW: https://www.denx.de/wiki/U-Boot
--- sysutils/u-boot-master/Makefile	
+++ sysutils/u-boot-master/Makefile	
@@ -104,6 +104,10 @@ UBOOT_METADATA_ARMADA38X_METHOD=	raw
 UBOOT_METADATA_ARMADA38X_RAW_OFFSET=	1
 UBOOT_METADATA_ARMADA38X_RAW_BS=	512
 
+# Override for ARMADA8040 family
+UBOOT_PLIST_ARMADA8040=	u-boot.bin
+UBOOT_ARCH_ARMADA8040=	aarch64
+
 # Override for QEMU family
 UBOOT_PLIST_QEMU=	u-boot.bin