Attachment 225194 Details for Bug 256101 – Gemini Lake UART patch

[patch] Gemini Lake UART patch

geminilake_uart.diff (text/plain), 1006 bytes, created by Daniel Ponte on 2021-05-23 13:27:49 UTC

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Creator: Daniel Ponte

Created: 2021-05-23 13:27:49 UTC

Size: 1006 bytes

patch

obsolete

>diff --git a/sys/dev/uart/uart_bus_pci.c b/sys/dev/uart/uart_bus_pci.c
>index 707b82dc078b..8c73299aa5db 100644
>--- a/sys/dev/uart/uart_bus_pci.c
>+++ b/sys/dev/uart/uart_bus_pci.c
>@@ -155,6 +155,14 @@ static const struct pci_id pci_ns8250_ids[] = {
>        24 * DEFAULT_RCLK, 2 },
> { 0x8086, 0x5aee, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 3", 0x10,
>        24 * DEFAULT_RCLK, 2 },
>+{ 0x8086, 0x31bc, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 0", 0x10,
>+       24 * DEFAULT_RCLK, 2 },
>+{ 0x8086, 0x31be, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 1", 0x10,
>+       24 * DEFAULT_RCLK, 2 },
>+{ 0x8086, 0x31c0, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 2", 0x10,
>+       24 * DEFAULT_RCLK, 2 },
>+{ 0x8086, 0x31ee, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 3", 0x10,
>+       24 * DEFAULT_RCLK, 2 },
> { 0x8086, 0x8811, 0xffff, 0, "Intel EG20T Serial Port 0", 0x10 },
> { 0x8086, 0x8812, 0xffff, 0, "Intel EG20T Serial Port 1", 0x10 },
> { 0x8086, 0x8813, 0xffff, 0, "Intel EG20T Serial Port 2", 0x10 },

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Attachments on bug 256101: 225194