Attachment #228109 for bug #258153

Lines 1728-1734 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) Link Here

(-)b/sys/dev/e1000/e1000_ich8lan.c (-1 / +44 lines)
1728	if (ret_val)	1728	if (ret_val)
1729	return ret_val;	1729	return ret_val;
1730	}	1730	}
1731
1732	/* Clear link partner's EEE ability */	1731	/* Clear link partner's EEE ability */
1733	hw->dev_spec.ich8lan.eee_lp_ability = 0;	1732	hw->dev_spec.ich8lan.eee_lp_ability = 0;
1734		1733
Lines 1749-1754 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) Link Here
1749	fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;	1748	fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1750		1749
1751	E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);	1750	E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
		1751
		1752	/* Configure K0s minimum time */
		1753	e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1752	}	1754	}
1753		1755
1754	if (!link)	1756	if (!link)
Lines 6144-6146 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) Link Here
6144	}	6146	}
6145	}	6147	}
6146		6148
		6149	/**
		6150	* e1000_configure_k0s_lpt - Configure K0s power state
		6151	* @hw: pointer to the HW structure
		6152	* @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
		6153	* 0 corresponds to 128ns, each value over 0 doubles the duration.
		6154	* @min_time: Minimum Tx idle period allowed - valid values are 0 to 4.
		6155	* 0 corresponds to 128ns, each value over 0 doubles the duration.
		6156	*
		6157	* Configure the K1 power state based on the provided parameter.
		6158	* Assumes semaphore already acquired.
		6159	*
		6160	* Success returns 0, Failure returns:
		6161	* -E1000_ERR_PHY (-2) in case of access error
		6162	* -E1000_ERR_PARAM (-4) in case of parameters error
		6163	**/
		6164	s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
		6165	{
		6166	s32 ret_val;
		6167	u16 kmrn_reg = 0;
		6168
		6169	DEBUGFUNC("e1000_configure_k0s_lpt");
		6170
		6171	if (entry_latency > 3 \|\| min_time > 4)
		6172	return -E1000_ERR_PARAM;
		6173
		6174	ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
		6175	&kmrn_reg);
		6176	if (ret_val)
		6177	return ret_val;
		6178
		6179	/* for now don't touch the latency */
		6180	kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
		6181	kmrn_reg \|= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
		6182
		6183	ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
		6184	kmrn_reg);
		6185	if (ret_val)
		6186	return ret_val;
		6187
		6188	return E1000_SUCCESS;
		6189	}

Lines 337-342 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); Link Here

(-)b/sys/dev/e1000/e1000_ich8lan.h (+1 lines)
337	void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);	337	void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
338	u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw);	338	u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
339	s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);	339	s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
		340	s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time);
340	void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);	341	void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
341	s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);	342	s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
342	s32 e1000_read_emi_reg_locked(struct e1000_hw hw, u16 addr, u16 data);	343	s32 e1000_read_emi_reg_locked(struct e1000_hw hw, u16 addr, u16 data);

Lines 281-286 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, Link Here

(-)b/sys/dev/e1000/e1000_phy.h (+7 lines)
281	#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7	281	#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
282	#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */	282	#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */
283	#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */	283	#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
		284	#define E1000_KMRNCTRLSTA_K0S_CTRL 0x1E /* Kumeran K0s Control */
		285	#define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT 0
		286	#define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT 4
		287	#define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_MASK \
		288	(3 << E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT)
		289	#define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK \
		290	(7 << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT)
284		291
285	#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10	292	#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
286	#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */	293	#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */

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