Attachment #228110 for bug #258153





#include "e1000_api.h"

static s32  e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
static s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
static s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);

	 * so forcibly disable it.
	 */
	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
	e1000_disable_ulp_lpt_lp(hw, TRUE);

	ret_val = hw->phy.ops.acquire(hw);
	if (ret_val) {

static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
{
	struct e1000_mac_info *mac = &hw->mac;
	u16 pci_cfg;

	DEBUGFUNC("e1000_init_mac_params_ich8lan");


			e1000_update_mc_addr_list_pch2lan;
		/* FALLTHROUGH */
	case e1000_pchlan:
		/* save PCH revision_id */
		e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
		/* SPT uses full byte for revision ID,
		 * as opposed to previous generations
		 */
		if (hw->mac.type >= e1000_pch_spt)
			hw->revision_id = (u8)(pci_cfg &= 0x00FF);
		else
			 hw->revision_id = (u8)(pci_cfg &= 0x000F);
		/* check management mode */
		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
		/* ID LED init */

	    (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
		return 0;

	if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
		/* Request ME configure ULP mode in the PHY */
		mac_reg = E1000_READ_REG(hw, E1000_H2ME);
		mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
		E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);

		goto out;
	}

	if (!to_sx) {
		int i = 0;

		/* Poll up to 5 seconds for Cable Disconnected indication */
		while (!(E1000_READ_REG(hw, E1000_FEXT) &
			 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
			/* Bail if link is re-acquired */
			if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
				return -E1000_ERR_PHY;

			if (i++ == 100)
				break;


		if (!(E1000_READ_REG(hw, E1000_FEXT) &
		    E1000_FEXT_PHY_CABLE_DISCONNECTED))
			return 0;
	}

	if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
		/* Request ME configure ULP mode in the PHY */
		mac_reg = E1000_READ_REG(hw, E1000_H2ME);
		mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
		E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);

		goto out;
	}

	ret_val = hw->phy.ops.acquire(hw);
	if (ret_val)
		goto out;

	/* During S0 Idle keep the phy in PCI-E mode */
	if (hw->dev_spec.ich8lan.smbus_disable)
		goto skip_smbus;

	/* Force SMBus mode in PHY */
	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
	if (ret_val)

			goto release;
	}

skip_smbus:
	if (!to_sx) {
		/* Change the 'Link Status Change' interrupt to trigger
		 * on 'Cable Status Change'
		 */
		ret_val = e1000_read_kmrn_reg_locked(hw,
						     E1000_KMRNCTRLSTA_OP_MODES,
						     &phy_reg);
		if (ret_val)
			goto release;
		phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
		e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
					    phy_reg);
	}

	/* Set Inband ULP Exit, Reset to SMBus mode and
	 * Disable SMBus Release on PERST# in PHY
	 */

	phy_reg |= I218_ULP_CONFIG1_START;
	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);

	if (!to_sx) {
		/* Disable Tx so that the MAC doesn't send any (buffered)
		 * packets to the PHY.
		 */
		mac_reg = E1000_READ_REG(hw, E1000_TCTL);
		mac_reg &= ~E1000_TCTL_EN;
		E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
	}

	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
	    to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,

 *  to disable ULP mode (force=false); otherwise, for example when unloading
 *  the driver or during Sx->S0 transitions, this is called with force=true
 *  to forcibly disable ULP.
 *
 *  When the cable is plugged in while the device is in D0, a Cable Status
 *  Change interrupt is generated which causes this function to be called
 *  to partially disable ULP mode and restart autonegotiation.  This function
 *  is then called again due to the resulting Link Status Change interrupt
 *  to finish cleaning up after the ULP flow.
 */
s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
{

			mac_reg = E1000_READ_REG(hw, E1000_H2ME);
			mac_reg &= ~E1000_H2ME_ULP;
			E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);

			/* Restore link speed advertisements and restart
			 * Auto-negotiation
			 */
			if (hw->mac.autoneg) {
				ret_val = e1000_phy_setup_autoneg(hw);
				if (ret_val)
					goto out;
			} else {
				ret_val = e1000_setup_copper_link_generic(hw);
				if (ret_val)
					goto out;
			}
			ret_val = e1000_oem_bits_config_ich8lan(hw, true);
		}

		goto out;

	if (ret_val)
		goto out;

	/* Revert the change to the 'Link Status Change'
	 * interrupt to trigger on 'Cable Status Change'
	 */
	ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
					     &phy_reg);
	if (ret_val)
		goto release;
	phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
	e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);

	if (force)
		/* Toggle LANPHYPC Value bit */
		e1000_toggle_lanphypc_pch_lpt(hw);

	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
	if (ret_val)
		goto release;
	/* CSC interrupt received due to ULP Indication */
	if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
		phy_reg &= ~(I218_ULP_CONFIG1_IND |
			     I218_ULP_CONFIG1_STICKY_ULP |
			     I218_ULP_CONFIG1_RESET_TO_SMBUS |
			     I218_ULP_CONFIG1_WOL_HOST |
			     I218_ULP_CONFIG1_INBAND_EXIT |
			     I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
			     I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
			     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
		e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);

		/* Commit ULP changes by starting auto ULP configuration */
		phy_reg |= I218_ULP_CONFIG1_START;
		e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);

		/* Clear Disable SMBus Release on PERST# in MAC */
		mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
		mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
		E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);

		if (!force) {
			hw->phy.ops.release(hw);

			if (hw->mac.autoneg)
				e1000_phy_setup_autoneg(hw);
			else
				e1000_setup_copper_link_generic(hw);

			e1000_sw_lcd_config_ich8lan(hw);
	phy_reg |= I218_ULP_CONFIG1_START;
	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);

			e1000_oem_bits_config_ich8lan(hw, true);

			/* Set ULP state to unknown and return non-zero to
			 * indicate no link (yet) and re-enter on the next LSC
			 * to finish disabling ULP flow.
			 */
			hw->dev_spec.ich8lan.ulp_state =
			    e1000_ulp_state_unknown;

			return 1;
		}
	}

	/* Re-enable Tx */
	mac_reg = E1000_READ_REG(hw, E1000_TCTL);
	mac_reg |= E1000_TCTL_EN;
	E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);

release:
	hw->phy.ops.release(hw);

	struct e1000_mac_info *mac = &hw->mac;
	s32 ret_val, tipg_reg = 0;
	u16 emi_addr, emi_val = 0;
	bool link = false;
	u16 phy_reg;

	DEBUGFUNC("e1000_check_for_copper_link_ich8lan");

	if (!mac->get_link_status)
		return E1000_SUCCESS;

	if ((hw->mac.type < e1000_pch_lpt) ||
	    (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
	    (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
		/* First we want to see if the MII Status Register reports
		 * link.  If so, then we want to get the current speed/duplex
		 * of the PHY.
		 */
		ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
		if (ret_val)
			return ret_val;
	} else {
		/* Check the MAC's STATUS register to determine link state
		 * since the PHY could be inaccessible while in ULP mode.
		 */
		link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
		if (link)
			ret_val = e1000_disable_ulp_lpt_lp(hw, false);
		else
			ret_val = e1000_enable_ulp_lpt_lp(hw, false);
		if (ret_val)
			return ret_val;
	}

	if (hw->mac.type == e1000_pchlan) {
		ret_val = e1000_k1_gig_workaround_hv(hw, link);

		if (ret_val)
			return ret_val;
	}

	/* Clear link partner's EEE ability */
	hw->dev_spec.ich8lan.eee_lp_ability = 0;


			fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;

		E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);

		/* Configure K0s minimum time */
		e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
	}

	if (!link)

							  (u8)(data >> 8));
		if (ret_val)
			break;
	}

	/* Don't bother writing the segment valid bits if sector
	 * programming failed.

	}
}

/**
 *  e1000_configure_k0s_lpt - Configure K0s power state
 *  @hw: pointer to the HW structure
 *  @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
 *	0 corresponds to 128ns, each value over 0 doubles the duration.
 *  @min_time: Minimum Tx idle period allowed  - valid values are 0 to 4.
 *	0 corresponds to 128ns, each value over 0 doubles the duration.
 *
 *  Configure the K1 power state based on the provided parameter.
 *  Assumes semaphore already acquired.
 *
 *  Success returns 0, Failure returns:
 *	-E1000_ERR_PHY (-2) in case of access error
 *	-E1000_ERR_PARAM (-4) in case of parameters error
 **/
s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
{
	s32 ret_val;
	u16 kmrn_reg = 0;

	DEBUGFUNC("e1000_configure_k0s_lpt");

	if (entry_latency > 3 || min_time > 4)
		return -E1000_ERR_PARAM;

	ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
					     &kmrn_reg);
	if (ret_val)
		return ret_val;

	/* for now don't touch the latency */
	kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
	kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));

	ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
					      kmrn_reg);
	if (ret_val)
		return ret_val;

	return E1000_SUCCESS;
}

Lines 330-335 Link Here

(-)b/sys/dev/e1000/e1000_ich8lan.h (+2 lines)
330		330
331	#define E1000_PCI_VENDOR_ID_REGISTER 0x00	331	#define E1000_PCI_VENDOR_ID_REGISTER 0x00
332		332
		333	#define E1000_PCI_REVISION_ID_REG 0x08
333	void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,	334	void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
334	bool state);	335	bool state);
335	void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);	336	void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
Lines 337-342 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); Link Here
337	void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);	338	void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
338	u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw);	339	u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
339	s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);	340	s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
		341	s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time);
340	void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);	342	void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
341	s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);	343	s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
342	s32 e1000_read_emi_reg_locked(struct e1000_hw hw, u16 addr, u16 data);	344	s32 e1000_read_emi_reg_locked(struct e1000_hw hw, u16 addr, u16 data);

Lines 281-286 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, Link Here

(-)b/sys/dev/e1000/e1000_phy.h (+9 lines)
281	#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7	281	#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
282	#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */	282	#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */
283	#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */	283	#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
		284	#define E1000_KMRNCTRLSTA_K0S_CTRL 0x1E /* Kumeran K0s Control */
		285	#define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT 0
		286	#define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT 4
		287	#define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_MASK \
		288	(3 << E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT)
		289	#define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK \
		290	(7 << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT)
		291	#define E1000_KMRNCTRLSTA_OP_MODES 0x1F /* Kumeran Modes of Operation */
		292	#define E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC 0x0002 /* change LSC to CSC */
284		293
285	#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10	294	#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
286	#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */	295	#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */

Return to bug 258153

Lines 72-77 Link Here

(-)b/sys/dev/e1000/e1000_ich8lan.c (-38 / +191 lines)
72		72
73	#include "e1000_api.h"	73	#include "e1000_api.h"
74		74
		75	static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
75	static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);	76	static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
76	static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);	77	static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
77	static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);	78	static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
Lines 330-336 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) Link Here
330	* so forcibly disable it.	331	* so forcibly disable it.
331	*/	332	*/
332	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;	333	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
333	e1000_disable_ulp_lpt_lp(hw, TRUE);
334		334
335	ret_val = hw->phy.ops.acquire(hw);	335	ret_val = hw->phy.ops.acquire(hw);
336	if (ret_val) {	336	if (ret_val) {
Lines 730-735 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) Link Here
730	static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)	730	static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
731	{	731	{
732	struct e1000_mac_info *mac = &hw->mac;	732	struct e1000_mac_info *mac = &hw->mac;
		733	u16 pci_cfg;
733		734
734	DEBUGFUNC("e1000_init_mac_params_ich8lan");	735	DEBUGFUNC("e1000_init_mac_params_ich8lan");
735		736
Lines 808-813 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) Link Here
808	e1000_update_mc_addr_list_pch2lan;	809	e1000_update_mc_addr_list_pch2lan;
809	/* FALLTHROUGH */	810	/* FALLTHROUGH */
810	case e1000_pchlan:	811	case e1000_pchlan:
		812	/* save PCH revision_id */
		813	e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
		814	/* SPT uses full byte for revision ID,
		815	* as opposed to previous generations
		816	*/
		817	if (hw->mac.type >= e1000_pch_spt)
		818	hw->revision_id = (u8)(pci_cfg &= 0x00FF);
		819	else
		820	hw->revision_id = (u8)(pci_cfg &= 0x000F);
811	/* check management mode */	821	/* check management mode */
812	mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;	822	mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
813	/* ID LED init */	823	/* ID LED init */
Lines 1279-1303 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) Link Here
1279	(hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))	1289	(hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1280	return 0;	1290	return 0;
1281		1291
1282	if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1283	/* Request ME configure ULP mode in the PHY */
1284	mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1285	mac_reg \|= E1000_H2ME_ULP \| E1000_H2ME_ENFORCE_SETTINGS;
1286	E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1287
1288	goto out;
1289	}
1290
1291	if (!to_sx) {	1292	if (!to_sx) {
1292	int i = 0;	1293	int i = 0;
1293
1294	/* Poll up to 5 seconds for Cable Disconnected indication */	1294	/* Poll up to 5 seconds for Cable Disconnected indication */
1295	while (!(E1000_READ_REG(hw, E1000_FEXT) &	1295	while (!(E1000_READ_REG(hw, E1000_FEXT) &
1296	E1000_FEXT_PHY_CABLE_DISCONNECTED)) {	1296	E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1297	/* Bail if link is re-acquired */	1297	/* Bail if link is re-acquired */
1298	if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)	1298	if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1299	return -E1000_ERR_PHY;	1299	return -E1000_ERR_PHY;
1300
1301	if (i++ == 100)	1300	if (i++ == 100)
1302	break;	1301	break;
1303		1302
Lines 1310-1322 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) Link Here
1310	if (!(E1000_READ_REG(hw, E1000_FEXT) &	1309	if (!(E1000_READ_REG(hw, E1000_FEXT) &
1311	E1000_FEXT_PHY_CABLE_DISCONNECTED))	1310	E1000_FEXT_PHY_CABLE_DISCONNECTED))
1312	return 0;	1311	return 0;
		1312	}
1313		1313
		1314	if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
		1315	/* Request ME configure ULP mode in the PHY */
		1316	mac_reg = E1000_READ_REG(hw, E1000_H2ME);
		1317	mac_reg \|= E1000_H2ME_ULP \| E1000_H2ME_ENFORCE_SETTINGS;
		1318	E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
		1319
		1320	goto out;
1314	}	1321	}
1315		1322
1316	ret_val = hw->phy.ops.acquire(hw);	1323	ret_val = hw->phy.ops.acquire(hw);
1317	if (ret_val)	1324	if (ret_val)
1318	goto out;	1325	goto out;
1319		1326
		1327	/* During S0 Idle keep the phy in PCI-E mode */
		1328	if (hw->dev_spec.ich8lan.smbus_disable)
		1329	goto skip_smbus;
		1330
1320	/* Force SMBus mode in PHY */	1331	/* Force SMBus mode in PHY */
1321	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);	1332	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1322	if (ret_val)	1333	if (ret_val)
Lines 1348-1353 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) Link Here
1348	goto release;	1359	goto release;
1349	}	1360	}
1350		1361
		1362	skip_smbus:
		1363	if (!to_sx) {
		1364	/* Change the 'Link Status Change' interrupt to trigger
		1365	* on 'Cable Status Change'
		1366	*/
		1367	ret_val = e1000_read_kmrn_reg_locked(hw,
		1368	E1000_KMRNCTRLSTA_OP_MODES,
		1369	&phy_reg);
		1370	if (ret_val)
		1371	goto release;
		1372	phy_reg \|= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
		1373	e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
		1374	phy_reg);
		1375	}
		1376
1351	/* Set Inband ULP Exit, Reset to SMBus mode and	1377	/* Set Inband ULP Exit, Reset to SMBus mode and
1352	* Disable SMBus Release on PERST# in PHY	1378	* Disable SMBus Release on PERST# in PHY
1353	*/	1379	*/
Lines 1380-1385 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) Link Here
1380	phy_reg \|= I218_ULP_CONFIG1_START;	1406	phy_reg \|= I218_ULP_CONFIG1_START;
1381	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);	1407	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1382		1408
		1409	if (!to_sx) {
		1410	/* Disable Tx so that the MAC doesn't send any (buffered)
		1411	* packets to the PHY.
		1412	*/
		1413	mac_reg = E1000_READ_REG(hw, E1000_TCTL);
		1414	mac_reg &= ~E1000_TCTL_EN;
		1415	E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
		1416	}
		1417
1383	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&	1418	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1384	to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {	1419	to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1385	ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,	1420	ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
Lines 1413-1418 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) Link Here
1413	* to disable ULP mode (force=false); otherwise, for example when unloading	1448	* to disable ULP mode (force=false); otherwise, for example when unloading
1414	* the driver or during Sx->S0 transitions, this is called with force=true	1449	* the driver or during Sx->S0 transitions, this is called with force=true
1415	* to forcibly disable ULP.	1450	* to forcibly disable ULP.
		1451	*
		1452	* When the cable is plugged in while the device is in D0, a Cable Status
		1453	* Change interrupt is generated which causes this function to be called
		1454	* to partially disable ULP mode and restart autonegotiation. This function
		1455	* is then called again due to the resulting Link Status Change interrupt
		1456	* to finish cleaning up after the ULP flow.
1416	*/	1457	*/
1417	s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)	1458	s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1418	{	1459	{
Lines 1462-1467 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) Link Here
1462	mac_reg = E1000_READ_REG(hw, E1000_H2ME);	1503	mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1463	mac_reg &= ~E1000_H2ME_ULP;	1504	mac_reg &= ~E1000_H2ME_ULP;
1464	E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);	1505	E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
		1506
		1507	/* Restore link speed advertisements and restart
		1508	* Auto-negotiation
		1509	*/
		1510	if (hw->mac.autoneg) {
		1511	ret_val = e1000_phy_setup_autoneg(hw);
		1512	if (ret_val)
		1513	goto out;
		1514	} else {
		1515	ret_val = e1000_setup_copper_link_generic(hw);
		1516	if (ret_val)
		1517	goto out;
		1518	}
		1519	ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1465	}	1520	}
1466		1521
1467	goto out;	1522	goto out;
Lines 1471-1476 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) Link Here
1471	if (ret_val)	1526	if (ret_val)
1472	goto out;	1527	goto out;
1473		1528
		1529	/* Revert the change to the 'Link Status Change'
		1530	* interrupt to trigger on 'Cable Status Change'
		1531	*/
		1532	ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
		1533	&phy_reg);
		1534	if (ret_val)
		1535	goto release;
		1536	phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
		1537	e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
		1538
1474	if (force)	1539	if (force)
1475	/* Toggle LANPHYPC Value bit */	1540	/* Toggle LANPHYPC Value bit */
1476	e1000_toggle_lanphypc_pch_lpt(hw);	1541	e1000_toggle_lanphypc_pch_lpt(hw);
Lines 1513-1536 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) Link Here
1513	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);	1578	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1514	if (ret_val)	1579	if (ret_val)
1515	goto release;	1580	goto release;
1516	phy_reg &= ~(I218_ULP_CONFIG1_IND \|	1581	/* CSC interrupt received due to ULP Indication */
1517	I218_ULP_CONFIG1_STICKY_ULP \|	1582	if ((phy_reg & I218_ULP_CONFIG1_IND) \|\| force) {
1518	I218_ULP_CONFIG1_RESET_TO_SMBUS \|	1583	phy_reg &= ~(I218_ULP_CONFIG1_IND \|
1519	I218_ULP_CONFIG1_WOL_HOST \|	1584	I218_ULP_CONFIG1_STICKY_ULP \|
1520	I218_ULP_CONFIG1_INBAND_EXIT \|	1585	I218_ULP_CONFIG1_RESET_TO_SMBUS \|
1521	I218_ULP_CONFIG1_EN_ULP_LANPHYPC \|	1586	I218_ULP_CONFIG1_WOL_HOST \|
1522	I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST \|	1587	I218_ULP_CONFIG1_INBAND_EXIT \|
1523	I218_ULP_CONFIG1_DISABLE_SMB_PERST);	1588	I218_ULP_CONFIG1_EN_ULP_LANPHYPC \|
1524	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);	1589	I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST \|
		1590	I218_ULP_CONFIG1_DISABLE_SMB_PERST);
		1591	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
		1592
		1593	/* Commit ULP changes by starting auto ULP configuration */
		1594	phy_reg \|= I218_ULP_CONFIG1_START;
		1595	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
		1596
		1597	/* Clear Disable SMBus Release on PERST# in MAC */
		1598	mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
		1599	mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
		1600	E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
		1601
		1602	if (!force) {
		1603	hw->phy.ops.release(hw);
		1604
		1605	if (hw->mac.autoneg)
		1606	e1000_phy_setup_autoneg(hw);
		1607	else
		1608	e1000_setup_copper_link_generic(hw);
1525		1609
1526	/* Commit ULP changes by starting auto ULP configuration */	1610	e1000_sw_lcd_config_ich8lan(hw);
1527	phy_reg \|= I218_ULP_CONFIG1_START;
1528	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1529		1611
1530	/* Clear Disable SMBus Release on PERST# in MAC */	1612	e1000_oem_bits_config_ich8lan(hw, true);
1531	mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);	1613
1532	mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;	1614	/* Set ULP state to unknown and return non-zero to
1533	E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);	1615	* indicate no link (yet) and re-enter on the next LSC
		1616	* to finish disabling ULP flow.
		1617	*/
		1618	hw->dev_spec.ich8lan.ulp_state =
		1619	e1000_ulp_state_unknown;
		1620
		1621	return 1;
		1622	}
		1623	}
		1624
		1625	/* Re-enable Tx */
		1626	mac_reg = E1000_READ_REG(hw, E1000_TCTL);
		1627	mac_reg \|= E1000_TCTL_EN;
		1628	E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1534		1629
1535	release:	1630	release:
1536	hw->phy.ops.release(hw);	1631	hw->phy.ops.release(hw);
Lines 1560-1566 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) Link Here
1560	struct e1000_mac_info *mac = &hw->mac;	1655	struct e1000_mac_info *mac = &hw->mac;
1561	s32 ret_val, tipg_reg = 0;	1656	s32 ret_val, tipg_reg = 0;
1562	u16 emi_addr, emi_val = 0;	1657	u16 emi_addr, emi_val = 0;
1563	bool link;	1658	bool link = false;
1564	u16 phy_reg;	1659	u16 phy_reg;
1565		1660
1566	DEBUGFUNC("e1000_check_for_copper_link_ich8lan");	1661	DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
Lines 1573-1585 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) Link Here
1573	if (!mac->get_link_status)	1668	if (!mac->get_link_status)
1574	return E1000_SUCCESS;	1669	return E1000_SUCCESS;
1575		1670
1576	/* First we want to see if the MII Status Register reports	1671	if ((hw->mac.type < e1000_pch_lpt) \|\|
1577	* link. If so, then we want to get the current speed/duplex	1672	(hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) \|\|
1578	* of the PHY.	1673	(hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1579	*/	1674	/* First we want to see if the MII Status Register reports
1580	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);	1675	* link. If so, then we want to get the current speed/duplex
1581	if (ret_val)	1676	* of the PHY.
1582	return ret_val;	1677	*/
		1678	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
		1679	if (ret_val)
		1680	return ret_val;
		1681	} else {
		1682	/* Check the MAC's STATUS register to determine link state
		1683	* since the PHY could be inaccessible while in ULP mode.
		1684	*/
		1685	link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
		1686	if (link)
		1687	ret_val = e1000_disable_ulp_lpt_lp(hw, false);
		1688	else
		1689	ret_val = e1000_enable_ulp_lpt_lp(hw, false);
		1690	if (ret_val)
		1691	return ret_val;
		1692	}
1583		1693
1584	if (hw->mac.type == e1000_pchlan) {	1694	if (hw->mac.type == e1000_pchlan) {
1585	ret_val = e1000_k1_gig_workaround_hv(hw, link);	1695	ret_val = e1000_k1_gig_workaround_hv(hw, link);
Lines 1728-1734 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) Link Here
1728	if (ret_val)	1838	if (ret_val)
1729	return ret_val;	1839	return ret_val;
1730	}	1840	}
1731
1732	/* Clear link partner's EEE ability */	1841	/* Clear link partner's EEE ability */
1733	hw->dev_spec.ich8lan.eee_lp_ability = 0;	1842	hw->dev_spec.ich8lan.eee_lp_ability = 0;
1734		1843
Lines 1749-1754 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) Link Here
1749	fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;	1858	fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1750		1859
1751	E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);	1860	E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
		1861
		1862	/* Configure K0s minimum time */
		1863	e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1752	}	1864	}
1753		1865
1754	if (!link)	1866	if (!link)
Lines 4316-4322 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) Link Here
4316	(u8)(data >> 8));	4428	(u8)(data >> 8));
4317	if (ret_val)	4429	if (ret_val)
4318	break;	4430	break;
4319	}	4431	}
4320		4432
4321	/* Don't bother writing the segment valid bits if sector	4433	/* Don't bother writing the segment valid bits if sector
4322	* programming failed.	4434	* programming failed.
Lines 6144-6146 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) Link Here
6144	}	6256	}
6145	}	6257	}
6146		6258
		6259	/**
		6260	* e1000_configure_k0s_lpt - Configure K0s power state
		6261	* @hw: pointer to the HW structure
		6262	* @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
		6263	* 0 corresponds to 128ns, each value over 0 doubles the duration.
		6264	* @min_time: Minimum Tx idle period allowed - valid values are 0 to 4.
		6265	* 0 corresponds to 128ns, each value over 0 doubles the duration.
		6266	*
		6267	* Configure the K1 power state based on the provided parameter.
		6268	* Assumes semaphore already acquired.
		6269	*
		6270	* Success returns 0, Failure returns:
		6271	* -E1000_ERR_PHY (-2) in case of access error
		6272	* -E1000_ERR_PARAM (-4) in case of parameters error
		6273	**/
		6274	s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
		6275	{
		6276	s32 ret_val;
		6277	u16 kmrn_reg = 0;
		6278
		6279	DEBUGFUNC("e1000_configure_k0s_lpt");
		6280
		6281	if (entry_latency > 3 \|\| min_time > 4)
		6282	return -E1000_ERR_PARAM;
		6283
		6284	ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
		6285	&kmrn_reg);
		6286	if (ret_val)
		6287	return ret_val;
		6288
		6289	/* for now don't touch the latency */
		6290	kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
		6291	kmrn_reg \|= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
		6292
		6293	ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
		6294	kmrn_reg);
		6295	if (ret_val)
		6296	return ret_val;
		6297
		6298	return E1000_SUCCESS;
		6299	}