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Lines 1-4
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| 1 |
/*- |
1 |
/* |
| 2 |
* SPDX-License-Identifier: BSD-4-Clause |
2 |
* SPDX-License-Identifier: BSD-4-Clause |
| 3 |
* |
3 |
* |
| 4 |
* Copyright (c) 2001 Wind River Systems |
4 |
* Copyright (c) 2001 Wind River Systems |
|
Lines 479-484
static void bge_sig_pre_reset(struct bge_softc *, int);
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| 479 |
static void bge_stop_fw(struct bge_softc *); |
479 |
static void bge_stop_fw(struct bge_softc *); |
| 480 |
static int bge_reset(struct bge_softc *); |
480 |
static int bge_reset(struct bge_softc *); |
| 481 |
static void bge_link_upd(struct bge_softc *); |
481 |
static void bge_link_upd(struct bge_softc *); |
|
|
482 |
static void bge_setwol(struct bge_softc *); |
| 483 |
static void bge_clrwol(struct bge_softc *); |
| 482 |
|
484 |
|
| 483 |
static void bge_ape_lock_init(struct bge_softc *); |
485 |
static void bge_ape_lock_init(struct bge_softc *); |
| 484 |
static void bge_ape_read_fw_ver(struct bge_softc *); |
486 |
static void bge_ape_read_fw_ver(struct bge_softc *); |
|
Lines 888-893
bge_ape_send_event(struct bge_softc *sc, uint32_t event)
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|
| 888 |
static void |
890 |
static void |
| 889 |
bge_ape_driver_state_change(struct bge_softc *sc, int kind) |
891 |
bge_ape_driver_state_change(struct bge_softc *sc, int kind) |
| 890 |
{ |
892 |
{ |
|
|
893 |
struct ifnet *ifp; |
| 891 |
uint32_t apedata, event; |
894 |
uint32_t apedata, event; |
| 892 |
|
895 |
|
| 893 |
if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) |
896 |
if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) |
|
Lines 920-927
bge_ape_driver_state_change(struct bge_softc *sc, int kind)
Link Here
|
| 920 |
event = BGE_APE_EVENT_STATUS_STATE_START; |
923 |
event = BGE_APE_EVENT_STATUS_STATE_START; |
| 921 |
break; |
924 |
break; |
| 922 |
case BGE_RESET_SHUTDOWN: |
925 |
case BGE_RESET_SHUTDOWN: |
| 923 |
APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, |
926 |
/* XXX Needs rewording |
| 924 |
BGE_APE_HOST_DRVR_STATE_UNLOAD); |
927 |
* With the interface we are currently using, |
|
|
928 |
* APE does not track driver state. Wiping |
| 929 |
* out the HOST SEGMENT SIGNATURE forces |
| 930 |
* the APE to assume OS absent status. |
| 931 |
*/ |
| 932 |
APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 0); |
| 933 |
|
| 934 |
ifp = sc->bge_ifp; |
| 935 |
if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { |
| 936 |
APE_WRITE_4(sc, BGE_APE_HOST_WOL_SPEED, |
| 937 |
BGE_APE_HOST_WOL_SPEED_AUTO); |
| 938 |
APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, |
| 939 |
BGE_APE_HOST_DRVR_STATE_WOL); |
| 940 |
} else { |
| 941 |
APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, |
| 942 |
BGE_APE_HOST_DRVR_STATE_UNLOAD); |
| 943 |
} |
| 925 |
event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; |
944 |
event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; |
| 926 |
break; |
945 |
break; |
| 927 |
case BGE_RESET_SUSPEND: |
946 |
case BGE_RESET_SUSPEND: |
|
Lines 3730-3736
bge_attach(device_t dev)
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| 3730 |
if_setsendqready(ifp); |
3749 |
if_setsendqready(ifp); |
| 3731 |
if_sethwassist(ifp, sc->bge_csum_features); |
3750 |
if_sethwassist(ifp, sc->bge_csum_features); |
| 3732 |
if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | |
3751 |
if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | |
| 3733 |
IFCAP_VLAN_MTU); |
3752 |
IFCAP_VLAN_MTU | IFCAP_WOL_MAGIC); |
| 3734 |
if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { |
3753 |
if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { |
| 3735 |
if_sethwassistbits(ifp, CSUM_TSO, 0); |
3754 |
if_sethwassistbits(ifp, CSUM_TSO, 0); |
| 3736 |
if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0); |
3755 |
if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0); |
|
Lines 3738-3743
bge_attach(device_t dev)
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| 3738 |
#ifdef IFCAP_VLAN_HWCSUM |
3757 |
#ifdef IFCAP_VLAN_HWCSUM |
| 3739 |
if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); |
3758 |
if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); |
| 3740 |
#endif |
3759 |
#endif |
|
|
3760 |
if (pci_find_cap(dev, PCIY_PMG, ®) == 0) |
| 3761 |
if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); |
| 3741 |
if_setcapenable(ifp, if_getcapabilities(ifp)); |
3762 |
if_setcapenable(ifp, if_getcapabilities(ifp)); |
| 3742 |
#ifdef DEVICE_POLLING |
3763 |
#ifdef DEVICE_POLLING |
| 3743 |
if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); |
3764 |
if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); |
|
Lines 3923-3928
bge_attach(device_t dev)
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| 3923 |
device_printf(sc->bge_dev, "couldn't set up irq\n"); |
3944 |
device_printf(sc->bge_dev, "couldn't set up irq\n"); |
| 3924 |
goto fail; |
3945 |
goto fail; |
| 3925 |
} |
3946 |
} |
|
|
3947 |
BGE_LOCK(sc); |
| 3948 |
bge_clrwol(sc); |
| 3949 |
BGE_UNLOCK(sc); |
| 3926 |
|
3950 |
|
| 3927 |
/* Attach driver debugnet methods. */ |
3951 |
/* Attach driver debugnet methods. */ |
| 3928 |
DEBUGNET_SET(ifp, bge); |
3952 |
DEBUGNET_SET(ifp, bge); |
|
Lines 3950-3955
bge_detach(device_t dev)
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| 3950 |
if (device_is_attached(dev)) { |
3974 |
if (device_is_attached(dev)) { |
| 3951 |
ether_ifdetach(ifp); |
3975 |
ether_ifdetach(ifp); |
| 3952 |
BGE_LOCK(sc); |
3976 |
BGE_LOCK(sc); |
|
|
3977 |
bge_setwol(sc); |
| 3953 |
bge_stop(sc); |
3978 |
bge_stop(sc); |
| 3954 |
BGE_UNLOCK(sc); |
3979 |
BGE_UNLOCK(sc); |
| 3955 |
callout_drain(&sc->bge_stat_ch); |
3980 |
callout_drain(&sc->bge_stat_ch); |
|
Lines 4137-4143
bge_reset(struct bge_softc *sc)
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| 4137 |
/* Reset some of the PCI state that got zapped by reset. */ |
4162 |
/* Reset some of the PCI state that got zapped by reset. */ |
| 4138 |
pci_write_config(dev, BGE_PCI_MISC_CTL, |
4163 |
pci_write_config(dev, BGE_PCI_MISC_CTL, |
| 4139 |
BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | |
4164 |
BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | |
| 4140 |
BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); |
4165 |
BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW | |
|
|
4166 |
BGE_PCIMISCCTL_CLOCKCTL_RW, 4); |
| 4141 |
val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; |
4167 |
val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; |
| 4142 |
if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && |
4168 |
if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && |
| 4143 |
(sc->bge_flags & BGE_FLAG_PCIX) != 0) |
4169 |
(sc->bge_flags & BGE_FLAG_PCIX) != 0) |
|
Lines 5841-5846
bge_ioctl(if_t ifp, u_long command, caddr_t data)
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| 5841 |
} |
5867 |
} |
| 5842 |
} |
5868 |
} |
| 5843 |
#endif |
5869 |
#endif |
|
|
5870 |
if ((mask & IFCAP_WOL_MAGIC) != 0 && |
| 5871 |
(if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) |
| 5872 |
if_togglecapenable(ifp, IFCAP_WOL_MAGIC); |
| 5844 |
if ((mask & IFCAP_TXCSUM) != 0 && |
5873 |
if ((mask & IFCAP_TXCSUM) != 0 && |
| 5845 |
(if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { |
5874 |
(if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { |
| 5846 |
if_togglecapenable(ifp, IFCAP_TXCSUM); |
5875 |
if_togglecapenable(ifp, IFCAP_TXCSUM); |
|
Lines 6068-6073
bge_shutdown(device_t dev)
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| 6068 |
|
6097 |
|
| 6069 |
sc = device_get_softc(dev); |
6098 |
sc = device_get_softc(dev); |
| 6070 |
BGE_LOCK(sc); |
6099 |
BGE_LOCK(sc); |
|
|
6100 |
bge_setwol(sc); |
| 6071 |
bge_stop(sc); |
6101 |
bge_stop(sc); |
| 6072 |
BGE_UNLOCK(sc); |
6102 |
BGE_UNLOCK(sc); |
| 6073 |
|
6103 |
|
|
Lines 6081-6086
bge_suspend(device_t dev)
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| 6081 |
|
6111 |
|
| 6082 |
sc = device_get_softc(dev); |
6112 |
sc = device_get_softc(dev); |
| 6083 |
BGE_LOCK(sc); |
6113 |
BGE_LOCK(sc); |
|
|
6114 |
bge_setwol(sc); |
| 6084 |
bge_stop(sc); |
6115 |
bge_stop(sc); |
| 6085 |
BGE_UNLOCK(sc); |
6116 |
BGE_UNLOCK(sc); |
| 6086 |
|
6117 |
|
|
Lines 6096-6106
bge_resume(device_t dev)
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| 6096 |
sc = device_get_softc(dev); |
6127 |
sc = device_get_softc(dev); |
| 6097 |
BGE_LOCK(sc); |
6128 |
BGE_LOCK(sc); |
| 6098 |
ifp = sc->bge_ifp; |
6129 |
ifp = sc->bge_ifp; |
|
|
6130 |
bge_reset(sc); |
| 6099 |
if (if_getflags(ifp) & IFF_UP) { |
6131 |
if (if_getflags(ifp) & IFF_UP) { |
| 6100 |
bge_init_locked(sc); |
6132 |
bge_init_locked(sc); |
| 6101 |
if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) |
6133 |
if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) |
| 6102 |
bge_start_locked(ifp); |
6134 |
bge_start_locked(ifp); |
| 6103 |
} |
6135 |
} |
|
|
6136 |
bge_clrwol(sc); |
| 6104 |
BGE_UNLOCK(sc); |
6137 |
BGE_UNLOCK(sc); |
| 6105 |
|
6138 |
|
| 6106 |
return (0); |
6139 |
return (0); |
|
Lines 6850-6852
bge_debugnet_poll(if_t ifp, int count)
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| 6850 |
return (0); |
6883 |
return (0); |
| 6851 |
} |
6884 |
} |
| 6852 |
#endif /* DEBUGNET */ |
6885 |
#endif /* DEBUGNET */ |
|
|
6886 |
|
| 6887 |
static void |
| 6888 |
bge_setwol(struct bge_softc *sc) |
| 6889 |
{ |
| 6890 |
struct ifnet *ifp; |
| 6891 |
uint32_t clk; |
| 6892 |
uint16_t pmstat; |
| 6893 |
int pmc; |
| 6894 |
|
| 6895 |
#ifdef BGE_WOL_DEBUG |
| 6896 |
device_printf(sc->bge_dev, "Entering bge WOL\n"); |
| 6897 |
#endif |
| 6898 |
ifp = sc->bge_ifp; |
| 6899 |
if ((if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) == 0) |
| 6900 |
return; |
| 6901 |
if (pci_find_cap(sc->bge_dev, PCIY_PMG, &pmc) != 0) |
| 6902 |
return; |
| 6903 |
if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { |
| 6904 |
#ifdef BGE_WOL_DEBUG |
| 6905 |
device_printf(sc->bge_dev, "Configuring bge WOL\n"); |
| 6906 |
#endif |
| 6907 |
bge_reset(sc); |
| 6908 |
BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_MAGIC_PKT_ENB); |
| 6909 |
BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_ACPI_PWRON_ENB); |
| 6910 |
BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); |
| 6911 |
BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); |
| 6912 |
BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); |
| 6913 |
clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) | |
| 6914 |
BGE_PCICLOCKCTL_RXCPU_CLK_DIS | |
| 6915 |
BGE_PCICLOCKCTL_ALTCLK | |
| 6916 |
BGE_PCICLOCKCTL_SYSPLL_DISABLE; |
| 6917 |
CSR_WRITE_4(sc, BGE_PCI_CLKCTL, clk); |
| 6918 |
} |
| 6919 |
else { |
| 6920 |
#ifdef BGE_WOL_DEBUG |
| 6921 |
device_printf(sc->bge_dev, "Bypassing bge WOL\n"); |
| 6922 |
#endif |
| 6923 |
BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_MAGIC_PKT_ENB); |
| 6924 |
BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_ACPI_PWRON_ENB); |
| 6925 |
} |
| 6926 |
|
| 6927 |
/* Request PME if WOL is requested. */ |
| 6928 |
pmstat = pci_read_config(sc->bge_dev, pmc + PCIR_POWER_STATUS, 2); |
| 6929 |
pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); |
| 6930 |
if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) |
| 6931 |
pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; |
| 6932 |
pci_write_config(sc->bge_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); |
| 6933 |
} |
| 6934 |
|
| 6935 |
static void |
| 6936 |
bge_clrwol(struct bge_softc *sc) |
| 6937 |
{ |
| 6938 |
struct ifnet *ifp; |
| 6939 |
uint16_t pmstat; |
| 6940 |
int pmc; |
| 6941 |
|
| 6942 |
ifp = sc->bge_ifp; |
| 6943 |
if ((if_getcapabilities(ifp) & IFCAP_WOL) == 0) |
| 6944 |
return; |
| 6945 |
if (pci_find_cap(sc->bge_dev, PCIY_PMG, &pmc) != 0) |
| 6946 |
return; |
| 6947 |
if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) |
| 6948 |
return; |
| 6949 |
BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_MAGIC_PKT_ENB); |
| 6950 |
BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_ACPI_PWRON_ENB); |
| 6951 |
|
| 6952 |
pmstat = pci_read_config(sc->bge_dev, pmc + PCIR_POWER_STATUS, 2); |
| 6953 |
pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); |
| 6954 |
pci_write_config(sc->bge_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); |
| 6955 |
} |