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Lines 141-146
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| 141 |
"Broadcom BCM5701 Gigabit Ethernet" }, |
141 |
"Broadcom BCM5701 Gigabit Ethernet" }, |
| 142 |
{ BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, |
142 |
{ BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, |
| 143 |
"Broadcom BCM5702X Gigabit Ethernet" }, |
143 |
"Broadcom BCM5702X Gigabit Ethernet" }, |
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|
144 |
{ BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, |
| 145 |
"Broadcom BCM5703X Gigabit Ethernet" }, |
| 144 |
{ SK_VENDORID, SK_DEVICEID_ALTIMA, |
146 |
{ SK_VENDORID, SK_DEVICEID_ALTIMA, |
| 145 |
"SysKonnect Gigabit Ethernet" }, |
147 |
"SysKonnect Gigabit Ethernet" }, |
| 146 |
{ ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, |
148 |
{ ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, |
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Lines 484-491
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| 484 |
sc = device_get_softc(dev); |
486 |
sc = device_get_softc(dev); |
| 485 |
ifp = &sc->arpcom.ac_if; |
487 |
ifp = &sc->arpcom.ac_if; |
| 486 |
|
488 |
|
| 487 |
if (sc->bge_asicrev == BGE_ASICREV_BCM5701_B5 && phy != 1) |
489 |
if (phy != 1) |
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|
490 |
switch(sc->bge_asicrev) { |
| 491 |
case BGE_ASICREV_BCM5701_B5: |
| 492 |
case BGE_ASICREV_BCM5703_A2: |
| 488 |
return(0); |
493 |
return(0); |
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|
494 |
} |
| 489 |
|
495 |
|
| 490 |
CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| |
496 |
CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| |
| 491 |
BGE_MIPHY(phy)|BGE_MIREG(reg)); |
497 |
BGE_MIPHY(phy)|BGE_MIREG(reg)); |
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Lines 1040-1046
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| 1040 |
bge_chipinit(sc) |
1046 |
bge_chipinit(sc) |
| 1041 |
struct bge_softc *sc; |
1047 |
struct bge_softc *sc; |
| 1042 |
{ |
1048 |
{ |
| 1043 |
u_int32_t cachesize; |
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|
| 1044 |
int i; |
1049 |
int i; |
| 1045 |
|
1050 |
|
| 1046 |
/* Set endianness before we access any non-PCI registers. */ |
1051 |
/* Set endianness before we access any non-PCI registers. */ |
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Lines 1098-1150
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| 1098 |
BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| |
1103 |
BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| |
| 1099 |
BGE_MODECTL_RX_NO_PHDR_CSUM); |
1104 |
BGE_MODECTL_RX_NO_PHDR_CSUM); |
| 1100 |
|
1105 |
|
| 1101 |
/* Get cache line size. */ |
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|
| 1102 |
cachesize = pci_read_config(sc->bge_dev, BGE_PCI_CACHESZ, 1); |
| 1103 |
|
| 1104 |
/* |
1106 |
/* |
| 1105 |
* Avoid violating PCI spec on certain chip revs. |
1107 |
* Disable memory write invalidate. Apparently it is not supported |
|
|
1108 |
* properly by these devices. |
| 1106 |
*/ |
1109 |
*/ |
| 1107 |
if (pci_read_config(sc->bge_dev, BGE_PCI_CMD, 4) & PCIM_CMD_MWIEN) { |
1110 |
PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); |
| 1108 |
switch(cachesize) { |
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|
| 1109 |
case 1: |
| 1110 |
PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, |
| 1111 |
BGE_PCI_WRITE_BNDRY_16BYTES, 4); |
| 1112 |
break; |
| 1113 |
case 2: |
| 1114 |
PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, |
| 1115 |
BGE_PCI_WRITE_BNDRY_32BYTES, 4); |
| 1116 |
break; |
| 1117 |
case 4: |
| 1118 |
PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, |
| 1119 |
BGE_PCI_WRITE_BNDRY_64BYTES, 4); |
| 1120 |
break; |
| 1121 |
case 8: |
| 1122 |
PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, |
| 1123 |
BGE_PCI_WRITE_BNDRY_128BYTES, 4); |
| 1124 |
break; |
| 1125 |
case 16: |
| 1126 |
PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, |
| 1127 |
BGE_PCI_WRITE_BNDRY_256BYTES, 4); |
| 1128 |
break; |
| 1129 |
case 32: |
| 1130 |
PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, |
| 1131 |
BGE_PCI_WRITE_BNDRY_512BYTES, 4); |
| 1132 |
break; |
| 1133 |
case 64: |
| 1134 |
PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, |
| 1135 |
BGE_PCI_WRITE_BNDRY_1024BYTES, 4); |
| 1136 |
break; |
| 1137 |
default: |
| 1138 |
/* Disable PCI memory write and invalidate. */ |
| 1139 |
if (bootverbose) |
| 1140 |
printf("bge%d: cache line size %d not " |
| 1141 |
"supported; disabling PCI MWI\n", |
| 1142 |
sc->bge_unit, cachesize); |
| 1143 |
PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, |
| 1144 |
PCIM_CMD_MWIEN, 4); |
| 1145 |
break; |
| 1146 |
} |
| 1147 |
} |
| 1148 |
|
1111 |
|
| 1149 |
#ifdef __brokenalpha__ |
1112 |
#ifdef __brokenalpha__ |
| 1150 |
/* |
1113 |
/* |
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Lines 1153-1159
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| 1153 |
* restriction on some ALPHA platforms with early revision |
1116 |
* restriction on some ALPHA platforms with early revision |
| 1154 |
* 21174 PCI chipsets, such as the AlphaPC 164lx |
1117 |
* 21174 PCI chipsets, such as the AlphaPC 164lx |
| 1155 |
*/ |
1118 |
*/ |
| 1156 |
PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); |
1119 |
PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, |
|
|
1120 |
BGE_PCI_READ_BNDRY_1024BYTES, 4); |
| 1157 |
#endif |
1121 |
#endif |
| 1158 |
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1122 |
|
| 1159 |
/* Set the timer prescaler (always 66Mhz) */ |
1123 |
/* Set the timer prescaler (always 66Mhz) */ |
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Lines 1556-1561
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| 1556 |
struct ifnet *ifp; |
1520 |
struct ifnet *ifp; |
| 1557 |
struct bge_softc *sc; |
1521 |
struct bge_softc *sc; |
| 1558 |
u_int32_t hwcfg = 0; |
1522 |
u_int32_t hwcfg = 0; |
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|
1523 |
u_int32_t mac_addr = 0; |
| 1559 |
int unit, error = 0, rid; |
1524 |
int unit, error = 0, rid; |
| 1560 |
|
1525 |
|
| 1561 |
s = splimp(); |
1526 |
s = splimp(); |
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Lines 1581-1587
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| 1581 |
|
1546 |
|
| 1582 |
rid = BGE_PCI_BAR0; |
1547 |
rid = BGE_PCI_BAR0; |
| 1583 |
sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, |
1548 |
sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, |
| 1584 |
0, ~0, 1, RF_ACTIVE); |
1549 |
0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); |
| 1585 |
|
1550 |
|
| 1586 |
if (sc->bge_res == NULL) { |
1551 |
if (sc->bge_res == NULL) { |
| 1587 |
printf ("bge%d: couldn't map memory\n", unit); |
1552 |
printf ("bge%d: couldn't map memory\n", unit); |
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Lines 1593-1614
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| 1593 |
sc->bge_bhandle = rman_get_bushandle(sc->bge_res); |
1558 |
sc->bge_bhandle = rman_get_bushandle(sc->bge_res); |
| 1594 |
sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); |
1559 |
sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); |
| 1595 |
|
1560 |
|
| 1596 |
/* |
|
|
| 1597 |
* XXX FIXME: rman_get_virtual() on the alpha is currently |
| 1598 |
* broken and returns a physical address instead of a kernel |
| 1599 |
* virtual address. Consequently, we need to do a little |
| 1600 |
* extra mangling of the vhandle on the alpha. This should |
| 1601 |
* eventually be fixed! The whole idea here is to get rid |
| 1602 |
* of platform dependencies. |
| 1603 |
*/ |
| 1604 |
#ifdef __alpha__ |
| 1605 |
if (pci_cvt_to_bwx(sc->bge_vhandle)) |
| 1606 |
sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle); |
| 1607 |
else |
| 1608 |
sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle); |
| 1609 |
sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle); |
| 1610 |
#endif |
| 1611 |
|
| 1612 |
/* Allocate interrupt */ |
1561 |
/* Allocate interrupt */ |
| 1613 |
rid = 0; |
1562 |
rid = 0; |
| 1614 |
|
1563 |
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Lines 1645-1651
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| 1645 |
/* |
1594 |
/* |
| 1646 |
* Get station address from the EEPROM. |
1595 |
* Get station address from the EEPROM. |
| 1647 |
*/ |
1596 |
*/ |
| 1648 |
if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, |
1597 |
mac_addr = bge_readmem_ind(sc, 0x0c14); |
|
|
1598 |
if ((mac_addr >> 16) == 0x484b) { |
| 1599 |
sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); |
| 1600 |
sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; |
| 1601 |
mac_addr = bge_readmem_ind(sc, 0x0c18); |
| 1602 |
sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); |
| 1603 |
sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); |
| 1604 |
sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); |
| 1605 |
sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; |
| 1606 |
} else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, |
| 1649 |
BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { |
1607 |
BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { |
| 1650 |
printf("bge%d: failed to read station address\n", unit); |
1608 |
printf("bge%d: failed to read station address\n", unit); |
| 1651 |
bge_release_resources(sc); |
1609 |
bge_release_resources(sc); |