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Lines 269-274
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| 269 |
/* Enable the TLB and flush */ |
269 |
/* Enable the TLB and flush */ |
| 270 |
WRITE2(AGP_AMD751_STATUS, |
270 |
WRITE2(AGP_AMD751_STATUS, |
| 271 |
READ2(AGP_AMD751_STATUS) | AGP_AMD751_STATUS_GCE); |
271 |
READ2(AGP_AMD751_STATUS) | AGP_AMD751_STATUS_GCE); |
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272 |
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| 273 |
/* Setting bit 0 is required for the size to be valid. */ |
| 274 |
pci_write_config(dev, |
| 275 |
AGP_AMD751_APCTRL, |
| 276 |
pci_read_config(dev, AGP_AMD751_APCTRL, 1) | 1, 1); |
| 277 |
|
| 272 |
AGP_FLUSH_TLB(dev); |
278 |
AGP_FLUSH_TLB(dev); |
| 273 |
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279 |
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| 274 |
return 0; |
280 |
return 0; |
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Lines 313-319
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| 313 |
/* |
319 |
/* |
| 314 |
* The aperture size is equal to 32M<<vas. |
320 |
* The aperture size is equal to 32M<<vas. |
| 315 |
*/ |
321 |
*/ |
| 316 |
vas = (pci_read_config(dev, AGP_AMD751_APCTRL, 1) & 0x06) >> 1; |
322 |
vas = (pci_read_config(dev, AGP_AMD751_APCTRL, 1) & 0x0e) >> 1; |
| 317 |
return (32*1024*1024) << vas; |
323 |
return (32*1024*1024) << vas; |
| 318 |
} |
324 |
} |
| 319 |
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325 |
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Lines 321-326
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| 321 |
agp_amd_set_aperture(device_t dev, u_int32_t aperture) |
327 |
agp_amd_set_aperture(device_t dev, u_int32_t aperture) |
| 322 |
{ |
328 |
{ |
| 323 |
int vas; |
329 |
int vas; |
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|
330 |
u_int32_t apctrl; |
| 324 |
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331 |
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| 325 |
/* |
332 |
/* |
| 326 |
* Check for a power of two and make sure its within the |
333 |
* Check for a power of two and make sure its within the |
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Lines 331-345
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| 331 |
|| aperture > 2U*1024*1024*1024) |
338 |
|| aperture > 2U*1024*1024*1024) |
| 332 |
return EINVAL; |
339 |
return EINVAL; |
| 333 |
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340 |
|
| 334 |
vas = ffs(aperture / 32*1024*1024) - 1; |
341 |
vas = ffs(aperture / (32*1024*1024)) - 1; |
| 335 |
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342 |
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| 336 |
/* |
343 |
/* |
| 337 |
* While the size register is bits 1-3 of APCTRL, bit 0 must be |
344 |
* While the size register is bits 1-3 of APCTRL, bit 0 must be |
| 338 |
* set for the size value to be 'valid' |
345 |
* set for the size value to be 'valid' |
| 339 |
*/ |
346 |
*/ |
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|
347 |
apctrl = pci_read_config(dev, AGP_AMD751_APCTRL, 1); |
| 340 |
pci_write_config(dev, AGP_AMD751_APCTRL, |
348 |
pci_write_config(dev, AGP_AMD751_APCTRL, |
| 341 |
(((pci_read_config(dev, AGP_AMD751_APCTRL, 1) & ~0x06) |
349 |
(apctrl & ~0x0e) | (vas << 1) | 1, 1); |
| 342 |
| ((vas << 1) | 1))), 1); |
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| 343 |
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350 |
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| 344 |
return 0; |
351 |
return 0; |
| 345 |
} |
352 |
} |