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# |
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PORTNAME= iverilog |
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PORTNAME= iverilog |
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PORTVERSION= 0.7.20031202 |
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PORTVERSION= 0.7.20040220 |
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PORTREVISION= 1 |
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PORTREVISION= 1 |
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CATEGORIES= cad |
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CATEGORIES= cad |
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MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/ |
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MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/ |
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DISTNAME= verilog-20031202 |
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DISTNAME= verilog-20040220 |
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MAINTAINER= watchman@ludd.luth.se |
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MAINTAINER= watchman@ludd.luth.se |
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COMMENT= A Verilog simulation and synthesis tool |
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COMMENT= A Verilog simulation and synthesis tool |