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Lines 733-739
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| 733 |
DELAY(100); |
733 |
DELAY(100); |
| 734 |
} |
734 |
} |
| 735 |
|
735 |
|
| 736 |
BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB); |
736 |
/* Enable CRC32 generation and set proper LED modes */ |
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|
737 |
BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); |
| 738 |
|
| 739 |
/* Reset/Clear powerdown bit */ |
| 740 |
BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); |
| 741 |
|
| 737 |
CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & |
742 |
CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & |
| 738 |
BFE_LAZY_FC_MASK)); |
743 |
BFE_LAZY_FC_MASK)); |
| 739 |
|
744 |
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Lines 835-841
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| 835 |
(((u_int32_t) data[1]))); |
840 |
(((u_int32_t) data[1]))); |
| 836 |
CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); |
841 |
CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); |
| 837 |
CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | |
842 |
CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | |
| 838 |
(index << BFE_CAM_INDEX_SHIFT))); |
843 |
((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); |
| 839 |
bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); |
844 |
bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); |
| 840 |
} |
845 |
} |
| 841 |
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846 |
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