Attachment #53126 for bug #80396




#define READ1(off)	bus_space_read_1(sc->bst, sc->bsh, off)
#define READ4(off)	bus_space_read_4(sc->bst, sc->bsh, off)
#define WRITE4(off,v)	bus_space_write_4(sc->bst, sc->bsh, off, v)
#define WRITEGTT(off,v)	bus_space_write_4(sc->gtt_bst, sc->gtt_bsh, off, v)

#define CHIP_I810 0	/* i810/i815 */
#define CHIP_I830 1	/* 830M/845G */
#define CHIP_I855 2	/* 852GM/855GM/865G */
#define CHIP_I915 3	/* 915G */

struct agp_i810_softc {
	struct agp_softc agp;

	u_int32_t dcache_size;		/* i810 only */
	u_int32_t stolen;		/* number of i830/845 gtt entries for stolen memory */
	device_t bdev;			/* bridge device */

	struct resource *regs;		/* memory mapped GC registers */
	bus_space_tag_t bst;		/* bus_space tag */
	bus_space_handle_t bsh;		/* bus_space handle */

	struct resource *gtt;		/* memory mapped GATT entries */
	bus_space_tag_t gtt_bst;	/* bus_space tag */
	bus_space_handle_t gtt_bsh;	/* bus_space handle */
};

static const char*


	case 0x25728086:
		return ("Intel 82865G (865G GMCH) SVGA controller");

	case 0x25828086:
		return ("Intel 82915G (915G GMCH) SVGA controller");
	};

	return NULL;

	case 0x25628086:
	case 0x35828086:
	case 0x25728086:
	case 0x25828086:
		devid -= 0x20000;
		break;
	};

		case 0x35828086:
		case 0x25628086:
		case 0x25728086:
		case 0x25828086:	/* XXX: Is this the right way? */
			gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
			if ((gcc1 & AGP_I830_GCC1_DEV2) == AGP_I830_GCC1_DEV2_DISABLED) {
				if (bootverbose)

	case 0x25728086:
		sc->chiptype = CHIP_I855;
		break;
	case 0x25828086:
		sc->chiptype = CHIP_I915;
		break;
	};

	/* Same for i810 and i830 */
	if (sc->chiptype == CHIP_I915)
		rid = AGP_I915_MMADR;
	else
		rid = AGP_I810_MMADR;

	sc->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
					  RF_ACTIVE);
	if (!sc->regs) {
		agp_generic_detach(dev);
		return ENODEV;
	}
	sc->bst = rman_get_bustag(sc->regs);
	sc->bsh = rman_get_bushandle(sc->regs);

	if (sc->chiptype == CHIP_I915) {
		rid = AGP_I915_GTTADR;
		sc->gtt = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
						 RF_ACTIVE);
		if (!sc->gtt) {
			bus_release_resource(dev, SYS_RES_MEMORY,
					     AGP_I810_MMADR, sc->regs);
			agp_generic_detach(dev);
			return ENODEV;
		}
		sc->gtt_bst = rman_get_bustag(sc->regs);
		sc->gtt_bsh = rman_get_bushandle(sc->regs);
	}

	sc->initial_aperture = AGP_GET_APERTURE(dev);

	gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT);

		WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);

		gatt->ag_physical = pgtblctl & ~1;
	} else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915) {	/* CHIP_I855 */
		/* The i855 automatically initializes the 128k gatt on boot. */
		unsigned int gcc1, pgtblctl;
		

			case AGP_I855_GCC1_GMS_STOLEN_32M: 
				sc->stolen = (32768 - 132) * 1024 / 4096;
				break;
			case AGP_I915_GCC1_GMS_STOLEN_48M: 
				sc->stolen = (49152 - 132) * 1024 / 4096;
				break;
			case AGP_I915_GCC1_GMS_STOLEN_64M: 
				sc->stolen = (65536 - 132) * 1024 / 4096;
				break;
			default:
				sc->stolen = 0;
				device_printf(dev, "unknown memory configuration, disabling\n");

	}
	free(sc->gatt, M_AGP);

	if (sc->chiptype == CHIP_I915) {
		bus_release_resource(dev, SYS_RES_MEMORY,
				     AGP_I915_GTTADR, sc->regs);
		bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_MMADR,
				     sc->regs);
	} else {
		bus_release_resource(dev, SYS_RES_MEMORY, AGP_I810_MMADR,
				     sc->regs);
	}

	child = device_find_child( dev, "drmsub", 0 );
	if (child)

agp_i810_get_aperture(device_t dev)
{
	struct agp_i810_softc *sc = device_get_softc(dev);
	uint32_t temp;
	u_int16_t miscc;

	switch (sc->chiptype) {
	case CHIP_I810:
		miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
		if ((miscc & AGP_I810_MISCC_WINSIZE) == AGP_I810_MISCC_WINSIZE_32)
			return 32 * 1024 * 1024;
		else
			return 64 * 1024 * 1024;
	case CHIP_I830:
		temp = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
		if ((temp & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
		gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
		if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
			return 64 * 1024 * 1024;
		else
			return 128 * 1024 * 1024;
	case CHIP_I855:
		return 128 * 1024 * 1024;
	case CHIP_I915:
		temp = pci_read_config(sc->bdev, AGP_I915_GMADR, 4);
		if (temp & (1 << 27)) {
			return 128 * 1024 * 1024;
		} else {
			return 256 * 1024 * 1024;
		}
	}

	return 0;
}

static int
agp_i810_set_aperture(device_t dev, u_int32_t aperture)
{
	struct agp_i810_softc *sc = device_get_softc(dev);
	u_int16_t miscc, gcc1;
	u_int32_t temp;

	switch (sc->chiptype) {
	case CHIP_I810:
		/*
		 * Double check for sanity.
		 */

			device_printf(dev, "bad aperture size %d\n", aperture);
			return EINVAL;
		}

		miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
		miscc &= ~AGP_I810_MISCC_WINSIZE;
		if (aperture == 32 * 1024 * 1024)

			miscc |= AGP_I810_MISCC_WINSIZE_64;
	
		pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
		break;
	case CHIP_I830:
		if (aperture != 64 * 1024 * 1024 &&
		    aperture != 128 * 1024 * 1024) {
			device_printf(dev, "bad aperture size %d\n", aperture);
			return EINVAL;
		}

			gcc1 |= AGP_I830_GCC1_GMASIZE_128;

		pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
		break;
	case CHIP_I855:
		if (aperture != 128 * 1024 * 1024) {
			device_printf(dev, "bad aperture size %d\n", aperture);
			return EINVAL;
		}
		break;
	case CHIP_I915:
		temp = pci_read_config(sc->bdev, AGP_I915_GMADR, 4);

		switch (aperture) {
		case 128 * 1024 * 1024:
			temp |= (1 << 27);
			break;
		case 256 * 1024 * 1024:
			temp &= ~(1 << 27);
			break;
		default:
			device_printf(dev, "bad aperture size %d\n", aperture);
			return EINVAL;
		}

		pci_write_config(sc->bdev, AGP_I915_GMADR, temp, 4);
		break;
	}

	return 0;

		}
	}

	if (sc->chiptype == CHIP_I915) {
		WRITEGTT(offset >> AGP_PAGE_SHIFT, physical | 1);
	} else {
		WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, physical | 1);
	}

	return 0;
}


		}
	}

	if (sc->chiptype == CHIP_I915) {
		WRITE4(offset >> AGP_PAGE_SHIFT, 0);
	} else {
		WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, 0);
	}
	
	return 0;
}


		return EINVAL;

	for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
		WRITE4(AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4,
		       offset | 3);
	}

	return 0;

Lines 233-238 Link Here

(-)agpreg.h (+9 lines)
233	#define AGP_I852_GM 0x5	233	#define AGP_I852_GM 0x5
234		234
235	/*	235	/*
		236	* 915G registers
		237	*/
		238	#define AGP_I915_GMADR 0x18
		239	#define AGP_I915_MMADR 0x10
		240	#define AGP_I915_GTTADR 0x1C
		241	#define AGP_I915_GCC1_GMS_STOLEN_48M 0x60
		242	#define AGP_I915_GCC1_GMS_STOLEN_64M 0x70
		243
		244	/*
236	* NVIDIA nForce/nForce2 registers	245	* NVIDIA nForce/nForce2 registers
237	*/	246	*/
238	#define AGP_NVIDIA_0_APBASE 0x10	247	#define AGP_NVIDIA_0_APBASE 0x10

Return to bug 80396

Lines 65-74 Link Here

(-)agp_i810.c (-25 / +111 lines)
65	#define READ1(off) bus_space_read_1(sc->bst, sc->bsh, off)	65	#define READ1(off) bus_space_read_1(sc->bst, sc->bsh, off)
66	#define READ4(off) bus_space_read_4(sc->bst, sc->bsh, off)	66	#define READ4(off) bus_space_read_4(sc->bst, sc->bsh, off)
67	#define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v)	67	#define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v)
		68	#define WRITEGTT(off,v) bus_space_write_4(sc->gtt_bst, sc->gtt_bsh, off, v)
68		69
69	#define CHIP_I810 0 /* i810/i815 */	70	#define CHIP_I810 0 /* i810/i815 */
70	#define CHIP_I830 1 /* 830M/845G */	71	#define CHIP_I830 1 /* 830M/845G */
71	#define CHIP_I855 2 /* 852GM/855GM/865G */	72	#define CHIP_I855 2 /* 852GM/855GM/865G */
		73	#define CHIP_I915 3 /* 915G */
72		74
73	struct agp_i810_softc {	75	struct agp_i810_softc {
74	struct agp_softc agp;	76	struct agp_softc agp;
Lines 78-86 Link Here
78	u_int32_t dcache_size; /* i810 only */	80	u_int32_t dcache_size; /* i810 only */
79	u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */	81	u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */
80	device_t bdev; /* bridge device */	82	device_t bdev; /* bridge device */
		83
81	struct resource regs; / memory mapped GC registers */	84	struct resource regs; / memory mapped GC registers */
82	bus_space_tag_t bst; /* bus_space tag */	85	bus_space_tag_t bst; /* bus_space tag */
83	bus_space_handle_t bsh; /* bus_space handle */	86	bus_space_handle_t bsh; /* bus_space handle */
		87
		88	struct resource gtt; / memory mapped GATT entries */
		89	bus_space_tag_t gtt_bst; /* bus_space tag */
		90	bus_space_handle_t gtt_bsh; /* bus_space handle */
84	};	91	};
85		92
86	static const char*	93	static const char*
Lines 129-134 Link Here
129		136
130	case 0x25728086:	137	case 0x25728086:
131	return ("Intel 82865G (865G GMCH) SVGA controller");	138	return ("Intel 82865G (865G GMCH) SVGA controller");
		139
		140	case 0x25828086:
		141	return ("Intel 82915G (915G GMCH) SVGA controller");
132	};	142	};
133		143
134	return NULL;	144	return NULL;
Lines 160-165 Link Here
160	case 0x25628086:	170	case 0x25628086:
161	case 0x35828086:	171	case 0x35828086:
162	case 0x25728086:	172	case 0x25728086:
		173	case 0x25828086:
163	devid -= 0x20000;	174	devid -= 0x20000;
164	break;	175	break;
165	};	176	};
Lines 222-227 Link Here
222	case 0x35828086:	233	case 0x35828086:
223	case 0x25628086:	234	case 0x25628086:
224	case 0x25728086:	235	case 0x25728086:
		236	case 0x25828086: /* XXX: Is this the right way? */
225	gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);	237	gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
226	if ((gcc1 & AGP_I830_GCC1_DEV2) == AGP_I830_GCC1_DEV2_DISABLED) {	238	if ((gcc1 & AGP_I830_GCC1_DEV2) == AGP_I830_GCC1_DEV2_DISABLED) {
227	if (bootverbose)	239	if (bootverbose)
Lines 272-290 Link Here
272	case 0x25728086:	284	case 0x25728086:
273	sc->chiptype = CHIP_I855;	285	sc->chiptype = CHIP_I855;
274	break;	286	break;
		287	case 0x25828086:
		288	sc->chiptype = CHIP_I915;
		289	break;
275	};	290	};
276		291
277	/* Same for i810 and i830 */	292	/* Same for i810 and i830 */
278	rid = AGP_I810_MMADR;	293	if (sc->chiptype == CHIP_I915)
		294	rid = AGP_I915_MMADR;
		295	else
		296	rid = AGP_I810_MMADR;
		297
279	sc->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,	298	sc->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
280	RF_ACTIVE);	299	RF_ACTIVE);
281	if (!sc->regs) {	300	if (!sc->regs) {
282	agp_generic_detach(dev);	301	agp_generic_detach(dev);
283	return ENOMEM;	302	return ENODEV;
284	}	303	}
285	sc->bst = rman_get_bustag(sc->regs);	304	sc->bst = rman_get_bustag(sc->regs);
286	sc->bsh = rman_get_bushandle(sc->regs);	305	sc->bsh = rman_get_bushandle(sc->regs);
287		306
		307	if (sc->chiptype == CHIP_I915) {
		308	rid = AGP_I915_GTTADR;
		309	sc->gtt = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
		310	RF_ACTIVE);
		311	if (!sc->gtt) {
		312	bus_release_resource(dev, SYS_RES_MEMORY,
		313	AGP_I810_MMADR, sc->regs);
		314	agp_generic_detach(dev);
		315	return ENODEV;
		316	}
		317	sc->gtt_bst = rman_get_bustag(sc->regs);
		318	sc->gtt_bsh = rman_get_bushandle(sc->regs);
		319	}
		320
288	sc->initial_aperture = AGP_GET_APERTURE(dev);	321	sc->initial_aperture = AGP_GET_APERTURE(dev);
289		322
290	gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT);	323	gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT);
Lines 350-356 Link Here
350	WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);	383	WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
351		384
352	gatt->ag_physical = pgtblctl & ~1;	385	gatt->ag_physical = pgtblctl & ~1;
353	} else { /* CHIP_I855 */	386	} else if (sc->chiptype == CHIP_I855 \|\| sc->chiptype == CHIP_I915) { /* CHIP_I855 */
354	/* The i855 automatically initializes the 128k gatt on boot. */	387	/* The i855 automatically initializes the 128k gatt on boot. */
355	unsigned int gcc1, pgtblctl;	388	unsigned int gcc1, pgtblctl;
356		389
Lines 371-376 Link Here
371	case AGP_I855_GCC1_GMS_STOLEN_32M:	404	case AGP_I855_GCC1_GMS_STOLEN_32M:
372	sc->stolen = (32768 - 132) * 1024 / 4096;	405	sc->stolen = (32768 - 132) * 1024 / 4096;
373	break;	406	break;
		407	case AGP_I915_GCC1_GMS_STOLEN_48M:
		408	sc->stolen = (49152 - 132) * 1024 / 4096;
		409	break;
		410	case AGP_I915_GCC1_GMS_STOLEN_64M:
		411	sc->stolen = (65536 - 132) * 1024 / 4096;
		412	break;
374	default:	413	default:
375	sc->stolen = 0;	414	sc->stolen = 0;
376	device_printf(dev, "unknown memory configuration, disabling\n");	415	device_printf(dev, "unknown memory configuration, disabling\n");
Lines 425-432 Link Here
425	}	464	}
426	free(sc->gatt, M_AGP);	465	free(sc->gatt, M_AGP);
427		466
428	bus_release_resource(dev, SYS_RES_MEMORY,	467	if (sc->chiptype == CHIP_I915) {
429	AGP_I810_MMADR, sc->regs);	468	bus_release_resource(dev, SYS_RES_MEMORY,
		469	AGP_I915_GTTADR, sc->regs);
		470	bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_MMADR,
		471	sc->regs);
		472	} else {
		473	bus_release_resource(dev, SYS_RES_MEMORY, AGP_I810_MMADR,
		474	sc->regs);
		475	}
430		476
431	child = device_find_child( dev, "drmsub", 0 );	477	child = device_find_child( dev, "drmsub", 0 );
432	if (child)	478	if (child)
Lines 439-472 Link Here
439	agp_i810_get_aperture(device_t dev)	485	agp_i810_get_aperture(device_t dev)
440	{	486	{
441	struct agp_i810_softc *sc = device_get_softc(dev);	487	struct agp_i810_softc *sc = device_get_softc(dev);
		488	uint32_t temp;
		489	u_int16_t miscc;
442		490
443	if ( sc->chiptype == CHIP_I810 ) {	491	switch (sc->chiptype) {
444	u_int16_t miscc;	492	case CHIP_I810:
445	miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);	493	miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
446	if ((miscc & AGP_I810_MISCC_WINSIZE) == AGP_I810_MISCC_WINSIZE_32)	494	if ((miscc & AGP_I810_MISCC_WINSIZE) == AGP_I810_MISCC_WINSIZE_32)
447	return 32 * 1024 * 1024;	495	return 32 * 1024 * 1024;
448	else	496	else
449	return 64 * 1024 * 1024;	497	return 64 * 1024 * 1024;
450	} else if ( sc->chiptype == CHIP_I830 ) {	498	case CHIP_I830:
451	unsigned int gcc1;	499	temp = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
452		500	if ((temp & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
453	gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
454	if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
455	return 64 * 1024 * 1024;	501	return 64 * 1024 * 1024;
456	else	502	else
457	return 128 * 1024 * 1024;	503	return 128 * 1024 * 1024;
458	} else { /* CHIP_I855 */	504	case CHIP_I855:
459	return 128 * 1024 * 1024;	505	return 128 * 1024 * 1024;
		506	case CHIP_I915:
		507	temp = pci_read_config(sc->bdev, AGP_I915_GMADR, 4);
		508	if (temp & (1 << 27)) {
		509	return 128 * 1024 * 1024;
		510	} else {
		511	return 256 * 1024 * 1024;
		512	}
460	}	513	}
		514
		515	return 0;
461	}	516	}
462		517
463	static int	518	static int
464	agp_i810_set_aperture(device_t dev, u_int32_t aperture)	519	agp_i810_set_aperture(device_t dev, u_int32_t aperture)
465	{	520	{
466	struct agp_i810_softc *sc = device_get_softc(dev);	521	struct agp_i810_softc *sc = device_get_softc(dev);
467	u_int16_t miscc;	522	u_int16_t miscc, gcc1;
		523	u_int32_t temp;
468		524
469	if ( sc->chiptype == CHIP_I810 ) {	525	switch (sc->chiptype) {
		526	case CHIP_I810:
470	/*	527	/*
471	* Double check for sanity.	528	* Double check for sanity.
472	*/	529	*/
Lines 474-480 Link Here
474	device_printf(dev, "bad aperture size %d\n", aperture);	531	device_printf(dev, "bad aperture size %d\n", aperture);
475	return EINVAL;	532	return EINVAL;
476	}	533	}
477		534
478	miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);	535	miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
479	miscc &= ~AGP_I810_MISCC_WINSIZE;	536	miscc &= ~AGP_I810_MISCC_WINSIZE;
480	if (aperture == 32 * 1024 * 1024)	537	if (aperture == 32 * 1024 * 1024)
Lines 483-492 Link Here
483	miscc \|= AGP_I810_MISCC_WINSIZE_64;	540	miscc \|= AGP_I810_MISCC_WINSIZE_64;
484		541
485	pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);	542	pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
486	} else if ( sc->chiptype == CHIP_I830 ) {	543	break;
487	unsigned int gcc1;	544	case CHIP_I830:
488		545	if (aperture != 64 * 1024 * 1024 &&
489	if (aperture != 64 * 1024 * 1024 && aperture != 128 * 1024 * 1024) {	546	aperture != 128 * 1024 * 1024) {
490	device_printf(dev, "bad aperture size %d\n", aperture);	547	device_printf(dev, "bad aperture size %d\n", aperture);
491	return EINVAL;	548	return EINVAL;
492	}	549	}
Lines 498-508 Link Here
498	gcc1 \|= AGP_I830_GCC1_GMASIZE_128;	555	gcc1 \|= AGP_I830_GCC1_GMASIZE_128;
499		556
500	pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);	557	pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
501	} else { /* CHIP_I855 */	558	break;
		559	case CHIP_I855:
502	if (aperture != 128 * 1024 * 1024) {	560	if (aperture != 128 * 1024 * 1024) {
503	device_printf(dev, "bad aperture size %d\n", aperture);	561	device_printf(dev, "bad aperture size %d\n", aperture);
504	return EINVAL;	562	return EINVAL;
505	}	563	}
		564	break;
		565	case CHIP_I915:
		566	temp = pci_read_config(sc->bdev, AGP_I915_GMADR, 4);
		567
		568	switch (aperture) {
		569	case 128 * 1024 * 1024:
		570	temp \|= (1 << 27);
		571	break;
		572	case 256 * 1024 * 1024:
		573	temp &= ~(1 << 27);
		574	break;
		575	default:
		576	device_printf(dev, "bad aperture size %d\n", aperture);
		577	return EINVAL;
		578	}
		579
		580	pci_write_config(sc->bdev, AGP_I915_GMADR, temp, 4);
		581	break;
506	}	582	}
507		583
508	return 0;	584	return 0;
Lines 525-531 Link Here
525	}	601	}
526	}	602	}
527		603
528	WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, physical \| 1);	604	if (sc->chiptype == CHIP_I915) {
		605	WRITEGTT(offset >> AGP_PAGE_SHIFT, physical \| 1);
		606	} else {
		607	WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, physical \| 1);
		608	}
		609
529	return 0;	610	return 0;
530	}	611	}
531		612
Lines 544-550 Link Here
544	}	625	}
545	}	626	}
546		627
547	WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, 0);	628	if (sc->chiptype == CHIP_I915) {
		629	WRITE4(offset >> AGP_PAGE_SHIFT, 0);
		630	} else {
		631	WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, 0);
		632	}
		633
548	return 0;	634	return 0;
549	}	635	}
550		636
Lines 669-676 Link Here
669	return EINVAL;	755	return EINVAL;
670		756
671	for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {	757	for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
672	WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4,	758	WRITE4(AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4,
673	i \| 3);	759	offset \| 3);
674	}	760	}
675		761
676	return 0;	762	return 0;