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Lines 566-572
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| 566 |
"\012APIC" /* SMP local APIC */ |
566 |
"\012APIC" /* SMP local APIC */ |
| 567 |
"\013oldMTRR" |
567 |
"\013oldMTRR" |
| 568 |
"\014SEP" |
568 |
"\014SEP" |
| 569 |
"\015MTRR" |
569 |
"\015MTRR" /* Memory Type Range Registers */ |
| 570 |
"\016PGE" /* PG_G (global bit) support */ |
570 |
"\016PGE" /* PG_G (global bit) support */ |
| 571 |
"\017MCA" |
571 |
"\017MCA" |
| 572 |
"\020CMOV" /* CMOV instruction */ |
572 |
"\020CMOV" /* CMOV instruction */ |
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Lines 961-1000
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| 961 |
static void |
961 |
static void |
| 962 |
print_AMD_features(u_int *regs) |
962 |
print_AMD_features(u_int *regs) |
| 963 |
{ |
963 |
{ |
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|
964 |
/* |
| 965 |
* Values taken from AMD Processor Recognition |
| 966 |
* http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf |
| 967 |
*/ |
| 964 |
do_cpuid(0x80000001, regs); |
968 |
do_cpuid(0x80000001, regs); |
| 965 |
printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature, |
969 |
printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature, |
| 966 |
"\020" /* in hex */ |
970 |
"\020" /* in hex */ |
| 967 |
"\001FPU" |
971 |
"\001FPU" /* Integral FPU */ |
| 968 |
"\002VME" |
972 |
"\002VME" /* Extended VM86 mode support */ |
| 969 |
"\003DE" |
973 |
"\003DE" /* Debug extensions */ |
| 970 |
"\004PSE" |
974 |
"\004PSE" /* 4MByte page tables */ |
| 971 |
"\005TSC" |
975 |
"\005TSC" /* Timestamp counter */ |
| 972 |
"\006MSR" |
976 |
"\006MSR" /* Machine specific registers */ |
| 973 |
"\007<b6>" |
977 |
"\007PAE" /* Physical address extension */ |
| 974 |
"\010MCE" |
978 |
"\010MCE" /* Machine Check support */ |
| 975 |
"\011CX8" |
979 |
"\011CX8" /* CMPEXCH8 instruction */ |
| 976 |
"\012<b9>" |
980 |
"\012APIC" /* SMP local APIC */ |
| 977 |
"\013<b10>" |
981 |
"\013<b10>" |
| 978 |
"\014SYSCALL" |
982 |
"\014SYSCALL" /* SYSENTER/SYSEXIT instructions */ |
| 979 |
"\015<b12>" |
983 |
"\015MTRR" /* Memory Type Range Registers */ |
| 980 |
"\016PGE" |
984 |
"\016PGE" /* PG_G (global bit) support */ |
| 981 |
"\017<b14>" |
985 |
"\017MCA" /* Machine Check Architecture */ |
| 982 |
"\020ICMOV" |
986 |
"\020ICMOV" /* CMOV instruction */ |
| 983 |
"\021FCMOV" |
987 |
"\021PAT" /* Page attributes table */ |
| 984 |
"\022<b17>" |
988 |
"\022PGE36" /* 36 bit address space support */ |
| 985 |
"\023<b18>" |
989 |
"\023<b18>" |
| 986 |
"\024<b19>" |
990 |
"\024<b19>" |
| 987 |
"\025<b20>" |
991 |
"\025<b20>" |
| 988 |
"\026<b21>" |
992 |
"\026<b21>" |
| 989 |
"\027<b22>" |
993 |
"\027AMX" /* AMD MMX Extensions */ |
| 990 |
"\030MMX" |
994 |
"\030MMX" |
| 991 |
"\031<b24>" |
995 |
"\031FXSAVE" /* FXSAVE/FXRSTOR */ |
| 992 |
"\032<b25>" |
996 |
"\032<b25>" |
| 993 |
"\033<b26>" |
997 |
"\033<b26>" |
| 994 |
"\034<b27>" |
998 |
"\034<b27>" |
| 995 |
"\035<b28>" |
999 |
"\035<b28>" |
| 996 |
"\036<b29>" |
1000 |
"\036<b29>" |
| 997 |
"\037<b30>" |
1001 |
"\0373DX" /* 3DNow! Extensions */ |
| 998 |
"\0403DNow!" |
1002 |
"\0403DNow!" |
| 999 |
); |
1003 |
); |
| 1000 |
} |
1004 |
} |