Attachment #7240 for bug #15845

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Lines 87-92 Link Here

(-)ed/if_ed.c (+155 lines)
87	static __inline void ed_xmit __P((struct ed_softc *));	87	static __inline void ed_xmit __P((struct ed_softc *));
88	static __inline char * ed_ring_copy __P((struct ed_softc , char , char *,	88	static __inline char * ed_ring_copy __P((struct ed_softc , char , char *,
89	/* u_short */ int));	89	/* u_short */ int));
		90	static int ed_rtl_set_media __P((struct ifnet *ifp));
		91	static void ed_rtl_get_media __P(( struct ifnet *ifp,
		92	struct ifmediareq *));
90	static void ed_hpp_set_physical_link __P((struct ed_softc *));	93	static void ed_hpp_set_physical_link __P((struct ed_softc *));
91	static void ed_hpp_readmem __P((struct ed_softc , int, unsigned char ,	94	static void ed_hpp_readmem __P((struct ed_softc , int, unsigned char ,
92	/* u_short */ int));	95	/* u_short */ int));
Lines 1139-1144 Link Here
1139	return ed_probe_Novell_generic(dev, flags);	1142	return ed_probe_Novell_generic(dev, flags);
1140	}	1143	}
1141		1144
		1145	int
		1146	ed_probe_Realtek(dev, port_rid, flags)
		1147	device_t dev;
		1148	int port_rid;
		1149	int flags;
		1150	{
		1151	struct ed_softc *sc = device_get_softc(dev);
		1152	int error;
		1153
		1154	if ((error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS)))
		1155	return (error);
		1156
		1157	if (!ed_probe_generic8390(sc))
		1158	return (ENXIO);
		1159
		1160	if (ed_nic_inb(sc, ED_P0_CR) & (ED_CR_PS0 \| ED_CR_PS1))
		1161	ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 \| ED_CR_STP);
		1162
		1163	if (ed_nic_inb(sc, ED_RTL80X9_80X9ID0) != 0x50)
		1164	return (ENXIO);
		1165
		1166	switch (ed_nic_inb(sc, ED_RTL80X9_80X9ID1)) {
		1167	case 0x70:
		1168	sc->chip_type = ED_CHIP_TYPE_RTL8019;
		1169	break;
		1170	case 0x43:
		1171	sc->chip_type = ED_CHIP_TYPE_RTL8029;
		1172	break;
		1173	default:
		1174	return (ENXIO);
		1175	}
		1176
		1177	sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
		1178	sc->nic_offset = ED_NOVELL_NIC_OFFSET;
		1179
		1180	if ((error = ed_probe_Novell_generic(dev, flags)))
		1181	return (error);
		1182
		1183	ifmedia_init(&sc->ifmedia, 0, ed_rtl_set_media, ed_rtl_get_media);
		1184
		1185	ifmedia_add(&sc->ifmedia, IFM_ETHER \| IFM_10_T \| IFM_FDX, 0, 0);
		1186	ifmedia_add(&sc->ifmedia, IFM_ETHER \| IFM_10_T, 0, 0);
		1187	ifmedia_add(&sc->ifmedia, IFM_ETHER \| IFM_10_2, 0, 0);
		1188	ifmedia_add(&sc->ifmedia, IFM_ETHER \| IFM_10_5, 0, 0);
		1189	ifmedia_add(&sc->ifmedia, IFM_ETHER \| IFM_AUTO, 0, 0);
		1190
		1191	ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 \| ED_CR_PAGE_3 \| ED_CR_STP);
		1192
		1193	switch (ed_nic_inb(sc, ED_RTL80X9_CONFIG2) & ED_RTL80X9_CF2_MEDIA) {
		1194	case ED_RTL80X9_CF2_AUTO:
		1195	ifmedia_set(&sc->ifmedia, IFM_ETHER \| IFM_AUTO);
		1196	break;
		1197	case ED_RTL80X9_CF2_10_5:
		1198	ifmedia_set(&sc->ifmedia, IFM_ETHER \| IFM_10_5);
		1199	break;
		1200	case ED_RTL80X9_CF2_10_2:
		1201	ifmedia_set(&sc->ifmedia, IFM_ETHER \| IFM_10_2);
		1202	break;
		1203	case ED_RTL80X9_CF2_10_T:
		1204	ifmedia_set(&sc->ifmedia, IFM_ETHER \| IFM_10_T \|
		1205	(ed_nic_inb(sc, ED_RTL80X9_CONFIG3)
		1206	& ED_RTL80X9_CF3_FUDUP) ? IFM_FDX : 0);
		1207	break;
		1208	}
1209	return (0);
1210	}
1211
1212	static int
1213	ed_rtl_set_media(ifp)
1214	struct ifnet *ifp;
1215	{
1216	struct ed_softc *sc;
1217	int spl;
1218
1219	sc = ifp->if_softc;
1220	spl = splimp();
1221	ed_nic_outb(sc, ED_P0_CR, sc->cr_proto \| ED_CR_PAGE_3
1222	\| (ed_nic_inb(sc, ED_P0_CR) & (ED_CR_STA \| ED_CR_STP)));
1223
1224	switch(IFM_SUBTYPE(sc->ifmedia.ifm_cur->ifm_media)) {
1225	case IFM_10_T:
1226	ed_nic_outb(sc, ED_RTL80X9_CONFIG2, ED_RTL80X9_CF2_10_T
1227	\| (ed_nic_inb(sc, ED_RTL80X9_CONFIG2)
1228	& ~ED_RTL80X9_CF2_MEDIA));
1229	break;
1230	case IFM_10_2:
1231	ed_nic_outb(sc, ED_RTL80X9_CONFIG2, ED_RTL80X9_CF2_10_2
1232	\| (ed_nic_inb(sc, ED_RTL80X9_CONFIG2)
1233	& ~ED_RTL80X9_CF2_MEDIA));
1234	break;
1235	case IFM_10_5:
1236	ed_nic_outb(sc, ED_RTL80X9_CONFIG2, ED_RTL80X9_CF2_10_5
1237	\| (ed_nic_inb(sc, ED_RTL80X9_CONFIG2)
1238	& ~ED_RTL80X9_CF2_MEDIA));
1239	break;
1240	case IFM_AUTO:
1241	ed_nic_outb(sc, ED_RTL80X9_CONFIG2, ED_RTL80X9_CF2_AUTO
1242	\| (ed_nic_inb(sc, ED_RTL80X9_CONFIG2)
1243	& ~ED_RTL80X9_CF2_MEDIA));
1244	break;
1245	}
1246
1247	ed_nic_outb(sc, ED_RTL80X9_CONFIG3,
1248	(sc->ifmedia.ifm_cur->ifm_media & IFM_FDX) ?
1249	(ed_nic_inb(sc, ED_RTL80X9_CONFIG3) \| ED_RTL80X9_CF3_FUDUP) :
1250	(ed_nic_inb(sc, ED_RTL80X9_CONFIG3) & ~ED_RTL80X9_CF3_FUDUP));
1251
1252	(void) splx(spl);
1253	return (0);
1254	}
1255
1256	static void
1257	ed_rtl_get_media(ifp, imr)
1258	struct ifnet *ifp;
1259	struct ifmediareq *imr;
1260	{
1261	struct ed_softc *sc;
1262	int spl;
1263
1264	sc = ifp->if_softc;
1265	imr->ifm_active = sc->ifmedia.ifm_cur->ifm_media;
1266
1267
1268	if (IFM_SUBTYPE(imr->ifm_active) == IFM_AUTO) {
1269	spl = splimp();
1270	ed_nic_outb(sc, ED_P0_CR, sc->cr_proto \| ED_CR_PAGE_3 \|
1271	(ed_nic_inb(sc, ED_P0_CR) & (ED_CR_STA \| ED_CR_STP)));
1272
1273	switch (ed_nic_inb(sc, ED_RTL80X9_CONFIG0)
1274	& (ED_CHIP_TYPE_RTL8029 ? ED_RTL80X9_CF0_BNC
1275	: (ED_RTL80X9_CF0_AUI \| ED_RTL80X9_CF0_BNC))) {
1276	case ED_RTL80X9_CF0_BNC:
1277	imr->ifm_active \|= IFM_10_2;
1278	break;
1279	case ED_RTL80X9_CF0_AUI:
1280	imr->ifm_active \|= IFM_10_5;
1281	break;
1282	default:
1283	imr->ifm_active \|= IFM_10_T;
1284	break;
1285	}
1286	(void) splx(spl);
1287	}
1288	imr->ifm_status = 0;
1289	}
1290
1142	#define ED_HPP_TEST_SIZE 16	1291	#define ED_HPP_TEST_SIZE 16
1143		1292
1144	/*	1293	/*
Lines 2587-2592 Link Here
2587		2736
2588	case SIOCGIFMEDIA:	2737	case SIOCGIFMEDIA:
2589	case SIOCSIFMEDIA:	2738	case SIOCSIFMEDIA:
		2739	if (sc->chip_type == ED_CHIP_TYPE_RTL8019 \|\|
		2740	sc->chip_type == ED_CHIP_TYPE_RTL8029) {
		2741
		2742	error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
		2743	break;
		2744	}
2590	if (sc->miibus == NULL) {	2745	if (sc->miibus == NULL) {
2591	error = EINVAL;	2746	error = EINVAL;
2592	break;	2747	break;

Lines 40-45 Link Here

(-)ed/if_ed_isa.c (+6 lines)
40	#include <net/if.h>	40	#include <net/if.h>
41	#include <net/if_arp.h>	41	#include <net/if_arp.h>
42	#include <net/if_mib.h>	42	#include <net/if_mib.h>
		43	#include <net/if_media.h>
43		44
44	#include <isa/isavar.h>	45	#include <isa/isavar.h>
45	#include <isa/pnpvar.h>	46	#include <isa/pnpvar.h>
Lines 93-98 Link Here
93	ed_release_resources(dev);	94	ed_release_resources(dev);
94		95
95	error = ed_probe_3Com(dev, 0, flags);	96	error = ed_probe_3Com(dev, 0, flags);
		97	if (error == 0)
		98	goto end;
		99	ed_release_resources(dev);
		100
		101	error = ed_probe_Realtek(dev, 0, flags);
96	if (error == 0)	102	if (error == 0)
97	goto end;	103	goto end;
98	ed_release_resources(dev);	104	ed_release_resources(dev);

Lines 35-40 Link Here

(-)ed/if_ed_pci.c (-1 / +6 lines)
35	#include <net/if.h>	35	#include <net/if.h>
36	#include <net/if_arp.h>	36	#include <net/if_arp.h>
37	#include <net/if_mib.h>	37	#include <net/if_mib.h>
		38	#include <net/if_media.h>
38		39
39	#include <pci/pcireg.h>	40	#include <pci/pcireg.h>
40	#include <pci/pcivar.h>	41	#include <pci/pcivar.h>
Lines 84-90 Link Here
84	int flags = 0;	85	int flags = 0;
85	int error;	86	int error;
86		87
87	error = ed_probe_Novell(dev, PCIR_MAPS, flags);	88	if (pci_get_devid(dev) == 0x802910ec)
		89	error = ed_probe_Realtek(dev, PCIR_MAPS, flags);
		90	else
		91	error = ed_probe_Novell(dev, PCIR_MAPS, flags);
		92
88	if (error)	93	if (error)
89	return (error);	94	return (error);
90		95




#define ED_CHIP_TYPE_DP8390	0x00
#define ED_CHIP_TYPE_WD790	0x01
#define ED_CHIP_TYPE_AX88190	0x02
#define ED_CHIP_TYPE_RTL8019	0x03
#define ED_CHIP_TYPE_RTL8029	0x04

/*
 * RTL8019/8029 Specific Registers
 */

#define ED_RTL80X9_CONFIG0	0x03
#define ED_RTL80X9_CONFIG2	0x05
#define ED_RTL80X9_CONFIG3	0x06
#define ED_RTL80X9_80X9ID0	0x0a
#define ED_RTL80X9_80X9ID1	0x0b

#define	ED_RTL80X9_CF0_BNC	0x04
#define ED_RTL80X9_CF0_AUI	0x20

#define ED_RTL80X9_CF2_MEDIA	0xc0
#define ED_RTL80X9_CF2_AUTO	0x00
#define ED_RTL80X9_CF2_10_T	0x40
#define ED_RTL80X9_CF2_10_5	0x80
#define ED_RTL80X9_CF2_10_2	0xc0

#define ED_RTL80X9_CF3_FUDUP	0x40

#define ED_CR_PAGE_3		0xc0

/*
 * AX88190 IOBASE registers.

Lines 90-95 Link Here

(-)ed/if_edvar.h (+3 lines)
90	u_char rec_page_stop; /* last page of RX ring-buffer */	90	u_char rec_page_stop; /* last page of RX ring-buffer */
91	u_char next_packet; /* pointer to next unread RX packet */	91	u_char next_packet; /* pointer to next unread RX packet */
92	struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */	92	struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */
		93
		94	struct ifmedia ifmedia; /* resource for media selection */
93	};	95	};
94		96
95	#define ed_nic_inb(sc, port) \	97	#define ed_nic_inb(sc, port) \
Lines 197-202 Link Here
197	int ed_probe_WD80x3 __P((device_t, int, int));	199	int ed_probe_WD80x3 __P((device_t, int, int));
198	int ed_probe_WD80x3_generic __P((device_t, int, unsigned short *[]));	200	int ed_probe_WD80x3_generic __P((device_t, int, unsigned short *[]));
199	int ed_probe_3Com __P((device_t, int, int));	201	int ed_probe_3Com __P((device_t, int, int));
		202	int ed_probe_Realtek __P((device_t, int, int));
200	int ed_probe_Novell __P((device_t, int, int));	203	int ed_probe_Novell __P((device_t, int, int));
201	int ed_probe_Novell_generic __P((device_t, int));	204	int ed_probe_Novell_generic __P((device_t, int));
202	int ed_probe_HP_pclanp __P((device_t, int, int));	205	int ed_probe_HP_pclanp __P((device_t, int, int));

Return to bug 15845

Lines 1107-1112 Link Here

(-)ed/if_edreg.h (+25 lines)
1107	#define ED_CHIP_TYPE_DP8390 0x00	1107	#define ED_CHIP_TYPE_DP8390 0x00
1108	#define ED_CHIP_TYPE_WD790 0x01	1108	#define ED_CHIP_TYPE_WD790 0x01
1109	#define ED_CHIP_TYPE_AX88190 0x02	1109	#define ED_CHIP_TYPE_AX88190 0x02
		1110	#define ED_CHIP_TYPE_RTL8019 0x03
		1111	#define ED_CHIP_TYPE_RTL8029 0x04
		1112
		1113	/*
		1114	* RTL8019/8029 Specific Registers
		1115	*/
		1116
		1117	#define ED_RTL80X9_CONFIG0 0x03
		1118	#define ED_RTL80X9_CONFIG2 0x05
		1119	#define ED_RTL80X9_CONFIG3 0x06
		1120	#define ED_RTL80X9_80X9ID0 0x0a
		1121	#define ED_RTL80X9_80X9ID1 0x0b
		1122
		1123	#define ED_RTL80X9_CF0_BNC 0x04
		1124	#define ED_RTL80X9_CF0_AUI 0x20
		1125
		1126	#define ED_RTL80X9_CF2_MEDIA 0xc0
		1127	#define ED_RTL80X9_CF2_AUTO 0x00
		1128	#define ED_RTL80X9_CF2_10_T 0x40
		1129	#define ED_RTL80X9_CF2_10_5 0x80
		1130	#define ED_RTL80X9_CF2_10_2 0xc0
		1131
		1132	#define ED_RTL80X9_CF3_FUDUP 0x40
		1133
		1134	#define ED_CR_PAGE_3 0xc0
1110		1135
1111	/*	1136	/*
1112	* AX88190 IOBASE registers.	1137	* AX88190 IOBASE registers.